* [Patch][edk2-platforms/devel-IntelAtomProcessorE3900 1Fix klocwork issues
@ 2018-08-23 5:32 Guo, Mang
0 siblings, 0 replies; only message in thread
From: Guo, Mang @ 2018-08-23 5:32 UTC (permalink / raw)
To: edk2-devel@lists.01.org
Cc: David Wei <david.wei@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Guo Mang <mang.guo@intel.com>
---
.../Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c | 2 +-
.../Smbios/SmBiosMiscDxe/MiscOemType0x94Function.c | 4 +--
.../PlatformPreMemPei/FvCallback.c | 4 +--
.../PlatformSetupDxe/SetupInfoRecords.c | 8 +++---
.../Common/PlatformSmm/Platform.c | 4 +--
.../IntelFsp2WrapperPkg/FspNotifyDxe/LoadBelow4G.c | 4 +--
.../BaseFspWrapperApiLib/FspWrapperApiLib.c | 10 ++++----
.../SampleCode/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c | 6 ++---
.../Cpu/SmmAccess/Dxe/SmmAccessDriver.c | 4 +--
.../Cpu/SmmAccess/Pei/SmmAccessDriver.c | 6 ++---
.../BaseConfigBlockLib/BaseConfigBlockLib.c | 10 ++++----
.../Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c | 4 +--
.../BroxtonSiPkg/Library/SideBandLib/SideBandLib.c | 4 +--
.../Universal/Variable/RuntimeDxe/Variable.c | 6 ++---
.../Library/BaseScSpiCommonLib/SpiCommon.c | 10 ++++----
.../Private/PeiDxeUsbCommonLib/UsbCommonLib.c | 4 +--
.../Library/ScPlatformLib/ScPlatformLibrary.c | 4 +--
.../SouthCluster/Reset/RuntimeDxe/ScReset.c | 14 +++++-----
.../BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c | 20 +++++++--------
.../BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScLpss.c | 14 +++++-----
.../SouthCluster/ScSmiDispatcher/Smm/ScSmmSx.c | 14 +++++-----
.../ScSmiDispatcher/Smm/ScxSmmHelpers.c | 30 +++++++++++-----------
.../BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c | 8 +++---
.../BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c | 24 ++++++++---------
24 files changed, 109 insertions(+), 109 deletions(-)
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c
index 6a4d675..4cc1e1f 100644
--- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c
+++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c
@@ -381,7 +381,7 @@ PlatformUpdateTables (
#if defined (IDCC2_SUPPORTED) && IDCC2_SUPPORTED
EFI_ACPI_ASPT_TABLE *pSpttTable;
#endif
- UINT16 NumberOfHpets;
+ UINT32 NumberOfHpets;
UINT16 HpetCapIdValue;
UINT32 HpetBlockID;
UINTN LocalApicCounter;
diff --git a/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscOemType0x94Function.c b/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscOemType0x94Function.c
index cce4bbe..b399a5f 100644
--- a/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscOemType0x94Function.c
+++ b/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscOemType0x94Function.c
@@ -165,7 +165,7 @@ EfiValueToString (
//
// Reverse temp string into Buffer.
//
- if (Width > 0 && (UINTN) (TempStr - TempBuffer) > Width) {
+ if (Width > 0 && ((UINTN)TempStr - (UINTN)TempBuffer) > Width) {
TempStr = TempBuffer + Width;
}
Index = 0;
@@ -241,7 +241,7 @@ EfiValueToHexStr (
//
// Reverse temp string into Buffer.
//
- if (Width > 0 && (UINTN) (TempStr - TempBuffer) > Width) {
+ if (Width > 0 && ((UINTN)TempStr - (UINTN)TempBuffer) > Width) {
TempStr = TempBuffer + Width;
}
Index = 0;
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/FvCallback.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/FvCallback.c
index 4a3a675..d5f514a 100644
--- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/FvCallback.c
+++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/FvCallback.c
@@ -1,7 +1,7 @@
/** @file
Locate and install Firmware Volume Hob's Once there is main memory.
- Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -158,7 +158,7 @@ CreateVariableHobs (
return EFI_INVALID_PARAMETER;
}
- VariableStoreBase = (EFI_PHYSICAL_ADDRESS) ((UINTN) NvStorageFvHeader + NvStorageFvHeader->HeaderLength);
+ VariableStoreBase = (EFI_PHYSICAL_ADDRESS) ((UINTN) NvStorageFvHeader + (UINTN)NvStorageFvHeader->HeaderLength);
VariableStoreHeader = (VARIABLE_STORE_HEADER *) (UINTN) VariableStoreBase;
DEBUG ((EFI_D_INFO, " VariableStoreHeader at 0x%x. VariableStoreSize = %d\n", VariableStoreHeader, (UINTN) VariableStoreHeader->Size));
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SetupInfoRecords.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SetupInfoRecords.c
index 0bb5f00..458131c 100644
--- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SetupInfoRecords.c
+++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SetupInfoRecords.c
@@ -192,7 +192,7 @@ EfiValueToString (
//
// Reverse temp string into Buffer.
//
- if (Width > 0 && (UINTN) (TempStr - TempBuffer) > Width) {
+ if (Width > 0 && ((UINTN)TempStr - (UINTN)TempBuffer) > Width) {
TempStr = TempBuffer + Width;
}
Index = 0;
@@ -270,7 +270,7 @@ EfiValueToHexStr (
//
// Reverse temp string into Buffer.
//
- if (Width > 0 && (UINTN) (TempStr - TempBuffer) > Width) {
+ if (Width > 0 && ((UINTN)TempStr - (UINTN)TempBuffer) > Width) {
TempStr = TempBuffer + Width;
}
Index = 0;
@@ -1298,10 +1298,10 @@ GetChipsetSataPortSpeed (
switch (PortNum) {
case 0:
- DeviceSpeed = *(volatile UINT32 *) (UINTN) (IdeAhciBar + R_SATA_AHCI_P0SSTS);
+ DeviceSpeed = *(volatile UINT32 *) (UINTN) (UINT32) (IdeAhciBar + R_SATA_AHCI_P0SSTS);
break;
case 1:
- DeviceSpeed = *(volatile UINT32 *) (UINTN) (IdeAhciBar + R_SATA_AHCI_P1SSTS);
+ DeviceSpeed = *(volatile UINT32 *) (UINTN) (UINT32) (IdeAhciBar + R_SATA_AHCI_P1SSTS);
break;
}
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSmm/Platform.c b/Platform/BroxtonPlatformPkg/Common/PlatformSmm/Platform.c
index 024384f..15014b0 100644
--- a/Platform/BroxtonPlatformPkg/Common/PlatformSmm/Platform.c
+++ b/Platform/BroxtonPlatformPkg/Common/PlatformSmm/Platform.c
@@ -1,7 +1,7 @@
/** @file
This is a generic template for a child of the IchSmm driver.
- Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -1058,7 +1058,7 @@ BcdToHex(
UINTN HighByte;
UINTN LowByte;
- HighByte = (UINTN) ((BcdValue >> 4) * 10);
+ HighByte = (UINTN)(UINT32)((BcdValue >> 4) * 10);
LowByte = (UINTN) (BcdValue & 0x0F);
return ((UINT8) (LowByte + HighByte));
diff --git a/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/FspNotifyDxe/LoadBelow4G.c b/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/FspNotifyDxe/LoadBelow4G.c
index c055c7f..a969bdf 100644
--- a/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/FspNotifyDxe/LoadBelow4G.c
+++ b/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/FspNotifyDxe/LoadBelow4G.c
@@ -1,5 +1,5 @@
/** @file
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -113,7 +113,7 @@ RelocateImageUnder4GIfNeeded (
// Align buffer on section boundry
//
ImageContext.ImageAddress += ImageContext.SectionAlignment - 1;
- ImageContext.ImageAddress &= ~((EFI_PHYSICAL_ADDRESS) (ImageContext.SectionAlignment - 1));
+ ImageContext.ImageAddress &= ~((EFI_PHYSICAL_ADDRESS)(UINT32) (ImageContext.SectionAlignment - 1));
//
// Load the image to our new buffer
//
diff --git a/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c b/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
index f763f86..e33444b 100644
--- a/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
+++ b/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
@@ -1,7 +1,7 @@
/** @file
Provide FSP API related function.
- Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -106,7 +106,7 @@ CallFspNotifyPhase (
return EFI_DEVICE_ERROR;
}
- NotifyPhaseApi = (FSP_NOTIFY_PHASE) (UINTN) (FspHeader->ImageBase + FspHeader->NotifyPhaseEntryOffset);
+ NotifyPhaseApi = (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase + (UINTN)FspHeader->NotifyPhaseEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
Status = Execute32BitCode ((UINTN) NotifyPhaseApi, (UINTN) NotifyPhaseParams, (UINTN) NULL);
SetInterruptState (InterruptState);
@@ -139,7 +139,7 @@ CallFspMemoryInit (
return EFI_DEVICE_ERROR;
}
- FspMemoryInitApi = (FSP_MEMORY_INIT) (UINTN) (FspHeader->ImageBase + FspHeader->FspMemoryInitEntryOffset);
+ FspMemoryInitApi = (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase + (UINTN)FspHeader->FspMemoryInitEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
Status = Execute32BitCode ((UINTN) FspMemoryInitApi, (UINTN) FspmUpdDataPtr, (UINTN) HobListPtr);
SetInterruptState (InterruptState);
@@ -171,7 +171,7 @@ CallTempRamExit (
return EFI_DEVICE_ERROR;
}
- TempRamExitApi = (FSP_TEMP_RAM_EXIT) (UINTN) (FspHeader->ImageBase + FspHeader->TempRamExitEntryOffset);
+ TempRamExitApi = (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase + (UINTN)FspHeader->TempRamExitEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
DEBUG ((DEBUG_INFO, "** calling TempRamExitApi\n"));
@@ -210,7 +210,7 @@ CallFspSiliconInit (
}
DEBUG ((DEBUG_INFO, "FspHeader = 0x%X\n", FspHeader));
- FspSiliconInitApi = (FSP_SILICON_INIT) (UINTN) (FspHeader->ImageBase + FspHeader->FspSiliconInitEntryOffset);
+ FspSiliconInitApi = (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase + (UINTN)FspHeader->FspSiliconInitEntryOffset);
DEBUG ((DEBUG_INFO, "FspSiliconInitApi = 0x%X\n", FspSiliconInitApi));
InterruptState = SaveAndDisableInterrupts ();
diff --git a/Platform/BroxtonPlatformPkg/Common/SampleCode/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c b/Platform/BroxtonPlatformPkg/Common/SampleCode/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c
index 12e5566..8be6d2f 100644
--- a/Platform/BroxtonPlatformPkg/Common/SampleCode/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c
+++ b/Platform/BroxtonPlatformPkg/Common/SampleCode/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c
@@ -1,7 +1,7 @@
/** @file
This implementation of EFI_PXE_BASE_CODE_PROTOCOL and EFI_LOAD_FILE_PROTOCOL.
- Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -148,8 +148,8 @@ EfiPxeBcStart (
//
// Configure block size for TFTP as a default value to handle all link layers.
//
- Private->BlockSize = (UINTN) (Private->Ip4MaxPacketSize -
- PXEBC_DEFAULT_UDP_OVERHEAD_SIZE - PXEBC_DEFAULT_TFTP_OVERHEAD_SIZE);
+ Private->BlockSize = (UINTN)Private->Ip4MaxPacketSize -
+ PXEBC_DEFAULT_UDP_OVERHEAD_SIZE - PXEBC_DEFAULT_TFTP_OVERHEAD_SIZE;
//
// PXE over IPv4 starts here, initialize the fields.
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Dxe/SmmAccessDriver.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Dxe/SmmAccessDriver.c
index 0167024..33b3027 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Dxe/SmmAccessDriver.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Dxe/SmmAccessDriver.c
@@ -2,7 +2,7 @@
This is the driver that publishes the SMM Access Protocol
instance for System Agent.
- Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -182,7 +182,7 @@ Close (
}
SmmAccess->SmramDesc[Index].RegionState &= ~EFI_SMRAM_OPEN;
- SmmAccess->SmramDesc[Index].RegionState |= (EFI_SMRAM_CLOSED |EFI_ALLOCATED);
+ SmmAccess->SmramDesc[Index].RegionState |= (UINTN)(EFI_SMRAM_CLOSED |EFI_ALLOCATED);
}
SmmAccess->SmmAccess.OpenState = FALSE;
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Pei/SmmAccessDriver.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Pei/SmmAccessDriver.c
index 6341f8e..39a77f4 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Pei/SmmAccessDriver.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Pei/SmmAccessDriver.c
@@ -2,7 +2,7 @@
This is the driver that publishes the SMM Access Protocol
instance for System Agent.
- Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -146,7 +146,7 @@ Open (
//
// END CHIPSET SPECIFIC CODE
//
- SmmAccess->SmramDesc[DescriptorIndex].RegionState &= ~(EFI_SMRAM_CLOSED | EFI_ALLOCATED);
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState &= (UINTN) (~(EFI_SMRAM_CLOSED | EFI_ALLOCATED));
SmmAccess->SmramDesc[DescriptorIndex].RegionState |= EFI_SMRAM_OPEN;
SmmAccess->SmmAccess.OpenState = TRUE;
@@ -191,7 +191,7 @@ Close (
}
SmmAccess->SmramDesc[DescriptorIndex].RegionState &= ~EFI_SMRAM_OPEN;
- SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (EFI_SMRAM_CLOSED | EFI_ALLOCATED);
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINTN)(EFI_SMRAM_CLOSED | EFI_ALLOCATED);
SmmAccess->SmmAccess.OpenState = FALSE;
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.c
index 5a1dfa5..3e089bf 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.c
@@ -1,7 +1,7 @@
/** @file
Library functions for Config Block management.
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -132,7 +132,7 @@ AddConfigBlock (
}
OffsetIndex = NumOfBlocks - ConfigBlkTblAddrPtr->AvailableBlocks;
- OffsetTblPtr = (UINT32 *) ((UINTN) ConfigBlkTblAddrPtr + ConfigBlkTblHdrSize + (UINTN) ((OffsetIndex) * 4));
+ OffsetTblPtr = (UINT32 *) ((UINTN) ConfigBlkTblAddrPtr + ConfigBlkTblHdrSize + (((UINTN)OffsetIndex) * 4));
if (OffsetIndex == 0) {
LastUsedOffset = 0;
} else {
@@ -144,7 +144,7 @@ AddConfigBlock (
ConfigBlkTblAddrPtr->AvailableBlocks--;
ConfigBlkTblAddrPtr->AvailableSize = ConfigBlkTblAddrPtr->AvailableSize - ConfigBlkSize;
- TempConfigBlk = (CONFIG_BLOCK *) ((UINTN) ConfigBlkTblAddrPtr + ConfigBlkTblHdrSize + (UINTN) (NumOfBlocks * 4) + LastUsedOffset);
+ TempConfigBlk = (CONFIG_BLOCK *) ((UINTN) ConfigBlkTblAddrPtr + (UINTN) ConfigBlkTblHdrSize + (UINTN) (NumOfBlocks * 4) + (UINTN) LastUsedOffset);
TempConfigBlk->Header.Size = ConfigBlkSize;
TempConfigBlk->Header.Revision = ConfigBlkAddrPtr->Header.Revision;
TempConfigBlk->Header.Guid = ConfigBlkAddrPtr->Header.Guid;
@@ -191,12 +191,12 @@ GetConfigBlock (
ConfigBlkOffset = 0;
for (OffsetIndex = 0; OffsetIndex < NumOfBlocks; OffsetIndex++) {
- TempConfigBlk = (CONFIG_BLOCK *) ((UINTN) ConfigBlkTblAddrPtr + (UINTN) ConfigBlkTblHdrSize + (UINTN) (NumOfBlocks * 4) + (UINTN) ConfigBlkOffset);
+ TempConfigBlk = (CONFIG_BLOCK *) ((UINTN) ConfigBlkTblAddrPtr + (UINTN) ConfigBlkTblHdrSize + ((UINTN)NumOfBlocks * 4) + (UINTN) ConfigBlkOffset);
if (CompareGuid (&(TempConfigBlk->Header.Guid), ConfigBlockGuid)) {
*ConfigBlockAddress = (VOID *) TempConfigBlk;
return EFI_SUCCESS;
}
- OffsetTblPtr = (UINT32 *) ((UINTN) ConfigBlkTblAddrPtr + ConfigBlkTblHdrSize + (UINTN) (OffsetIndex * 4));
+ OffsetTblPtr = (UINT32 *) ((UINTN) ConfigBlkTblAddrPtr + ConfigBlkTblHdrSize + ((UINTN)OffsetIndex * 4));
ConfigBlkOffset = *OffsetTblPtr;
}
DEBUG ((DEBUG_ERROR, "Could not find the config block.\n"));
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c
index 7cb0556..1522b23 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c
@@ -1,7 +1,7 @@
/** @file
This file contains routines that get PCI Express Address.
- Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -41,7 +41,7 @@ MmPciBase (
// Use local variable PcieAddress here. This library is for PEI\DXE\SMM
// When PEI, the module variable can't be updated. Need a local variable to get the pcie base address + offset.
//
- PcieAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN) ((Bus << 20) + (Device << 15) + (Function << 12));
+ PcieAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN)(UINT32) ((Bus << 20) + (Device << 15) + (Function << 12));
return PcieAddress;
}
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/SideBandLib/SideBandLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/SideBandLib/SideBandLib.c
index 89303fe..83e023d 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/SideBandLib/SideBandLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/SideBandLib/SideBandLib.c
@@ -2,7 +2,7 @@
This file contains the implementation of SideBandLib library.
The library exposes an abstract interface to the SoC SideBand network.
- Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -70,7 +70,7 @@ GetSideBandMmioAddress (
{
UINT32 Temp = MmioRead32 (P2SB_PCI_MM_BASE + R_P2SB_BASE) & 0xff000000;
Temp |= TargetPortId << 16;
- Temp |= TargetRegister;
+ Temp |= (UINT32)TargetRegister;
return Temp;
}
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
index 316e5c7..6383442 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
@@ -16,7 +16,7 @@
VariableServiceSetVariable() should also check authenticate data to avoid buffer overflow,
integer overflow. It should also check attribute to avoid authentication bypass.
- Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -1413,7 +1413,7 @@ Reclaim (
CurrPtr += NewVariableSize;
}
- *LastVariableOffset = (UINTN) (CurrPtr - ValidBuffer);
+ *LastVariableOffset = ((UINTN)CurrPtr - (UINTN)ValidBuffer);
if (IsVolatile) {
//
// If volatile variable store, just copy valid buffer.
@@ -4759,7 +4759,7 @@ VariableCommonInitialize (
GuidHob = GetFirstGuidHob (VariableGuid);
if (GuidHob != NULL) {
VariableStoreHeader = GET_GUID_HOB_DATA (GuidHob);
- VariableStoreLength = (UINT64) (GuidHob->Header.HobLength - sizeof (EFI_HOB_GUID_TYPE));
+ VariableStoreLength = (UINT64)(UINT32)(GuidHob->Header.HobLength - sizeof (EFI_HOB_GUID_TYPE));
if (GetVariableStoreStatus (VariableStoreHeader) == EfiValid) {
mVariableModuleGlobal->VariableGlobal.HobVariableBase = (EFI_PHYSICAL_ADDRESS) (UINTN) AllocateRuntimeCopyPool ((UINTN) VariableStoreLength, (VOID *) VariableStoreHeader);
if (mVariableModuleGlobal->VariableGlobal.HobVariableBase == 0) {
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c
index 4240fd5..c1fa73d 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c
@@ -158,7 +158,7 @@ PchPmTimerStallRuntimeSafe (
return;
}
- OriginalTick = IoRead32 ((UINTN) (ABase + R_ACPI_PM1_TMR)) & B_ACPI_PM1_TMR_VAL;
+ OriginalTick = IoRead32 ((UINTN)(UINT16)(ABase + R_ACPI_PM1_TMR)) & B_ACPI_PM1_TMR_VAL;
CurrentTick = OriginalTick;
//
@@ -181,7 +181,7 @@ PchPmTimerStallRuntimeSafe (
// one I/O operation, and maybe generate SMI
//
while ((Counts != 0) || (RemainingTick > CurrentTick)) {
- CurrentTick = IoRead32 ((UINTN) (ABase + R_ACPI_PM1_TMR)) & B_ACPI_PM1_TMR_VAL;
+ CurrentTick = IoRead32 ((UINTN)(UINT16)(ABase + R_ACPI_PM1_TMR)) & B_ACPI_PM1_TMR_VAL;
//
// Check if timer overflow
//
@@ -625,8 +625,8 @@ SendSpiCmd (
// whose SMI handlers access flash before flash cycle and re-enabling the SMI
// sources after the flash cycle .
//
- SmiEnSave = IoRead32 ((UINTN) (ABase + R_SMI_EN));
- IoWrite32 ((UINTN) (ABase + R_SMI_EN), SmiEnSave & (UINT32) (~B_SMI_EN_GBL_SMI));
+ SmiEnSave = IoRead32 ((UINTN)(UINT16)(ABase + R_SMI_EN));
+ IoWrite32 ((UINTN) (UINT16) (ABase + R_SMI_EN), SmiEnSave & (UINT32) (~B_SMI_EN_GBL_SMI));
BiosCtlSave = MmioRead8 (SpiBaseAddress + R_SPI_BCR) & B_SPI_BCR_SRC;
//
@@ -947,7 +947,7 @@ SendSpiCmdEnd:
//
// Restore SMIs.
//
- IoWrite32 ((UINTN) (ABase + R_SMI_EN), SmiEnSave);
+ IoWrite32 ((UINTN)(UINT16) (ABase + R_SMI_EN), SmiEnSave);
ReleaseSpiBar0 (SpiInstance);
return Status;
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeUsbCommonLib/UsbCommonLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeUsbCommonLib/UsbCommonLib.c
index f7a2a4a..8f9203b 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeUsbCommonLib/UsbCommonLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeUsbCommonLib/UsbCommonLib.c
@@ -1,7 +1,7 @@
/** @file
Initializes USB Controllers.
- Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -804,7 +804,7 @@ CommonXhciHcInit (
BitMask = (UINT32) (BIT29);
BitValue = 0;
Status = ScMmioPoll32 (
- (UINTN) (XhciMmioBase + R_XHCI_MEM_DUAL_ROLE_CFG1),
+ (UINTN) (UINT32) (XhciMmioBase + R_XHCI_MEM_DUAL_ROLE_CFG1),
BitMask,
BitValue,
50
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.c
index afc744a..e2018e6 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.c
@@ -1,7 +1,7 @@
/** @file
SC Platform Lib implementation.
- Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -92,7 +92,7 @@ ScPmTimerStall (
//
AcpiBaseAddr = (UINT16)PcdGet16(PcdScAcpiIoPortBaseAddress);
- OriginalTick = IoRead32 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_TMR)) & B_ACPI_PM1_TMR_VAL;
+ OriginalTick = IoRead32 ((UINTN)(UINT32)(AcpiBaseAddr + R_ACPI_PM1_TMR)) & B_ACPI_PM1_TMR_VAL;
CurrentTick = OriginalTick;
//
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Reset/RuntimeDxe/ScReset.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Reset/RuntimeDxe/ScReset.c
index 96dd4f7..ca7c89b 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Reset/RuntimeDxe/ScReset.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Reset/RuntimeDxe/ScReset.c
@@ -1,7 +1,7 @@
/** @file
Reset Architectural Protocol implementation.
- Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -307,7 +307,7 @@ IntelScResetSystem (
//
Data16 = 0;
- IoWrite16 ((UINTN) (AcpiBase + R_ACPI_GPE0a_EN), Data16);
+ IoWrite16 ((UINTN) (UINT16) (AcpiBase + R_ACPI_GPE0a_EN), Data16);
//
// Clear Sleep SMI Status
@@ -332,19 +332,19 @@ IntelScResetSystem (
// Clear it through SMI Status register
//
Data16 = B_SMI_STS_PM1_STS_REG;
- IoWrite16 ((UINTN) (AcpiBase + R_SMI_STS), Data16);
+ IoWrite16 ((UINTN) (UINT16) (AcpiBase + R_SMI_STS), Data16);
//
// Finally, transform system into S5 sleep state
//
- Data32 = IoRead32 ((UINTN) (AcpiBase + R_ACPI_PM1_CNT));
- Data32 = (UINT32) ((Data32 & ~(B_ACPI_PM1_CNT_SLP_TYP + B_ACPI_PM1_CNT_SLP_EN)) | V_ACPI_PM1_CNT_S5);
+ Data32 = IoRead32 ((UINTN) (UINT16) (AcpiBase + R_ACPI_PM1_CNT));
+ Data32 = (UINT32)((Data32 & ~(B_ACPI_PM1_CNT_SLP_TYP + B_ACPI_PM1_CNT_SLP_EN)) | V_ACPI_PM1_CNT_S5);
- IoWrite32 ((UINTN) (AcpiBase + R_ACPI_PM1_CNT), Data32);
+ IoWrite32 ((UINTN) (UINT16) (AcpiBase + R_ACPI_PM1_CNT), Data32);
Data32 = Data32 | B_ACPI_PM1_CNT_SLP_EN;
- IoWrite32 ((UINTN) (AcpiBase + R_ACPI_PM1_CNT), Data32);
+ IoWrite32 ((UINTN) (UINT16) (AcpiBase + R_ACPI_PM1_CNT), Data32);
//
// Should not return
//
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c
index ebb424b..abf9cc4 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c
@@ -1,7 +1,7 @@
/** @file
This is the driver that initializes the Intel SC devices
- Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -670,14 +670,14 @@ ScOnEndOfDxe (
FuncDisableReg = MmioRead32 (PmcBase + R_PMC_FUNC_DIS);
MmioAnd32 (
- (UINTN) (PmcBase + R_PMC_PMIR),
+ (UINTN) (UINT32) (PmcBase + R_PMC_PMIR),
(UINT32) ~(B_PMC_PMIR_CF9GR)
);
S3BootScriptSaveMemWrite (
EfiBootScriptWidthUint32,
- (UINTN) (PmcBase + R_PMC_PMIR),
+ (UINTN) (UINT32) (PmcBase + R_PMC_PMIR),
1,
- (VOID *) (UINTN) (PmcBase + R_PMC_PMIR)
+ (VOID *) (UINTN) (UINT32) (PmcBase + R_PMC_PMIR)
);
if (BxtSeries == BxtP){
@@ -700,24 +700,24 @@ ScOnEndOfDxe (
//
// Save Global SMI Enable bit setting before BIOS enables SMI_LOCK during S3 resume
//
- Data32Or = IoRead32 ((UINTN) (AcpiBaseAddr + R_SMI_EN));
+ Data32Or = IoRead32 ((UINTN) (UINT16) (AcpiBaseAddr + R_SMI_EN));
if ((Data32Or & B_SMI_EN_GBL_SMI) != 0) {
Data32And = 0xFFFFFFFF;
Data32Or &= B_SMI_EN_GBL_SMI;
S3BootScriptSaveIoReadWrite (
EfiBootScriptWidthUint32,
- (UINTN) (AcpiBaseAddr + R_SMI_EN),
+ (UINTN) (UINT16) (AcpiBaseAddr + R_SMI_EN),
&Data32Or, // Data to be ORed
&Data32And // Data to be ANDed
);
}
- MmioOr8 ((UINTN) (PmcBase + R_PMC_GEN_PMCON_2), B_PMC_GEN_PMCON_SMI_LOCK);
+ MmioOr8 ((UINTN) (UINT32) (PmcBase + R_PMC_GEN_PMCON_2), B_PMC_GEN_PMCON_SMI_LOCK);
S3BootScriptSaveMemWrite (
EfiBootScriptWidthUint8,
- (UINTN) (PmcBase + R_PMC_GEN_PMCON_2),
+ (UINTN) (UINT32) (PmcBase + R_PMC_GEN_PMCON_2),
1,
- (VOID *) (UINTN) (PmcBase + R_PMC_GEN_PMCON_2)
+ (VOID *)(UINTN) (UINT32) (PmcBase + R_PMC_GEN_PMCON_2)
);
}
@@ -818,7 +818,7 @@ ScOnEndOfDxe (
S3BootScriptSaveIoReadWrite (
EfiBootScriptWidthUint16,
- (UINTN) (AcpiBaseAddr + R_TCO_CNT),
+ (UINTN) (UINT16) (AcpiBaseAddr + R_TCO_CNT),
&Data16Or, // Data to be ORed
&Data16And // Data to be ANDed
);
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScLpss.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScLpss.c
index 593db98..6ce0a0d 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScLpss.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScLpss.c
@@ -1,7 +1,7 @@
/** @file
Initializes SC LPSS Devices.
- Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -130,8 +130,8 @@ ConfigureLpssAtBoot (
//
// Assume the MMIO address for BAR0 is always 32 bits (high DW is 0).
//
- MmioWrite32 ((UINTN) (LpssMmioBase0 + R_LPSS_IO_REMAP_ADDRESS_LOW), LpssMmioBase0);
- MmioWrite32 ((UINTN) (LpssMmioBase0 + R_LPSS_IO_REMAP_ADDRESS_HI), LpssMmioBase0_High);
+ MmioWrite32 ((UINTN) (UINT32) (LpssMmioBase0 + R_LPSS_IO_REMAP_ADDRESS_LOW), LpssMmioBase0);
+ MmioWrite32 ((UINTN) (UINT32) (LpssMmioBase0 + R_LPSS_IO_REMAP_ADDRESS_HI), LpssMmioBase0_High);
DEBUG ((DEBUG_INFO, "Read back LPSS REMAP Register, High DW = 0x%x, Low DW = 0x%x, Index = %d\n",
MmioRead32 ((UINTN) (LpssMmioBase0 + R_LPSS_IO_REMAP_ADDRESS_HI)),
@@ -262,18 +262,18 @@ StopLpssAtBoot (
if ((mLpssIoDevices[Index].PciDeviceNum == PCI_DEVICE_NUMBER_LPSS_I2C0) || \
(mLpssIoDevices[Index].PciDeviceNum == PCI_DEVICE_NUMBER_LPSS_I2C1)) {
- D32 = MmioRead32 ((UINTN) (LpssMmioBase0 + R_LPSS_I2C_IC_ENABLE));
+ D32 = MmioRead32 ((UINTN) (UINT32) (LpssMmioBase0 + R_LPSS_I2C_IC_ENABLE));
if (D32 & B_LPSS_I2C_IC_ENABLE_ENABLE) {
DEBUG ((DEBUG_INFO, "Stop I2C controller D:%02X, F: %02X...\n", mLpssIoDevices[Index].PciDeviceNum, mLpssIoDevices[Index].PciFuncNum));
MmioWrite32 ((UINTN) LpssMmioBase0 + R_LPSS_I2C_IC_ENABLE, \
- MmioRead32 ((UINTN) (LpssMmioBase0 + R_LPSS_I2C_IC_ENABLE)) & (~(UINT32) B_LPSS_I2C_IC_ENABLE_ENABLE));
+ MmioRead32 ((UINTN) (UINT32) (LpssMmioBase0 + R_LPSS_I2C_IC_ENABLE)) & (~(UINT32) B_LPSS_I2C_IC_ENABLE_ENABLE));
}
} else if (mLpssIoDevices[Index].PciDeviceNum == PCI_DEVICE_NUMBER_LPSS_SPI) {
- D32 = MmioRead32 ((UINTN) (LpssMmioBase0 + R_LPSS_SPI_MEM_SSP_CONTROL0));
+ D32 = MmioRead32 ((UINTN) (UINT32) (LpssMmioBase0 + R_LPSS_SPI_MEM_SSP_CONTROL0));
if (D32 & B_LPSS_SPI_MEM_SSP_CONTROL0_SSE) {
DEBUG ((DEBUG_INFO, "Stop SPI controller D:%02X, F: %02X...\n", mLpssIoDevices[Index].PciDeviceNum, mLpssIoDevices[Index].PciFuncNum));
MmioWrite32 ((UINTN) LpssMmioBase0 + R_LPSS_SPI_MEM_SSP_CONTROL0, \
- MmioRead32 ((UINTN) (LpssMmioBase0 + R_LPSS_SPI_MEM_SSP_CONTROL0)) & (~(UINT32) B_LPSS_SPI_MEM_SSP_CONTROL0_SSE));
+ MmioRead32 ((UINTN) (UINT32) (LpssMmioBase0 + R_LPSS_SPI_MEM_SSP_CONTROL0)) & (~(UINT32) B_LPSS_SPI_MEM_SSP_CONTROL0_SSE));
}
}
}
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmSx.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmSx.c
index 8baf1c0..f860320 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmSx.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmSx.c
@@ -1,7 +1,7 @@
/** @file
File to contain all the hardware specific stuff for the Smm Sx dispatch protocol.
- Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -64,7 +64,7 @@ SxGetContext (
{
UINT32 Pm1Cnt;
- Pm1Cnt = IoRead32 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_CNT));
+ Pm1Cnt = IoRead32(((UINTN) AcpiBaseAddr + R_ACPI_PM1_CNT));
//
// By design, the context phase will always be ENTRY
@@ -199,7 +199,7 @@ ScSmmSxGoToSleep (
//
// Get Power Management 1 Control Register Value
//
- Pm1Cnt = IoRead32 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_CNT));
+ Pm1Cnt = IoRead32 (((UINTN) AcpiBaseAddr + R_ACPI_PM1_CNT));
if (((Pm1Cnt & B_ACPI_PM1_CNT_SLP_TYP) == V_ACPI_PM1_CNT_S3) ||
((Pm1Cnt & B_ACPI_PM1_CNT_SLP_TYP) == V_ACPI_PM1_CNT_S4) ||
@@ -229,13 +229,13 @@ ScSmmSxGoToSleep (
// Now that SMIs are disabled, write to the SLP_EN bit again to trigger the sleep
//
Pm1Cnt |= B_ACPI_PM1_CNT_SLP_EN;
- IoWrite32 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_CNT), Pm1Cnt);
+ IoWrite32 (((UINTN) AcpiBaseAddr + R_ACPI_PM1_CNT), Pm1Cnt);
//
// Should only proceed if wake event is generated.
//
if ((Pm1Cnt & B_ACPI_PM1_CNT_SLP_TYP) == V_ACPI_PM1_CNT_S1) {
- while (((IoRead16 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_STS))) & B_ACPI_PM1_STS_WAK) == 0x0);
+ while (((IoRead16 (((UINTN) AcpiBaseAddr + R_ACPI_PM1_STS))) & B_ACPI_PM1_STS_WAK) == 0x0);
} else {
CpuDeadLoop ();
}
@@ -244,7 +244,7 @@ ScSmmSxGoToSleep (
// The system just went to sleep. If the sleep state was S1, then code execution will resume
// here when the system wakes up.
//
- Pm1Cnt = IoRead32 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_CNT));
+ Pm1Cnt = IoRead32 (((UINTN) AcpiBaseAddr + R_ACPI_PM1_CNT));
if ((Pm1Cnt & B_ACPI_PM1_CNT_SCI_EN) == 0) {
//
@@ -253,7 +253,7 @@ ScSmmSxGoToSleep (
Pm1Cnt &= ~B_ACPI_PM1_CNT_SLP_TYP;
Pm1Cnt |= V_ACPI_PM1_CNT_S0;
- IoWrite32 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_CNT), Pm1Cnt);
+ IoWrite32 (((UINTN) AcpiBaseAddr + R_ACPI_PM1_CNT), Pm1Cnt);
}
ScSmmClearSource (&SX_SOURCE_DESC);
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScxSmmHelpers.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScxSmmHelpers.c
index ef81449..c85463f 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScxSmmHelpers.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScxSmmHelpers.c
@@ -2,7 +2,7 @@
This driver is responsible for the registration of child drivers
and the abstraction of the SC SMI sources.
- Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -90,13 +90,13 @@ ScSmmEnableGlobalSmiBit (
{
UINT32 SmiEn;
- SmiEn = IoRead32 ((UINTN) (AcpiBaseAddr + R_SMI_EN));
+ SmiEn = IoRead32 (((UINTN)AcpiBaseAddr + R_SMI_EN));
//
// Set the "global smi enable" bit
//
SmiEn |= B_SMI_EN_GBL_SMI;
- IoWrite32 ((UINTN) (AcpiBaseAddr + R_SMI_EN), SmiEn);
+ IoWrite32 (((UINTN)AcpiBaseAddr + R_SMI_EN), SmiEn);
return EFI_SUCCESS;
}
@@ -129,14 +129,14 @@ ScSmmClearSmi (
//
// Determine whether an ACPI OS is present (via the SCI_EN bit)
//
- Pm1Cnt = IoRead32 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_CNT));
+ Pm1Cnt = IoRead32 (((UINTN)AcpiBaseAddr + R_ACPI_PM1_CNT));
SciEn = (BOOLEAN) ((Pm1Cnt & B_ACPI_PM1_CNT_SCI_EN) == B_ACPI_PM1_CNT_SCI_EN);
if (!SciEn) {
//
// Clear any SMIs that double as SCIs (when SCI_EN==0)
//
- Pm1Sts = IoRead16 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_STS));
- Gpe0aStsLow = IoRead32 ((UINTN) (AcpiBaseAddr + R_ACPI_GPE0a_STS));
+ Pm1Sts = IoRead16 (((UINTN)AcpiBaseAddr + R_ACPI_PM1_STS));
+ Gpe0aStsLow = IoRead32 (((UINTN)AcpiBaseAddr + R_ACPI_GPE0a_STS));
Pm1Sts |=
(
@@ -167,15 +167,15 @@ ScSmmClearSmi (
B_ACPI_GPE0a_STS_HOT_PLUG
);
- IoWrite16 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_STS), (UINT16) Pm1Sts);
- IoWrite32 ((UINTN) (AcpiBaseAddr + R_ACPI_GPE0a_STS), (UINT32) Gpe0aStsLow);
+ IoWrite16 (((UINTN)AcpiBaseAddr + R_ACPI_PM1_STS), (UINT16) Pm1Sts);
+ IoWrite32 (((UINTN)AcpiBaseAddr + R_ACPI_GPE0a_STS), (UINT32) Gpe0aStsLow);
}
//
// Clear all SMIs that are unaffected by SCI_EN
//
- SmiSts = IoRead32 ((UINTN) (AcpiBaseAddr + R_SMI_STS));
- TcoSts = IoRead32 ((UINTN) (AcpiBaseAddr + R_TCO_STS));
+ SmiSts = IoRead32 (((UINTN)AcpiBaseAddr + R_SMI_STS));
+ TcoSts = IoRead32 (((UINTN)AcpiBaseAddr + R_TCO_STS));
SmiSts |=
(
@@ -194,7 +194,7 @@ ScSmmClearSmi (
);
GpioClearAllGpiSmiSts ();
- IoWrite32 ((UINTN) (AcpiBaseAddr + R_SMI_STS), SmiSts);
+ IoWrite32 (((UINTN)AcpiBaseAddr + R_SMI_STS), SmiSts);
//
// Try to clear the EOS bit. ASSERT on an error
@@ -220,18 +220,18 @@ ScSmmSetAndCheckEos (
{
UINT32 SmiEn;
- SmiEn = IoRead32 ((UINTN) (AcpiBaseAddr + R_SMI_EN));
+ SmiEn = IoRead32 (((UINTN)AcpiBaseAddr + R_SMI_EN));
//
// Reset the SC to generate subsequent SMIs
//
SmiEn |= B_SMI_EN_EOS;
- IoWrite32 ((UINTN) (AcpiBaseAddr + R_SMI_EN), SmiEn);
+ IoWrite32 (((UINTN)AcpiBaseAddr + R_SMI_EN), SmiEn);
//
// Double check that the assert worked
//
- SmiEn = IoRead32 ((UINTN) (AcpiBaseAddr + R_SMI_EN));
+ SmiEn = IoRead32 (((UINTN)AcpiBaseAddr + R_SMI_EN));
//
// Return TRUE if EOS is set correctly
@@ -268,7 +268,7 @@ ScSmmGetSciEn (
//
// Determine whether an ACPI OS is present (via the SCI_EN bit)
//
- Pm1Cnt = IoRead32 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_CNT));
+ Pm1Cnt = IoRead32 (((UINTN)AcpiBaseAddr + R_ACPI_PM1_CNT));
SciEn = (BOOLEAN) ((Pm1Cnt & B_ACPI_PM1_CNT_SCI_EN) == B_ACPI_PM1_CNT_SCI_EN);
return SciEn;
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c
index 3c11424..37d7fa4 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c
@@ -1,7 +1,7 @@
/** @file
HECI driver.
- Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -170,16 +170,16 @@ LockConfig (
}
MmioAndThenOr32 (
- (UINTN) (PmcBase + R_PMC_PMIR),
+ (UINTN)(UINT32)(PmcBase + R_PMC_PMIR),
(UINT32) (~(B_PMC_PMIR_CF9LOCK | B_PMC_PMIR_CF9GR)),
(UINT32) Data
);
S3BootScriptSaveMemWrite (
EfiBootScriptWidthUint32,
- (UINTN) (PmcBase + R_PMC_PMIR),
+ (UINTN)(UINT32)(PmcBase + R_PMC_PMIR),
1,
- (VOID *) (UINTN) (PmcBase + R_PMC_PMIR)
+ (VOID *) (UINTN)(UINT32)(PmcBase + R_PMC_PMIR)
);
}
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c
index 518636a..a7fc7a4 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c
@@ -1,7 +1,7 @@
/** @file
HECI Smm driver.
- Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -148,9 +148,9 @@ SendPGIEntry (
volatile HECI_HOST_CONTROL_REGISTER *HostControlReg;
volatile HECI_SEC_CONTROL_REGISTER *SecControlReg;
- HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *) (UINTN) (mHeci_HeciBar + H_CSR);
- SecControlReg = (volatile HECI_SEC_CONTROL_REGISTER *) (UINTN) (mHeci_HeciBar + SEC_CSR_HA);
- WriteBuffer = (UINT32 *) (UINTN) (mHeci_HeciBar + H_CB_WW);
+ HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *) ((UINTN)mHeci_HeciBar + H_CSR);
+ SecControlReg = (volatile HECI_SEC_CONTROL_REGISTER *) ((UINTN)mHeci_HeciBar + SEC_CSR_HA);
+ WriteBuffer = (UINT32 *) ((UINTN)mHeci_HeciBar + H_CB_WW);
//
// Prepare message header
@@ -619,9 +619,9 @@ HeciReceiveInterrupt (
volatile HECI_HOST_CONTROL_REGISTER *HostControlReg;
volatile HECI_SEC_CONTROL_REGISTER *SecControlReg;
- HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *) (UINTN) (mHeci_HeciBar + H_CSR);
- SecControlReg = (volatile HECI_SEC_CONTROL_REGISTER *) (UINTN) (mHeci_HeciBar + SEC_CSR_HA);
- ReadBuffer = (UINT32 *) (UINTN) (mHeci_HeciBar + SEC_CB_RW);
+ HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *) ((UINTN)mHeci_HeciBar + H_CSR);
+ SecControlReg = (volatile HECI_SEC_CONTROL_REGISTER *) ((UINTN)mHeci_HeciBar + SEC_CSR_HA);
+ ReadBuffer = (UINT32 *) ((UINTN)mHeci_HeciBar + SEC_CB_RW);
Size = 0;
ReadSize = 0;
@@ -654,7 +654,7 @@ HeciDisableInterrupt (
{
volatile HECI_HOST_CONTROL_REGISTER *HostControlReg;
- HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *) (UINTN) (mHeci_HeciBar + H_CSR);
+ HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *)((UINTN)mHeci_HeciBar + H_CSR);
HostControlReg->r.H_IE = 0;
}
@@ -671,7 +671,7 @@ HeciEnableInterrupt (
{
volatile HECI_HOST_CONTROL_REGISTER *HostControlReg;
- HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *) (UINTN) (mHeci_HeciBar + H_CSR);
+ HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *)((UINTN)mHeci_HeciBar + H_CSR);
HostControlReg->r.H_IE = 1;
}
@@ -688,7 +688,7 @@ HeciClearInterrupt (
{
volatile HECI_HOST_CONTROL_REGISTER *HostControlReg;
- HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *) (UINTN) (mHeci_HeciBar + H_CSR);
+ HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *)((UINTN)mHeci_HeciBar + H_CSR);
HostControlReg->r.H_IS = 1;
}
@@ -707,7 +707,7 @@ HeciInterruptOccur (
{
volatile HECI_HOST_CONTROL_REGISTER *HostControlReg;
- HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *) (UINTN) (mHeci_HeciBar + H_CSR);
+ HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *)((UINTN)mHeci_HeciBar + H_CSR);
return (HostControlReg->r.H_IS == 1);
}
@@ -726,7 +726,7 @@ IsHeciCseResponse (
{
volatile HECI_SEC_CONTROL_REGISTER *SecControlReg;
- SecControlReg = (volatile HECI_SEC_CONTROL_REGISTER *) (UINTN) (mHeci_HeciBar + SEC_CSR_HA);
+ SecControlReg = (volatile HECI_SEC_CONTROL_REGISTER *)((UINTN)mHeci_HeciBar + SEC_CSR_HA);
return (SecControlReg->r.SEC_CBRP_HRA != SecControlReg->r.SEC_CBWP_HRA);
}
--
2.10.1.windows.1
^ permalink raw reply related [flat|nested] only message in thread
only message in thread, other threads:[~2018-08-23 5:32 UTC | newest]
Thread overview: (only message) (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-08-23 5:32 [Patch][edk2-platforms/devel-IntelAtomProcessorE3900 1Fix klocwork issues Guo, Mang
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox