[Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Disable the fourth PCIE port

["Guo, Mang" <mang.guo@intel.com>]

Disable the fourth PCIE port for UP2 board because it caused Yocto S3 failure.
It is a temporary solution of platform.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Guo Mang <mang.guo@intel.com>
CC: David Wei <david.wei@intel.com>
---
 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c   | 5 +++++
 .../Board/UP2/BoardInitPostMem/BoardInitPostMem.inf                  | 3 ++-
 .../Common/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf       | 3 ++-
 .../Common/Library/PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c       | 4 +++-
 Platform/BroxtonPlatformPkg/PlatformPkg.dec                          | 2 ++
 5 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c
index de07429..b7d526a 100644
--- a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c
+++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c
@@ -151,6 +151,11 @@ Up2PostMemInitCallback (
   PcdSet8(HdaEndpointI2sRenderSKPVirtualBusId, 5); //I2S6
   PcdSet8(HdaEndpointI2sRenderHPVirtualBusId, 5);  //I2S6
   PcdSet8(HdaEndpointI2sCaptureVirtualBusId, 5);   //I2S6
+
+  //
+  // Set PcdPciePort3Enable
+  //
+  PcdSetBool(PcdPciePort3Enable, FALSE);
   
   //
   // Add init steps here
diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInitPostMem.inf
index be10d85..4cfa196 100644
--- a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInitPostMem.inf
+++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInitPostMem.inf
@@ -3,7 +3,7 @@
 #
 #  It will detect the board ID.
 #
-#  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -73,6 +73,7 @@
   gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderSKPVirtualBusId
   gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderHPVirtualBusId
   gEfiBxtTokenSpaceGuid.HdaEndpointI2sCaptureVirtualBusId
+  gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable
   
 [Guids]
   gEfiPlatformInfoGuid
diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
index 36e1b1d..9259152 100644
--- a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
+++ b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
@@ -1,7 +1,7 @@
 ## @file
 #  Library functions for Fsp Policy Initialization Library.
 #
-#  Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -90,6 +90,7 @@
   gPlatformModuleTokenSpaceGuid.PcdeMMCHostMaxSpeed
   gPlatformModuleTokenSpaceGuid.PcdHdaVerbTablePtr
   gPlatformModuleTokenSpaceGuid.HdaVerbTableEntryNum
+  gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable
 
 [Ppis]
   gSiPolicyPpiGuid                 ## CONSUMES
diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c
index f9055db..f541ce4 100644
--- a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c
+++ b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c
@@ -1,7 +1,7 @@
 /** @file
   Implementation of Fsp SC Policy Initialization.
 
-  Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -282,6 +282,8 @@ PeiFspScPolicyInit (
       FspsUpd->FspsConfig.PcieRpNonSnoopLatencyOverrideValue[PortIndex]       = SystemConfiguration->PchPcieNonSnoopLatencyOverrideValue[PortIndex];
       FspsUpd->FspsConfig.PtmEnable[PortIndex]                                = TRUE;
     }
+  FspsUpd->FspsConfig.PcieRootPortEn[3]                                     = PcdGetBool(PcdPciePort3Enable);
+
 #if (ENBDT_PF_ENABLE == 1)
     FspsUpd->FspsConfig.PcieRpClkReqSupported[0] = TRUE;
     FspsUpd->FspsConfig.PcieRpClkReqNumber   [0] = 2;
diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.dec b/Platform/BroxtonPlatformPkg/PlatformPkg.dec
index e42b6e7..e7b26a9 100644
--- a/Platform/BroxtonPlatformPkg/PlatformPkg.dec
+++ b/Platform/BroxtonPlatformPkg/PlatformPkg.dec
@@ -212,6 +212,8 @@
   gPlatformModuleTokenSpaceGuid.HdaVerbTableEntryNum|0|UINT8|0x8000001E
 
   gPlatformModuleTokenSpaceGuid.PcdOemLogoFileGuid|{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x8000001F
+  ## This PCD is used to enable or disable PCIE port 3
+  gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable|TRUE|BOOLEAN|0x80000020
 
   
   ## MemoryCheck value for checking memory before boot OS.
-- 
2.10.1.windows.1