From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.136; helo=mga12.intel.com; envelope-from=mang.guo@intel.com; receiver=edk2-devel@lists.01.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 65D7D21127CD7 for ; Wed, 12 Sep 2018 00:01:08 -0700 (PDT) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Sep 2018 00:01:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,363,1531810800"; d="dat'59?scan'59,208,59";a="261877760" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga005.fm.intel.com with ESMTP; 12 Sep 2018 00:01:07 -0700 Received: from fmsmsx112.amr.corp.intel.com (10.18.116.6) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 12 Sep 2018 00:01:07 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX112.amr.corp.intel.com (10.18.116.6) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 12 Sep 2018 00:01:06 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.240]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.143]) with mapi id 14.03.0319.002; Wed, 12 Sep 2018 15:00:23 +0800 From: "Guo, Mang" To: "edk2-devel@lists.01.org" CC: "Wei, David" Thread-Topic: [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Disable the fourth PCIE port Thread-Index: AdRKZkZJ7jLk9lwITciFR2RBoIkOGw== Date: Wed, 12 Sep 2018 07:00:23 +0000 Message-ID: <22D2C85ED001C54AA20BFE3B0E4751D1526D8144@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: <22D2C85ED001C54AA20BFE3B0E4751D1526D8144@SHSMSX103.ccr.corp.intel.com> x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Disable the fourth PCIE port X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 12 Sep 2018 07:01:08 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Disable the fourth PCIE port for UP2 board because it caused Yocto S3 failu= re. It is a temporary solution of platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Guo Mang CC: David Wei --- Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c | 5 += ++++ .../Board/UP2/BoardInitPostMem/BoardInitPostMem.inf | 3 += +- .../Common/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf | 3 += +- .../Common/Library/PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c | 4 += ++- Platform/BroxtonPlatformPkg/PlatformPkg.dec | 2 += + 5 files changed, 14 insertions(+), 3 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardIn= it.c b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c index de07429..b7d526a 100644 --- a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c @@ -151,6 +151,11 @@ Up2PostMemInitCallback ( PcdSet8(HdaEndpointI2sRenderSKPVirtualBusId, 5); //I2S6 PcdSet8(HdaEndpointI2sRenderHPVirtualBusId, 5); //I2S6 PcdSet8(HdaEndpointI2sCaptureVirtualBusId, 5); //I2S6 + + // + // Set PcdPciePort3Enable + // + PcdSetBool(PcdPciePort3Enable, FALSE); =20 // // Add init steps here diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardIn= itPostMem.inf b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/Boar= dInitPostMem.inf index be10d85..4cfa196 100644 --- a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInitPostM= em.inf +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInitPostM= em.inf @@ -3,7 +3,7 @@ # # It will detect the board ID. # -# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -73,6 +73,7 @@ gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderSKPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderHPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sCaptureVirtualBusId + gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable =20 [Guids] gEfiPlatformInfoGuid diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib= /PeiFspPolicyInitLib.inf b/Platform/BroxtonPlatformPkg/Common/Library/PeiFs= pPolicyInitLib/PeiFspPolicyInitLib.inf index 36e1b1d..9259152 100644 --- a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFsp= PolicyInitLib.inf +++ b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFsp= PolicyInitLib.inf @@ -1,7 +1,7 @@ ## @file # Library functions for Fsp Policy Initialization Library. # -# Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -90,6 +90,7 @@ gPlatformModuleTokenSpaceGuid.PcdeMMCHostMaxSpeed gPlatformModuleTokenSpaceGuid.PcdHdaVerbTablePtr gPlatformModuleTokenSpaceGuid.HdaVerbTableEntryNum + gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable =20 [Ppis] gSiPolicyPpiGuid ## CONSUMES diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib= /PeiFspScPolicyInitLib.c b/Platform/BroxtonPlatformPkg/Common/Library/PeiFs= pPolicyInitLib/PeiFspScPolicyInitLib.c index f9055db..f541ce4 100644 --- a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFsp= ScPolicyInitLib.c +++ b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFsp= ScPolicyInitLib.c @@ -1,7 +1,7 @@ /** @file Implementation of Fsp SC Policy Initialization. =20 - Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -282,6 +282,8 @@ PeiFspScPolicyInit ( FspsUpd->FspsConfig.PcieRpNonSnoopLatencyOverrideValue[PortIndex] = =3D SystemConfiguration->PchPcieNonSnoopLatencyOverrideValue[PortIndex]= ; FspsUpd->FspsConfig.PtmEnable[PortIndex] = =3D TRUE; } + FspsUpd->FspsConfig.PcieRootPortEn[3] = =3D PcdGetBool(PcdPciePort3Enable); + #if (ENBDT_PF_ENABLE =3D=3D 1) FspsUpd->FspsConfig.PcieRpClkReqSupported[0] =3D TRUE; FspsUpd->FspsConfig.PcieRpClkReqNumber [0] =3D 2; diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.dec b/Platform/Broxton= PlatformPkg/PlatformPkg.dec index e42b6e7..e7b26a9 100644 --- a/Platform/BroxtonPlatformPkg/PlatformPkg.dec +++ b/Platform/BroxtonPlatformPkg/PlatformPkg.dec @@ -212,6 +212,8 @@ gPlatformModuleTokenSpaceGuid.HdaVerbTableEntryNum|0|UINT8|0x8000001E =20 gPlatformModuleTokenSpaceGuid.PcdOemLogoFileGuid|{ 0x00, 0x00, 0x00, 0x0= 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }= |VOID*|0x8000001F + ## This PCD is used to enable or disable PCIE port 3 + gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable|TRUE|BOOLEAN|0x80000020 =20 =20 ## MemoryCheck value for checking memory before boot OS. --=20 2.10.1.windows.1