From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=mang.guo@intel.com; receiver=edk2-devel@lists.01.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 796962194D387 for ; Wed, 26 Sep 2018 01:39:12 -0700 (PDT) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2018 01:39:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,305,1534834800"; d="dat'59?scan'59,208,59";a="236026427" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga004.jf.intel.com with ESMTP; 26 Sep 2018 01:35:44 -0700 Received: from fmsmsx119.amr.corp.intel.com (10.18.124.207) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 26 Sep 2018 01:35:36 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by FMSMSX119.amr.corp.intel.com (10.18.124.207) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 26 Sep 2018 01:35:36 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.245]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.220]) with mapi id 14.03.0319.002; Wed, 26 Sep 2018 16:35:34 +0800 From: "Guo, Mang" To: "edk2-devel@lists.01.org" CC: "Wei, David" Thread-Topic: [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Set PcdPciePort3Enable Thread-Index: AdRVc+QWW+PiDalnTEmI9l5sRwPKrw== Date: Wed, 26 Sep 2018 08:35:34 +0000 Message-ID: <22D2C85ED001C54AA20BFE3B0E4751D1526FBD0C@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: <22D2C85ED001C54AA20BFE3B0E4751D1526FBD0C@SHSMSX103.ccr.corp.intel.com> x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Set PcdPciePort3Enable X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Sep 2018 08:39:12 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Use system setup variable to set PcdPciePort3Enable. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Guo Mang --- .../Board/AuroraGlacier/BoardInitPostMem/BoardInit.c | 5 +++= ++ .../Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf | 1 + .../Board/BensonGlacier/BoardInitPostMem/BoardInit.c | 5 +++= ++ .../Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf | 1 + .../BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c | 7 +++= +++- .../Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf | 1 + .../Board/MinnowBoard3/BoardInitPostMem/BoardInit.c | 6 +++= +++ .../Board/MinnowBoard3/BoardInitPostMem/BoardInitPostMem.inf | 1 + .../Board/MinnowBoard3Module/BoardInitPostMem/BoardInit.c | 5 +++= ++ .../Board/MinnowBoard3Module/BoardInitPostMem/BoardInitPostMem.inf | 1 + 10 files changed, 32 insertions(+), 1 deletion(-) diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostM= em/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitP= ostMem/BoardInit.c index ce98086..c61ac86 100644 --- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Boar= dInit.c +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Boar= dInit.c @@ -146,6 +146,11 @@ AuroraGlacierPostMemInitCallback ( PcdSet8(HdaEndpointI2sCaptureVirtualBusId, 1); // I2S2 =20 // + // Set PcdPciePort3Enable + // + PcdSetBool(PcdPciePort3Enable, SystemConfiguration.PcieRootPortEn[3]); + + // // Add init steps here // // diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostM= em/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/B= oardInitPostMem/BoardInitPostMem.inf index c619332..32aa1da 100644 --- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Boar= dInitPostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Boar= dInitPostMem.inf @@ -74,6 +74,7 @@ gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderSKPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderHPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sCaptureVirtualBusId + gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable =20 [Guids] gEfiPlatformInfoGuid diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostM= em/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitP= ostMem/BoardInit.c index 856d773..c1c4dcd 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInit.c +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInit.c @@ -146,6 +146,11 @@ BensonGlacierPostMemInitCallback ( PcdSet8(HdaEndpointI2sCaptureVirtualBusId, 1); // I2S2 =20 // + // Set PcdPciePort3Enable + // + PcdSetBool(PcdPciePort3Enable, SystemConfiguration.PcieRootPortEn[3]); + + // // Add init steps here // // diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostM= em/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/B= oardInitPostMem/BoardInitPostMem.inf index 01d7f27..7dbfed9 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInitPostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInitPostMem.inf @@ -74,6 +74,7 @@ gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderSKPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderHPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sCaptureVirtualBusId + gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable =20 [Guids] gEfiPlatformInfoGuid diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/Bo= ardInit.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/Boa= rdInit.c index 729b15f..5f509a3 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit= .c +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit= .c @@ -151,7 +151,12 @@ LeafHillPostMemInitCallback ( PcdSet8(HdaEndpointI2sRenderSKPVirtualBusId, 5); //I2S6 PcdSet8(HdaEndpointI2sRenderHPVirtualBusId, 5); //I2S6 PcdSet8(HdaEndpointI2sCaptureVirtualBusId, 5); //I2S6 - =20 + + // + // Set PcdPciePort3Enable + // + PcdSetBool(PcdPciePort3Enable, SystemConfiguration.PcieRootPortEn[3]); + // // Add init steps here // diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/Bo= ardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPo= stMem/BoardInitPostMem.inf index 46a6f4b..904b491 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit= PostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit= PostMem.inf @@ -74,6 +74,7 @@ gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderSKPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderHPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sCaptureVirtualBusId + gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable =20 [Guids] gEfiPlatformInfoGuid diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMe= m/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPos= tMem/BoardInit.c index 3323ee8..d2ed286 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= Init.c +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= Init.c @@ -157,6 +157,12 @@ MinnowBoard3PostMemInitCallback ( PcdSet8(HdaEndpointI2sRenderHPVirtualBusId, 0); // I2S1 PcdSet8(HdaEndpointI2sCaptureVirtualBusId, 0); // I2S1 =20 + + // + // Set PcdPciePort3Enable + // + PcdSetBool(PcdPciePort3Enable, SystemConfiguration.PcieRootPortEn[3]); + // // Add init steps here // diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMe= m/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/Boa= rdInitPostMem/BoardInitPostMem.inf index 15d7f46..275a7f4 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= InitPostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= InitPostMem.inf @@ -70,6 +70,7 @@ gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderSKPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderHPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sCaptureVirtualBusId + gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable =20 [Guids] gEfiPlatformInfoGuid diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInit= PostMem/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/= BoardInitPostMem/BoardInit.c index 445897a..6d5817a 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem= /BoardInit.c +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem= /BoardInit.c @@ -127,6 +127,11 @@ MinnowBoard3ModulePostMemInitCallback ( PcdSet8 (PcdeMMCHostMaxSpeed, (UINT8) (SystemConfiguration.ScceMMCHostMa= xSpeed)); =20 // + // Set PcdPciePort3Enable + // + PcdSetBool(PcdPciePort3Enable, SystemConfiguration.PcieRootPortEn[3]); + + // // Add init steps here // // diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInit= PostMem/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoar= d3Module/BoardInitPostMem/BoardInitPostMem.inf index 67708d2..d5b0604 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem= /BoardInitPostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem= /BoardInitPostMem.inf @@ -66,6 +66,7 @@ gPlatformModuleTokenSpaceGuid.PcdOemLogoFileGuid gPlatformModuleTokenSpaceGuid.PcdTianoCoreLogoFileGuid gPlatformModuleTokenSpaceGuid.PcdeMMCHostMaxSpeed + gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable =20 [Guids] gEfiPlatformInfoGuid --=20 2.10.1.windows.1