From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qk1-f180.google.com (mail-qk1-f180.google.com [209.85.222.180]) by mx.groups.io with SMTP id smtpd.web09.3365.1661805424342333299 for ; Mon, 29 Aug 2022 13:37:04 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20210112 header.b=NBgZt5Kj; spf=pass (domain: gmail.com, ip: 209.85.222.180, mailfrom: benjamin.doron00@gmail.com) Received: by mail-qk1-f180.google.com with SMTP id f14so7009879qkm.0 for ; Mon, 29 Aug 2022 13:37:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=NnsU4PEzHXrCazai+xdcWBYLV3tC8QuP8HudtOXlQOg=; b=NBgZt5KjXukeXJ4orIwpMCJ5fOrb1Tjcs4RcrsZHiZ2EC25KOwCBVX++YErbNgWdgS zFVe9bPKDZuWo9qxZ/t5ZmWUxOyd5dVSbyAqN5C9CR497jIGw5XQTEQ9K8gDOwpokRZA d8b/2Ti/UvOajG1I3Vg+4SkD0yjdnzlaujN0JQPSQlHj6Egw3r/Elxa7B3fd3XK1UFzk NiXAzioPGm3JUuswbX5XlwW6SXq0tyNv3DEHEbI3csiidHoTluWKvYDepFuuZYpdhukD uUe0nLI+O73Gpawkge+1hZSnqfuyWe9gH+mYShFqj698z12M54JZl+DTaogOWT/AeLvj /4cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=NnsU4PEzHXrCazai+xdcWBYLV3tC8QuP8HudtOXlQOg=; b=g3Nslif3Flft2TBxJ2AlwWwl577w8IuVnb+prIAkZwWHbRWyt+24CAmiMPPA40yQSZ q1/QRp8Wt8YHTq13FhheZGKy6g2Dcc7iTNhr5vnDjNt/esX+MBv4FB091o8B+CFfQoOD JRp1ZZHFDg6F5AoFZdiiB3NQYK+q0gIT9kCEFt7RMeOkXq1YusZyzSZ1ztmppceYi0RS nNKar6EtL+X9rDlAe6yebCwBl5OiygHXG/nbYGb4YgNxpub4vDg33Rvxl0BUkgLQQje0 KW8k3ZiQ788Fth5tG0o6Hjwt9VWYE+t24GHA5EABB+MFH80CsTQ0Qc1emXPcH1BogJIq OdGw== X-Gm-Message-State: ACgBeo1YGXFxZStKc1/kqHrpOjaw3dSlkzi2Xatx2HqWbLPAfat2ERnl x19KfSPN22lc7A1bO/uiZzl8jlpf/dPVcA== X-Google-Smtp-Source: AA6agR6q9I89pA3Dq5OCBqY1uJUu+N+cO9ChT/HtQbEoeyYfVLKQcXU4lMWfVlc70kOCxsGVtcUXgw== X-Received: by 2002:a05:620a:408a:b0:6bb:584a:fb49 with SMTP id f10-20020a05620a408a00b006bb584afb49mr9905236qko.468.1661805423114; Mon, 29 Aug 2022 13:37:03 -0700 (PDT) Return-Path: Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:da1:4180:8030:1a92]) by smtp.gmail.com with ESMTPSA id bp6-20020a05620a458600b006bbda80595asm6846218qkb.5.2022.08.29.13.37.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 13:37:02 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Nate DeSimone , Ankit Sinha , Sai Chaganty , Isaac Oram , Liming Gao Subject: [edk2-devel][edk2-platforms][PATCH v1 3/5] S3FeaturePkg: Implement working S3 resume Date: Mon, 29 Aug 2022 16:36:18 -0400 Message-Id: <23fd6d63ba743cfbfa994dda115437719dbc2b4f.1661799519.git.benjamin.doron00@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Follow-up commits to MinPlatform (PeiFspWrapperHobProcessLib for memory) and FSP-related board libraries (policy overrides) required for successful S3 resume. Factored allocation logic into new module to avoid MinPlatform dependency on S3Feature package. TODO: Can optimise required size. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Sai Chaganty Cc: Isaac Oram Cc: Liming Gao Signed-off-by: Benjamin Doron --- .../S3FeaturePkg/Include/PostMemory.fdf | 15 ++ .../S3FeaturePkg/Include/PreMemory.fdf | 8 +- .../S3FeaturePkg/Include/S3Feature.dsc | 42 ++++- .../S3FeaturePkg/S3Dxe/S3Dxe.c | 156 ++++++++++++++++++ .../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++++++ .../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++++++++- .../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +- .../Include/AcpiS3MemoryNvData.h | 22 +++ 8 files changed, 375 insertions(+), 8 deletions(-) create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe= .c create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe= .inf create mode 100644 Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvDat= a.h diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory= .fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf index 9e17f853c630..5d3d96f4f317 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf @@ -2,7 +2,22 @@ # FDF file for post-memory S3 advanced feature modules.=0D #=0D # Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2022, Baruch Binyamin Doron.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D ##=0D +=0D +## Dependencies=0D + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf=0D + INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf=0D +=0D +## Save-state module stack=0D + INF S3FeaturePkg/S3Dxe/S3Dxe.inf=0D + INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf=0D + # FSP may perform CPU finalisation, requires CpuInitDxe from closed code= =0D + # - Presently, PiSmmCpuDxeSmm shall perform finalisation with this data= =0D + INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf=0D +=0D +## Restore-state module stack=0D + INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutor= Dxe.inf=0D diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.= fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf index fdd16a4e0356..e130fa5f098d 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf @@ -2,9 +2,15 @@ # FDF file for pre-memory S3 advanced feature modules.=0D #=0D # Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2022, Baruch Binyamin Doron.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D ##=0D =0D -INF S3FeaturePkg/S3Pei/S3Pei.inf=0D +## Dependencies=0D + INF S3FeaturePkg/S3Pei/S3Pei.inf=0D + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf=0D +=0D +## Restore-state module stack=0D + INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf=0D diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.= dsc b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc index cc34e785076a..bf45b56258ff 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc @@ -7,6 +7,7 @@ # for the build infrastructure.=0D #=0D # Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2022, Baruch Binyamin Doron.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -25,6 +26,10 @@ !error "DXE_ARCH must be specified to build this feature!"=0D !endif=0D =0D +[PcdsFixedAtBuild]=0D + # Attempts to improve performance at the cost of more DRAM usage=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE=0D +=0D ##########################################################################= ######=0D #=0D # Library Class section - list of all Library Classes needed by this featu= re.=0D @@ -32,7 +37,15 @@ ##########################################################################= ######=0D =0D [LibraryClasses.common.PEIM]=0D - SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/P= eiSmmAccessLib.inf=0D + #SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibS= mramc/PeiSmmAccessLib.inf=0D + SmmControlLib|IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLi= b/PeiSmmControlLib.inf=0D + #IntelCompatShimLib|$(PLATFORM_SI_PACKAGE)/Library/BaseIntelCompatShimLi= bKbl/BaseIntelCompatShimLibKbl.inf=0D +=0D +[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_SMM_DRIVER]=0D + #######################################=0D + # Edk2 Packages=0D + #######################################=0D + S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScrip= tLib.inf=0D =0D ##########################################################################= ######=0D #=0D @@ -65,3 +78,30 @@ =0D # Add components here that should be included in the package build.=0D S3FeaturePkg/S3Pei/S3Pei.inf=0D + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf=0D + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf=0D +=0D +#=0D +# Feature DXE Components=0D +#=0D +=0D +# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzi= lla.tianocore.org/show_bug.cgi?id=3D2308=0D +# is completed.=0D +[Components.X64]=0D + #####################################=0D + # S3 Feature Package=0D + #####################################=0D +=0D + # Add library instances here that are not included in package components= and should be tested=0D + # in the package build.=0D +=0D + # Add components here that should be included in the package build.=0D + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf=0D + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf=0D + S3FeaturePkg/S3Dxe/S3Dxe.inf=0D + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf=0D + UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf=0D + # NOTE: RSC will be after end-of-BS, use DebugLibSerialPort=0D + # - No gBS in SerialPortInitialize()=0D + # - No global assigns after ReadyToLock possible, due to LockBox copy=0D + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf=0D diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c b/Fe= atures/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c new file mode 100644 index 000000000000..b3fb63e2bc33 --- /dev/null +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c @@ -0,0 +1,156 @@ +/** @file=0D + Source code file for S3 DXE module=0D +=0D +Copyright (c) 2022, Baruch Binyamin Doron.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Get the mem size in memory type infromation table.=0D +=0D + @return the mem size in memory type infromation table.=0D +**/=0D +UINT64=0D +EFIAPI=0D +GetMemorySizeInMemoryTypeInformation (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_MEMORY_TYPE_INFORMATION *MemoryData;=0D + UINT8 Index;=0D + UINTN TempPageNum;=0D +=0D + Status =3D EfiGetSystemConfigurationTable (&gEfiMemoryTypeInformationGui= d, (VOID **) &MemoryData);=0D +=0D + if (EFI_ERROR (Status) || MemoryData =3D=3D NULL) {=0D + return 0;=0D + }=0D +=0D + TempPageNum =3D 0;=0D + for (Index =3D 0; MemoryData[Index].Type !=3D EfiMaxMemoryType; Index++)= {=0D + //=0D + // Accumulate default memory size requirements=0D + //=0D + TempPageNum +=3D MemoryData[Index].NumberOfPages;=0D + }=0D +=0D + return TempPageNum * EFI_PAGE_SIZE;=0D +}=0D +=0D +/**=0D + Get the mem size need to be consumed and reserved for PEI phase resume.= =0D +=0D + @return the mem size to be reserved for PEI phase resume.=0D +**/=0D +UINT64=0D +EFIAPI=0D +GetPeiMemSize (=0D + VOID=0D + )=0D +{=0D + #define PEI_ADDITIONAL_MEMORY_SIZE (16 * EFI_PAGE_SIZE)=0D +=0D + UINT64 Size;=0D +=0D + Size =3D GetMemorySizeInMemoryTypeInformation ();=0D +=0D + return PcdGet32 (PcdPeiMinMemSize) + Size + PEI_ADDITIONAL_MEMORY_SIZE;= =0D +}=0D +=0D +/**=0D + Allocate EfiACPIMemoryNVS below 4G memory address.=0D +=0D + This function allocates EfiACPIMemoryNVS below 4G memory address.=0D +=0D + @param Size Size of memory to allocate.=0D +=0D + @return Allocated address for output.=0D +=0D +**/=0D +VOID *=0D +EFIAPI=0D +AllocateAcpiNvsMemoryBelow4G (=0D + IN UINTN Size=0D + )=0D +{=0D + UINTN Pages;=0D + EFI_PHYSICAL_ADDRESS Address;=0D + EFI_STATUS Status;=0D + VOID *Buffer;=0D +=0D + Pages =3D EFI_SIZE_TO_PAGES (Size);=0D + Address =3D 0xffffffff;=0D +=0D + Status =3D gBS->AllocatePages (=0D + AllocateMaxAddress,=0D + EfiACPIMemoryNVS,=0D + Pages,=0D + &Address=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Buffer =3D (VOID *)(UINTN)Address;=0D + ZeroMem (Buffer, Size);=0D +=0D + return Buffer;=0D +}=0D +=0D +/**=0D + Allocates memory to use on S3 resume.=0D +=0D + @param[in] ImageHandle Not used.=0D + @param[in] SystemTable General purpose services available to e= very DXE driver.=0D +=0D + @retval EFI_SUCCESS The function completes successfully=0D + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databa= se=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +S3DxeEntryPoint (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + )=0D +{=0D + UINT64 S3PeiMemSize;=0D + UINT64 S3PeiMemBase;=0D + ACPI_S3_MEMORY S3MemoryInfo;=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__));=0D +=0D + S3PeiMemSize =3D GetPeiMemSize ();=0D + S3PeiMemBase =3D (UINTN) AllocateAcpiNvsMemoryBelow4G (S3PeiMemSize);=0D + ASSERT (S3PeiMemBase !=3D 0);=0D +=0D + S3MemoryInfo.S3PeiMemBase =3D S3PeiMemBase;=0D + S3MemoryInfo.S3PeiMemSize =3D S3PeiMemSize;=0D +=0D + DEBUG ((DEBUG_INFO, "S3PeiMemBase: 0x%x\n", S3PeiMemBase));=0D + DEBUG ((DEBUG_INFO, "S3PeiMemSize: 0x%x\n", S3PeiMemSize));=0D +=0D + // TODO: LockBox is potentially superior, though requires static locatio= n=0D + Status =3D gRT->SetVariable (=0D + ACPI_S3_MEMORY_NV_NAME,=0D + &gEfiAcpiVariableGuid,=0D + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACC= ESS,=0D + sizeof (S3MemoryInfo),=0D + &S3MemoryInfo=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__));=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf b/= Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf new file mode 100644 index 000000000000..28589c2c869b --- /dev/null +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf @@ -0,0 +1,49 @@ +### @file=0D +# Component information file for the S3 DXE module.=0D +#=0D +# Copyright (c) 2022, Baruch Binyamin Doron.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +###=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D S3Dxe=0D + FILE_GUID =3D 30926F92-CC83-4381-9F70-AC96EDB5BEE0=0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D DXE_DRIVER=0D + ENTRY_POINT =3D S3DxeEntryPoint=0D +=0D +[LibraryClasses]=0D + UefiDriverEntryPoint=0D + UefiBootServicesTableLib=0D + UefiRuntimeServicesTableLib=0D + BaseMemoryLib=0D + DebugLib=0D + PcdLib=0D + UefiLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec=0D + S3FeaturePkg/S3FeaturePkg.dec=0D +=0D +[Sources]=0D + S3Dxe.c=0D +=0D +[Pcd]=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize=0D +=0D +[FeaturePcd]=0D + gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable=0D +=0D +[Guids]=0D + gEfiMemoryTypeInformationGuid ## CONSUMES=0D + gEfiAcpiVariableGuid ## CONSUMES=0D +=0D +[Depex]=0D + gEfiVariableArchProtocolGuid AND=0D + gEfiVariableWriteArchProtocolGuid=0D diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c b/Fe= atures/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c index b0aaa04962c8..6acb894b6fc9 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c @@ -2,12 +2,87 @@ Source code file for S3 PEI module=0D =0D Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2022, Baruch Binyamin Doron.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D =0D +#include =0D +#include =0D +#include =0D #include =0D #include =0D +#include =0D +=0D +// TODO: Finalise implementation factoring=0D +#define R_SA_PAM0 (0x80)=0D +#define R_SA_PAM5 (0x85)=0D +#define R_SA_PAM6 (0x86)=0D +=0D +/**=0D + This function is called after FspSiliconInitDone installed PPI.=0D + For FSP API mode, this is when FSP-M HOBs are installed into EDK2.=0D +=0D + @param[in] PeiServices Pointer to PEI Services Table.=0D + @param[in] NotifyDesc Pointer to the descriptor for the Notification= event that=0D + caused this function to execute.=0D + @param[in] Ppi Pointer to the PPI data associated with this f= unction.=0D +=0D + @retval EFI_STATUS Always return EFI_SUCCESS=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +FspSiliconInitDoneNotify (=0D + IN EFI_PEI_SERVICES **PeiServices,=0D + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,=0D + IN VOID *Ppi=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_BOOT_MODE BootMode;=0D + UINT64 MchBaseAddress;=0D +=0D + Status =3D PeiServicesGetBootMode (&BootMode);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + // Enable PAM regions for AP wakeup vector (resume)=0D + // - CPU is finalised by PiSmmCpuDxeSmm, not FSP. So, it's safe here?=0D + // TODO/TEST: coreboot does this unconditionally, vendor FWs may not (te= st resume). Should we?=0D + // - It is certainly interesting that only PAM0, PAM5 and PAM6 are defin= ed for KabylakeSiliconPkg.=0D + // - Also note that 0xA0000-0xFFFFF is marked "reserved" in FSP HOB - th= is does not mean=0D + // that the memory is unusable, perhaps this is precisely because it w= ill contain=0D + // the AP wakeup vector.=0D + if (BootMode =3D=3D BOOT_ON_S3_RESUME) {=0D + MchBaseAddress =3D PCI_LIB_ADDRESS (0, 0, 0, 0);=0D + PciWrite8 (MchBaseAddress + R_SA_PAM0, 0x30);=0D + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 1), 0x33);=0D + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 2), 0x33);=0D + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 3), 0x33);=0D + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 4), 0x33);=0D + PciWrite8 (MchBaseAddress + R_SA_PAM5, 0x33);=0D + PciWrite8 (MchBaseAddress + R_SA_PAM6, 0x33);=0D + }=0D +=0D + //=0D + // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case=0D + //=0D + Status =3D PeiInstallSmmAccessPpi ();=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Install EFI_PEI_MM_CONTROL_PPI for S3 resume case=0D + //=0D + Status =3D PeiInstallSmmControlPpi ();=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return Status;=0D +}=0D +=0D +EFI_PEI_NOTIFY_DESCRIPTOR mFspSiliconInitDoneNotifyDesc =3D {=0D + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST),=0D + &gFspSiliconInitDonePpiGuid,=0D + FspSiliconInitDoneNotify=0D +};=0D =0D /**=0D S3 PEI module entry point=0D @@ -25,12 +100,10 @@ S3PeiEntryPoint ( IN CONST EFI_PEI_SERVICES **PeiServices=0D )=0D {=0D - EFI_STATUS Status;=0D + EFI_STATUS Status;=0D =0D - //=0D - // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case=0D - //=0D - Status =3D PeiInstallSmmAccessPpi ();=0D + Status =3D PeiServicesNotifyPpi (&mFspSiliconInitDoneNotifyDesc);=0D + ASSERT_EFI_ERROR (Status);=0D =0D return Status;=0D }=0D diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf b/= Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf index e485eac9521f..173919bb881e 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf @@ -18,10 +18,13 @@ [LibraryClasses]=0D PeimEntryPoint=0D PeiServicesLib=0D + DebugLib=0D SmmAccessLib=0D + SmmControlLib=0D =0D [Packages]=0D MdePkg/MdePkg.dec=0D + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec=0D IntelSiliconPkg/IntelSiliconPkg.dec=0D S3FeaturePkg/S3FeaturePkg.dec=0D =0D @@ -31,5 +34,8 @@ [FeaturePcd]=0D gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable=0D =0D +[Ppis]=0D + gFspSiliconInitDonePpiGuid=0D +=0D [Depex]=0D - gEfiPeiMemoryDiscoveredPpiGuid=0D + TRUE=0D diff --git a/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h b/P= latform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h new file mode 100644 index 000000000000..0d75af8e9a03 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h @@ -0,0 +1,22 @@ +/** @file + Header file for NV data structure definition. + +Copyright (c) 2021, Baruch Binyamin Doron +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ACPI_S3_MEMORY_NV_DATA_H__ +#define __ACPI_S3_MEMORY_NV_DATA_H__ + +// +// NV data structure +// +typedef struct { + UINT64 S3PeiMemBase; + UINT64 S3PeiMemSize; +} ACPI_S3_MEMORY; + +#define ACPI_S3_MEMORY_NV_NAME L"S3MemoryInfo" + +#endif --=20 2.37.2