From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3984C1A1E10 for ; Mon, 17 Oct 2016 10:50:42 -0700 (PDT) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga101.fm.intel.com with ESMTP; 17 Oct 2016 10:50:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,357,1473145200"; d="scan'208";a="20455664" Received: from mxma-desk2.amr.corp.intel.com ([134.134.155.154]) by fmsmga006.fm.intel.com with ESMTP; 17 Oct 2016 10:50:41 -0700 From: Maurice Ma To: edk2-devel@lists.01.org Cc: Maurice Ma , Prince Agyeman Date: Mon, 17 Oct 2016 10:50:30 -0700 Message-Id: <242be7336b58c61b624a03c9f5b5ccebdd5bb5ff.1476726574.git.maurice.ma@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 Subject: [PATCH] CorebootPayloadPkg/PciHostBridgeLib: Fix the wrong PCI resource limit X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 17 Oct 2016 17:50:42 -0000 The current PCI resource limit calculation in CorebootPayloadPkg PciHostBridgeLib is wrong. Adjusted it to match the PciHostBridge driver's expectation. Cc: Prince Agyeman Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma --- CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c index 0f1c8cb1a210..6d94ff72c956 100644 --- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c +++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c @@ -91,7 +91,7 @@ AdjustRootBridgeResource ( // Align IO resource at 4K boundary // Mask = 0xFFFULL; - Io->Limit = (Io->Limit + Mask) & ~Mask; + Io->Limit = ((Io->Limit + Mask) & ~Mask) - 1; if (Io->Base != MAX_UINT64) { Io->Base &= ~Mask; } @@ -100,7 +100,7 @@ AdjustRootBridgeResource ( // Align MEM resource at 1MB boundary // Mask = 0xFFFFFULL; - Mem->Limit = (Mem->Limit + Mask) & ~Mask; + Mem->Limit = ((Mem->Limit + Mask) & ~Mask) - 1; if (Mem->Base != MAX_UINT64) { Mem->Base &= ~Mask; } -- 1.9.5.msysgit.0