[PATCH v1 0/5] Adds AmdSmmCpuFeaturesLib

[PATCH v1 0/5] Adds AmdSmmCpuFeaturesLib

[Abdul Lateef Attar]

Implements SmmCpuFeaturesLib library class for AMD processor family.
Adds AMD processor families processor save state registers.
Implements required functions.
Handles S3 save state from SMM.

PR: https://github.com/tianocore/edk2/pull/3726

Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Garrett Kirkendall <garrett.kirkendall@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Abdul Lateef Attar (5):
  UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code
  MdePkg: Adds AMD SMRAM save state map
  UefiCpuPkg: Initial implementation of AMD's SmmCpuFeaturesLib
  UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family
  UefiCpuPkg/AmdSmmCpuFeaturesLib: Handles S3 save state

 UefiCpuPkg/UefiCpuPkg.dsc                     |   9 +
 .../AmdSmmCpuFeaturesLib.inf                  |  40 ++
 .../Include/Register/Amd/SmramSaveStateMap.h  | 194 +++++++
 .../SmmCpuFeaturesLib/Amd/SmramSaveState.h    | 128 +++++
 .../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c | 476 ++++++++++++++++++
 .../SmmCpuFeaturesLib/Amd/SmramSaveState.c    | 409 +++++++++++++++
 .../IntelSmmCpuFeaturesLib.c                  | 140 ++++++
 .../SmmCpuFeaturesLibCommon.c                 | 140 ------
 MdePkg/MdePkg.ci.yaml                         |   3 +-
 9 files changed, 1398 insertions(+), 141 deletions(-)
 create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
 create mode 100644 MdePkg/Include/Register/Amd/SmramSaveStateMap.h
 create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
 create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
 create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.c

-- 
2.25.1

[PATCH v1 1/5] UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code

[Abdul Lateef Attar]

From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182

moves Intel-specific code to the arch-dependent file.
Other processor families might have different
implementation of these functions.
Hence, moving out of the common file.

Cc: Abner Chang <abner.chang@amd.com>
Cc: Garrett Kirkendall <garrett.kirkendall@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
---
 .../IntelSmmCpuFeaturesLib.c                  | 140 ++++++++++++++++++
 .../SmmCpuFeaturesLibCommon.c                 | 140 ------------------
 2 files changed, 140 insertions(+), 140 deletions(-)

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c
index d5eaaa7a991e..994267f393b3 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c
@@ -400,3 +400,143 @@ SmmCpuFeaturesSetSmmRegister (
     AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);
   }
 }
+
+/**
+  This function updates the SMRAM save state on the currently executing CPU
+  to resume execution at a specific address after an RSM instruction.  This
+  function must evaluate the SMRAM save state to determine the execution mode
+  the RSM instruction resumes and update the resume execution address with
+  either NewInstructionPointer32 or NewInstructionPoint.  The auto HALT restart
+  flag in the SMRAM save state must always be cleared.  This function returns
+  the value of the instruction pointer from the SMRAM save state that was
+  replaced.  If this function returns 0, then the SMRAM save state was not
+  modified.
+
+  This function is called during the very first SMI on each CPU after
+  SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
+  to signal that the SMBASE of each CPU has been updated before the default
+  SMBASE address is used for the first SMI to the next CPU.
+
+  @param[in] CpuIndex                 The index of the CPU to hook.  The value
+                                      must be between 0 and the NumberOfCpus
+                                      field in the System Management System Table
+                                      (SMST).
+  @param[in] CpuState                 Pointer to SMRAM Save State Map for the
+                                      currently executing CPU.
+  @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
+                                      32-bit execution mode from 64-bit SMM.
+  @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
+                                      same execution mode as SMM.
+
+  @retval 0    This function did modify the SMRAM save state.
+  @retval > 0  The original instruction pointer value from the SMRAM save state
+               before it was replaced.
+**/
+UINT64
+EFIAPI
+SmmCpuFeaturesHookReturnFromSmm (
+  IN UINTN                 CpuIndex,
+  IN SMRAM_SAVE_STATE_MAP  *CpuState,
+  IN UINT64                NewInstructionPointer32,
+  IN UINT64                NewInstructionPointer
+  )
+{
+  return 0;
+}
+
+/**
+  Read an SMM Save State register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
+  SMM Save Sate register.
+
+  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
+                        value must be between 0 and the NumberOfCpus field in
+                        the System Management System Table (SMST).
+  @param[in]  Register  The SMM Save State register to read.
+  @param[in]  Width     The number of bytes to read from the CPU save state.
+  @param[out] Buffer    Upon return, this holds the CPU register value read
+                        from the save state.
+
+  @retval EFI_SUCCESS           The register was read from Save State.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support reading Register.
+
+**/
+EFI_STATUS
+EFIAPI
+SmmCpuFeaturesReadSaveStateRegister (
+  IN  UINTN                        CpuIndex,
+  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,
+  IN  UINTN                        Width,
+  OUT VOID                         *Buffer
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+/**
+  Writes an SMM Save State register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
+  SMM Save Sate register.
+
+  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
+                       value must be between 0 and the NumberOfCpus field in
+                       the System Management System Table (SMST).
+  @param[in] Register  The SMM Save State register to write.
+  @param[in] Width     The number of bytes to write to the CPU save state.
+  @param[in] Buffer    Upon entry, this holds the new CPU register value.
+
+  @retval EFI_SUCCESS           The register was written to Save State.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support writing Register.
+**/
+EFI_STATUS
+EFIAPI
+SmmCpuFeaturesWriteSaveStateRegister (
+  IN UINTN                        CpuIndex,
+  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
+  IN UINTN                        Width,
+  IN CONST VOID                   *Buffer
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+/**
+  Check to see if an SMM register is supported by a specified CPU.
+
+  @param[in] CpuIndex  The index of the CPU to check for SMM register support.
+                       The value must be between 0 and the NumberOfCpus field
+                       in the System Management System Table (SMST).
+  @param[in] RegName   Identifies the SMM register to check for support.
+
+  @retval TRUE   The SMM register specified by RegName is supported by the CPU
+                 specified by CpuIndex.
+  @retval FALSE  The SMM register specified by RegName is not supported by the
+                 CPU specified by CpuIndex.
+**/
+BOOLEAN
+EFIAPI
+SmmCpuFeaturesIsSmmRegisterSupported (
+  IN UINTN         CpuIndex,
+  IN SMM_REG_NAME  RegName
+  )
+{
+  if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {
+    return TRUE;
+  }
+
+  return FALSE;
+}
+
+/**
+  This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
+  notification is completely processed.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesCompleteSmmReadyToLock (
+  VOID
+  )
+{
+}
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
index 7777e52740eb..2f8841bbbf77 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
@@ -17,49 +17,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 
 #include "CpuFeaturesLib.h"
 
-/**
-  This function updates the SMRAM save state on the currently executing CPU
-  to resume execution at a specific address after an RSM instruction.  This
-  function must evaluate the SMRAM save state to determine the execution mode
-  the RSM instruction resumes and update the resume execution address with
-  either NewInstructionPointer32 or NewInstructionPoint.  The auto HALT restart
-  flag in the SMRAM save state must always be cleared.  This function returns
-  the value of the instruction pointer from the SMRAM save state that was
-  replaced.  If this function returns 0, then the SMRAM save state was not
-  modified.
-
-  This function is called during the very first SMI on each CPU after
-  SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
-  to signal that the SMBASE of each CPU has been updated before the default
-  SMBASE address is used for the first SMI to the next CPU.
-
-  @param[in] CpuIndex                 The index of the CPU to hook.  The value
-                                      must be between 0 and the NumberOfCpus
-                                      field in the System Management System Table
-                                      (SMST).
-  @param[in] CpuState                 Pointer to SMRAM Save State Map for the
-                                      currently executing CPU.
-  @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
-                                      32-bit execution mode from 64-bit SMM.
-  @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
-                                      same execution mode as SMM.
-
-  @retval 0    This function did modify the SMRAM save state.
-  @retval > 0  The original instruction pointer value from the SMRAM save state
-               before it was replaced.
-**/
-UINT64
-EFIAPI
-SmmCpuFeaturesHookReturnFromSmm (
-  IN UINTN                 CpuIndex,
-  IN SMRAM_SAVE_STATE_MAP  *CpuState,
-  IN UINT64                NewInstructionPointer32,
-  IN UINT64                NewInstructionPointer
-  )
-{
-  return 0;
-}
-
 /**
   Hook point in normal execution mode that allows the one CPU that was elected
   as monarch during System Management Mode initialization to perform additional
@@ -90,103 +47,6 @@ SmmCpuFeaturesRendezvousExit (
 {
 }
 
-/**
-  Check to see if an SMM register is supported by a specified CPU.
-
-  @param[in] CpuIndex  The index of the CPU to check for SMM register support.
-                       The value must be between 0 and the NumberOfCpus field
-                       in the System Management System Table (SMST).
-  @param[in] RegName   Identifies the SMM register to check for support.
-
-  @retval TRUE   The SMM register specified by RegName is supported by the CPU
-                 specified by CpuIndex.
-  @retval FALSE  The SMM register specified by RegName is not supported by the
-                 CPU specified by CpuIndex.
-**/
-BOOLEAN
-EFIAPI
-SmmCpuFeaturesIsSmmRegisterSupported (
-  IN UINTN         CpuIndex,
-  IN SMM_REG_NAME  RegName
-  )
-{
-  if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {
-    return TRUE;
-  }
-
-  return FALSE;
-}
-
-/**
-  Read an SMM Save State register on the target processor.  If this function
-  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
-  SMM Save Sate register.
-
-  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
-                        value must be between 0 and the NumberOfCpus field in
-                        the System Management System Table (SMST).
-  @param[in]  Register  The SMM Save State register to read.
-  @param[in]  Width     The number of bytes to read from the CPU save state.
-  @param[out] Buffer    Upon return, this holds the CPU register value read
-                        from the save state.
-
-  @retval EFI_SUCCESS           The register was read from Save State.
-  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
-  @retval EFI_UNSUPPORTED       This function does not support reading Register.
-
-**/
-EFI_STATUS
-EFIAPI
-SmmCpuFeaturesReadSaveStateRegister (
-  IN  UINTN                        CpuIndex,
-  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN  UINTN                        Width,
-  OUT VOID                         *Buffer
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
-/**
-  Writes an SMM Save State register on the target processor.  If this function
-  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
-  SMM Save Sate register.
-
-  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
-                       value must be between 0 and the NumberOfCpus field in
-                       the System Management System Table (SMST).
-  @param[in] Register  The SMM Save State register to write.
-  @param[in] Width     The number of bytes to write to the CPU save state.
-  @param[in] Buffer    Upon entry, this holds the new CPU register value.
-
-  @retval EFI_SUCCESS           The register was written to Save State.
-  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
-  @retval EFI_UNSUPPORTED       This function does not support writing Register.
-**/
-EFI_STATUS
-EFIAPI
-SmmCpuFeaturesWriteSaveStateRegister (
-  IN UINTN                        CpuIndex,
-  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN UINTN                        Width,
-  IN CONST VOID                   *Buffer
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
-/**
-  This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
-  notification is completely processed.
-**/
-VOID
-EFIAPI
-SmmCpuFeaturesCompleteSmmReadyToLock (
-  VOID
-  )
-{
-}
-
 /**
   This API provides a method for a CPU to allocate a specific region for storing page tables.
 
-- 
2.25.1

[PATCH v1 2/5] MdePkg: Adds AMD SMRAM save state map

[Abdul Lateef Attar]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182

Adds an SMM SMRAM save-state map for AMD processors.
SMRAM save state maps for the AMD processor family are now supported.

Save state map structure is added based on
AMD64 Architecture Programmer's Manual, Volume 2, Section 10.2.

The AMD legacy save state map for 32-bit architecture is defined.
The AMD64 save state map for 64-bit architecture is defined. 

Also added Amd/SmramSaveStateMap.h to IgnoreFiles of EccCheck,
because structures defined in this file are derived from
Intel/SmramSaveStateMap.h.

Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Garrett Kirkendall <garrett.kirkendall@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
---
 .../Include/Register/Amd/SmramSaveStateMap.h  | 194 ++++++++++++++++++
 MdePkg/MdePkg.ci.yaml                         |   3 +-
 2 files changed, 196 insertions(+), 1 deletion(-)
 create mode 100644 MdePkg/Include/Register/Amd/SmramSaveStateMap.h

diff --git a/MdePkg/Include/Register/Amd/SmramSaveStateMap.h b/MdePkg/Include/Register/Amd/SmramSaveStateMap.h
new file mode 100644
index 000000000000..6da1538608cf
--- /dev/null
+++ b/MdePkg/Include/Register/Amd/SmramSaveStateMap.h
@@ -0,0 +1,194 @@
+/** @file
+  AMD SMRAM Save State Map Definitions.
+
+  SMRAM Save State Map definitions based on contents of the
+    AMD64 Architecture Programmer Manual:
+    Volume 2, System Programming, Section 10.2 SMM Resources
+
+  Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
+  Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved .<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef AMD_SMRAM_SAVE_STATE_MAP_H_
+#define AMD_SMRAM_SAVE_STATE_MAP_H_
+
+///
+/// Default SMBASE address
+///
+#define SMM_DEFAULT_SMBASE  0x30000
+
+///
+/// Offset of SMM handler from SMBASE
+///
+#define SMM_HANDLER_OFFSET  0x8000
+
+// SMM-Revision Identifier for AMD64 Architecture.
+#define AMD_SMM_MIN_REV_ID_X64  0x30064
+
+#pragma pack (1)
+
+///
+/// 32-bit SMRAM Save State Map
+///
+typedef struct {
+  // Padded an extra 0x200 bytes to match Intel/EDK2
+  UINT8     Reserved[0x200]; // fc00h
+  // AMD Save State area starts @ 0xfe00
+  UINT8     Reserved1[0xf8]; // fe00h
+  UINT32    SMBASE;          // fef8h
+  UINT32    SMMRevId;        // fefch
+  UINT16    IORestart;       // ff00h
+  UINT16    AutoHALTRestart; // ff02h
+  UINT8     Reserved2[0x84]; // ff04h
+  UINT32    GDTBase;         // ff88h
+  UINT64    Reserved3;       // ff8ch
+  UINT32    IDTBase;         // ff94h
+  UINT8     Reserved4[0x10]; // ff98h
+  UINT32    _ES;             // ffa8h
+  UINT32    _CS;             // ffach
+  UINT32    _SS;             // ffb0h
+  UINT32    _DS;             // ffb4h
+  UINT32    _FS;             // ffb8h
+  UINT32    _GS;             // ffbch
+  UINT32    LDTBase;         // ffc0h
+  UINT32    _TR;             // ffc4h
+  UINT32    _DR7;            // ffc8h
+  UINT32    _DR6;            // ffcch
+  UINT32    _EAX;            // ffd0h
+  UINT32    _ECX;            // ffd4h
+  UINT32    _EDX;            // ffd8h
+  UINT32    _EBX;            // ffdch
+  UINT32    _ESP;            // ffe0h
+  UINT32    _EBP;            // ffe4h
+  UINT32    _ESI;            // ffe8h
+  UINT32    _EDI;            // ffech
+  UINT32    _EIP;            // fff0h
+  UINT32    _EFLAGS;         // fff4h
+  UINT32    _CR3;            // fff8h
+  UINT32    _CR0;            // fffch
+} AMD_SMRAM_SAVE_STATE_MAP32;
+
+///
+/// 64-bit SMRAM Save State Map
+///
+typedef struct {
+  // Padded an extra 0x200 bytes to match Intel/EDK2
+  UINT8     Reserved[0x200]; // fc00h
+  // AMD Save State area starts @ 0xfe00
+  UINT16    _ES;              // fe00h
+  UINT16    _ESAttributes;    // fe02h
+  UINT32    _ESLimit;         // fe04h
+  UINT64    _ESBase;          // fe08h
+
+  UINT16    _CS;              // fe10h
+  UINT16    _CSAttributes;    // fe12h
+  UINT32    _CSLimit;         // fe14h
+  UINT64    _CSBase;          // fe18h
+
+  UINT16    _SS;              // fe20h
+  UINT16    _SSAttributes;    // fe22h
+  UINT32    _SSLimit;         // fe24h
+  UINT64    _SSBase;          // fe28h
+
+  UINT16    _DS;              // fe30h
+  UINT16    _DSAttributes;    // fe32h
+  UINT32    _DSLimit;         // fe34h
+  UINT64    _DSBase;          // fe38h
+
+  UINT16    _FS;              // fe40h
+  UINT16    _FSAttributes;    // fe42h
+  UINT32    _FSLimit;         // fe44h
+  UINT64    _FSBase;          // fe48h
+
+  UINT16    _GS;              // fe50h
+  UINT16    _GSAttributes;    // fe52h
+  UINT32    _GSLimit;         // fe54h
+  UINT64    _GSBase;          // fe58h
+
+  UINT32    _GDTRReserved1;   // fe60h
+  UINT16    _GDTRLimit;       // fe64h
+  UINT16    _GDTRReserved2;   // fe66h
+  // UINT64  _GDTRBase;        // fe68h
+  UINT32    _GDTRBaseLoDword;
+  UINT32    _GDTRBaseHiDword;
+
+  UINT16    _LDTR;            // fe70h
+  UINT16    _LDTRAttributes;  // fe72h
+  UINT32    _LDTRLimit;       // fe74h
+  // UINT64  _LDTRBase;        // fe78h
+  UINT32    _LDTRBaseLoDword;
+  UINT32    _LDTRBaseHiDword;
+
+  UINT32    _IDTRReserved1;   // fe80h
+  UINT16    _IDTRLimit;       // fe84h
+  UINT16    _IDTRReserved2;   // fe86h
+  // UINT64  _IDTRBase;        // fe88h
+  UINT32    _IDTRBaseLoDword;
+  UINT32    _IDTRBaseHiDword;
+
+  UINT16    _TR;              // fe90h
+  UINT16    _TRAttributes;    // fe92h
+  UINT32    _TRLimit;         // fe94h
+  UINT64    _TRBase;          // fe98h
+
+  UINT64    IO_RIP;           // fea0h
+  UINT64    IO_RCX;           // fea8h
+  UINT64    IO_RSI;           // feb0h
+  UINT64    IO_RDI;           // feb8h
+  UINT32    IO_DWord;         // fec0h
+  UINT8     Reserved1[0x04];  // fec4h
+  UINT8     IORestart;        // fec8h
+  UINT8     AutoHALTRestart;  // fec9h
+  UINT8     Reserved2[0x06];  // fecah
+  UINT64    EFER;             // fed0h
+  UINT64    SVM_Guest;        // fed8h
+  UINT64    SVM_GuestVMCB;    // fee0h
+  UINT64    SVM_GuestVIntr;   // fee8h
+  UINT8     Reserved3[0x0c];  // fef0h
+  UINT32    SMMRevId;         // fefch
+  UINT32    SMBASE;           // ff00h
+  UINT8     Reserved4[0x14];  // ff04h
+  UINT64    SSP;              // ff18h
+  UINT64    SVM_GuestPAT;     // ff20h
+  UINT64    SVM_HostEFER;     // ff28h
+  UINT64    SVM_HostCR4;      // ff30h
+  UINT64    SVM_HostCR3;      // ff38h
+  UINT64    SVM_HostCR0;      // ff40h
+  UINT64    _CR4;             // ff48h
+  UINT64    _CR3;             // ff50h
+  UINT64    _CR0;             // ff58h
+  UINT64    _DR7;             // ff60h
+  UINT64    _DR6;             // ff68h
+  UINT64    _RFLAGS;          // ff70h
+  UINT64    _RIP;             // ff78h
+  UINT64    _R15;             // ff80h
+  UINT64    _R14;             // ff88h
+  UINT64    _R13;             // ff90h
+  UINT64    _R12;             // ff98h
+  UINT64    _R11;             // ffa0h
+  UINT64    _R10;             // ffa8h
+  UINT64    _R9;              // ffb0h
+  UINT64    _R8;              // ffb8h
+  UINT64    _RDI;             // ffc0h
+  UINT64    _RSI;             // ffc8h
+  UINT64    _RBP;             // ffd0h
+  UINT64    _RSP;             // ffd8h
+  UINT64    _RBX;             // ffe0h
+  UINT64    _RDX;             // ffe8h
+  UINT64    _RCX;             // fff0h
+  UINT64    _RAX;             // fff8h
+} AMD_SMRAM_SAVE_STATE_MAP64;
+
+///
+/// Union of 32-bit and 64-bit SMRAM Save State Maps
+///
+typedef union  {
+  AMD_SMRAM_SAVE_STATE_MAP32    x86;
+  AMD_SMRAM_SAVE_STATE_MAP64    x64;
+} AMD_SMRAM_SAVE_STATE_MAP;
+
+#pragma pack ()
+
+#endif
diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml
index 19bc0138cb76..86c9c502d799 100644
--- a/MdePkg/MdePkg.ci.yaml
+++ b/MdePkg/MdePkg.ci.yaml
@@ -65,7 +65,8 @@
             "Include/Library/PcdLib.h",
             "Include/Library/SafeIntLib.h",
             "Include/Protocol/DebugSupport.h",
-            "Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c"
+            "Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c",
+            "Include/Register/Amd/SmramSaveStateMap.h"
         ]
     },
     ## options defined ci/Plugin/CompilerPlugin
-- 
2.25.1

[PATCH v1 3/5] UefiCpuPkg: Initial implementation of AMD's SmmCpuFeaturesLib

[Abdul Lateef Attar]

From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182

Adds initial defination for AMD's SmmCpuFeaturesLib
library implementation.
All function's body either empty or just returns
value. Its initial skeleton of library implementation.

Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Garrett Kirkendall <garrett.kirkendall@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
---
 UefiCpuPkg/UefiCpuPkg.dsc                     |   9 +
 .../AmdSmmCpuFeaturesLib.inf                  |  37 ++
 .../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c | 357 ++++++++++++++++++
 3 files changed, 403 insertions(+)
 create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
 create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c

diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index 67b0ce46e455..8aeaf992af9b 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -2,6 +2,7 @@
 #  UefiCpuPkg Package
 #
 #  Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>
+#  Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.<BR>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -160,6 +161,7 @@ [Components.IA32, Components.X64]
   UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.inf
   UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf
   UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf
+  UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
   UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
   UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
   UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf
@@ -176,6 +178,13 @@ [Components.IA32, Components.X64]
     <LibraryClasses>
       SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
   }
+  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {
+    <Defines>
+      FILE_GUID = B7242C74-BD21-49EE-84B4-07162E8C080D
+    <LibraryClasses>
+      SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
+      SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf
+  }
   UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
   UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
   UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
new file mode 100644
index 000000000000..08ac0262022f
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
@@ -0,0 +1,37 @@
+## @file
+#  The CPU specific programming for PiSmmCpuDxeSmm module.
+#
+#  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+#  Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.<BR>
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SmmCpuFeaturesLib
+  MODULE_UNI_FILE                = SmmCpuFeaturesLib.uni
+  FILE_GUID                      = 5849E964-78EC-428E-8CBD-848A7E359134
+  MODULE_TYPE                    = DXE_SMM_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SmmCpuFeaturesLib
+  CONSTRUCTOR                    = SmmCpuFeaturesLibConstructor
+
+[Sources]
+  SmmCpuFeaturesLib.c
+  SmmCpuFeaturesLibCommon.c
+  Amd/SmmCpuFeaturesLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  PcdLib
+  MemoryAllocationLib
+  DebugLib
+
+[FeaturePcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable               ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable  ## CONSUMES
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
new file mode 100644
index 000000000000..dc3fed0302d2
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
@@ -0,0 +1,357 @@
+/** @file
+Implementation specific to the SmmCpuFeatureLib library instance
+for AMD based platforms.
+
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) Microsoft Corporation.<BR>
+Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/SmmCpuFeaturesLib.h>
+#include <Uefi/UefiBaseType.h>
+
+/**
+  Read an SMM Save State register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
+  SMM Save Sate register.
+
+  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
+                        value must be between 0 and the NumberOfCpus field in
+                        the System Management System Table (SMST).
+  @param[in]  Register  The SMM Save State register to read.
+  @param[in]  Width     The number of bytes to read from the CPU save state.
+  @param[out] Buffer    Upon return, this holds the CPU register value read
+                        from the save state.
+
+  @retval EFI_SUCCESS           The register was read from Save State.
+  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support reading Register.
+
+**/
+EFI_STATUS
+EFIAPI
+SmmCpuFeaturesReadSaveStateRegister (
+  IN  UINTN                        CpuIndex,
+  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,
+  IN  UINTN                        Width,
+  OUT VOID                         *Buffer
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Writes an SMM Save State register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
+  SMM Save Sate register.
+
+  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
+                       value must be between 0 and the NumberOfCpus field in
+                       the System Management System Table (SMST).
+  @param[in] Register  The SMM Save State register to write.
+  @param[in] Width     The number of bytes to write to the CPU save state.
+  @param[in] Buffer    Upon entry, this holds the new CPU register value.
+
+  @retval EFI_SUCCESS           The register was written to Save State.
+  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support writing Register.
+**/
+EFI_STATUS
+EFIAPI
+SmmCpuFeaturesWriteSaveStateRegister (
+  IN UINTN                        CpuIndex,
+  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
+  IN UINTN                        Width,
+  IN CONST VOID                   *Buffer
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Performs library initialization.
+
+  This initialization function contains common functionality shared betwen all
+  library instance constructors.
+
+**/
+VOID
+CpuFeaturesLibInitialization (
+  VOID
+  )
+{
+}
+
+/**
+  Called during the very first SMI into System Management Mode to initialize
+  CPU features, including SMBASE, for the currently executing CPU.  Since this
+  is the first SMI, the SMRAM Save State Map is at the default address of
+  AMD_SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET.  The currently executing
+  CPU is specified by CpuIndex and CpuIndex can be used to access information
+  about the currently executing CPU in the ProcessorInfo array and the
+  HotPlugCpuData data structure.
+
+  @param[in] CpuIndex        The index of the CPU to initialize.  The value
+                             must be between 0 and the NumberOfCpus field in
+                             the System Management System Table (SMST).
+  @param[in] IsMonarch       TRUE if the CpuIndex is the index of the CPU that
+                             was elected as monarch during System Management
+                             Mode initialization.
+                             FALSE if the CpuIndex is not the index of the CPU
+                             that was elected as monarch during System
+                             Management Mode initialization.
+  @param[in] ProcessorInfo   Pointer to an array of EFI_PROCESSOR_INFORMATION
+                             structures.  ProcessorInfo[CpuIndex] contains the
+                             information for the currently executing CPU.
+  @param[in] CpuHotPlugData  Pointer to the CPU_HOT_PLUG_DATA structure that
+                             contains the ApidId and SmBase arrays.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesInitializeProcessor (
+  IN UINTN                      CpuIndex,
+  IN BOOLEAN                    IsMonarch,
+  IN EFI_PROCESSOR_INFORMATION  *ProcessorInfo,
+  IN CPU_HOT_PLUG_DATA          *CpuHotPlugData
+  )
+{
+}
+
+/**
+  This function updates the SMRAM save state on the currently executing CPU
+  to resume execution at a specific address after an RSM instruction.  This
+  function must evaluate the SMRAM save state to determine the execution mode
+  the RSM instruction resumes and update the resume execution address with
+  either NewInstructionPointer32 or NewInstructionPoint.  The auto HALT restart
+  flag in the SMRAM save state must always be cleared.  This function returns
+  the value of the instruction pointer from the SMRAM save state that was
+  replaced.  If this function returns 0, then the SMRAM save state was not
+  modified.
+
+  This function is called during the very first SMI on each CPU after
+  SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
+  to signal that the SMBASE of each CPU has been updated before the default
+  SMBASE address is used for the first SMI to the next CPU.
+
+  @param[in] CpuIndex                 The index of the CPU to hook.  The value
+                                      must be between 0 and the NumberOfCpus
+                                      field in the System Management System Table
+                                      (SMST).
+  @param[in] CpuState                 Pointer to SMRAM Save State Map for the
+                                      currently executing CPU.
+  @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
+                                      32-bit execution mode from 64-bit SMM.
+  @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
+                                      same execution mode as SMM.
+
+  @retval 0    This function did modify the SMRAM save state.
+  @retval > 0  The original instruction pointer value from the SMRAM save state
+               before it was replaced.
+**/
+UINT64
+EFIAPI
+SmmCpuFeaturesHookReturnFromSmm (
+  IN UINTN                 CpuIndex,
+  IN SMRAM_SAVE_STATE_MAP  *CpuState,
+  IN UINT64                NewInstructionPointer32,
+  IN UINT64                NewInstructionPointer
+  )
+{
+  return 0;
+}
+
+/**
+  Return the size, in bytes, of a custom SMI Handler in bytes.  If 0 is
+  returned, then a custom SMI handler is not provided by this library,
+  and the default SMI handler must be used.
+
+  @retval 0    Use the default SMI handler.
+  @retval > 0  Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
+               The caller is required to allocate enough SMRAM for each CPU to
+               support the size of the custom SMI handler.
+**/
+UINTN
+EFIAPI
+SmmCpuFeaturesGetSmiHandlerSize (
+  VOID
+  )
+{
+  return 0;
+}
+
+/**
+  Install a custom SMI handler for the CPU specified by CpuIndex.  This function
+  is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
+  than zero and is called by the CPU that was elected as monarch during System
+  Management Mode initialization.
+
+  @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.
+                        The value must be between 0 and the NumberOfCpus field
+                        in the System Management System Table (SMST).
+  @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.
+  @param[in] SmiStack   The stack to use when an SMI is processed by the
+                        the CPU specified by CpuIndex.
+  @param[in] StackSize  The size, in bytes, if the stack used when an SMI is
+                        processed by the CPU specified by CpuIndex.
+  @param[in] GdtBase    The base address of the GDT to use when an SMI is
+                        processed by the CPU specified by CpuIndex.
+  @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is
+                        processed by the CPU specified by CpuIndex.
+  @param[in] IdtBase    The base address of the IDT to use when an SMI is
+                        processed by the CPU specified by CpuIndex.
+  @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is
+                        processed by the CPU specified by CpuIndex.
+  @param[in] Cr3        The base address of the page tables to use when an SMI
+                        is processed by the CPU specified by CpuIndex.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesInstallSmiHandler (
+  IN UINTN   CpuIndex,
+  IN UINT32  SmBase,
+  IN VOID    *SmiStack,
+  IN UINTN   StackSize,
+  IN UINTN   GdtBase,
+  IN UINTN   GdtSize,
+  IN UINTN   IdtBase,
+  IN UINTN   IdtSize,
+  IN UINT32  Cr3
+  )
+{
+}
+
+/**
+  Determines if MTRR registers must be configured to set SMRAM cache-ability
+  when executing in System Management Mode.
+
+  @retval TRUE   MTRR registers must be configured to set SMRAM cache-ability.
+  @retval FALSE  MTRR registers do not need to be configured to set SMRAM
+                 cache-ability.
+**/
+BOOLEAN
+EFIAPI
+SmmCpuFeaturesNeedConfigureMtrrs (
+  VOID
+  )
+{
+  return FALSE;
+}
+
+/**
+  Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
+  returns TRUE.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesDisableSmrr (
+  VOID
+  )
+{
+}
+
+/**
+  Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
+  returns TRUE.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesReenableSmrr (
+  VOID
+  )
+{
+}
+
+/**
+  Processor specific hook point each time a CPU enters System Management Mode.
+
+  @param[in] CpuIndex  The index of the CPU that has entered SMM.  The value
+                       must be between 0 and the NumberOfCpus field in the
+                       System Management System Table (SMST).
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesRendezvousEntry (
+  IN UINTN  CpuIndex
+  )
+{
+}
+
+/**
+  Returns the current value of the SMM register for the specified CPU.
+  If the SMM register is not supported, then 0 is returned.
+
+  @param[in] CpuIndex  The index of the CPU to read the SMM register.  The
+                       value must be between 0 and the NumberOfCpus field in
+                       the System Management System Table (SMST).
+  @param[in] RegName   Identifies the SMM register to read.
+
+  @return  The value of the SMM register specified by RegName from the CPU
+           specified by CpuIndex.
+**/
+UINT64
+EFIAPI
+SmmCpuFeaturesGetSmmRegister (
+  IN UINTN         CpuIndex,
+  IN SMM_REG_NAME  RegName
+  )
+{
+  return 0;
+}
+
+/**
+  Sets the value of an SMM register on a specified CPU.
+  If the SMM register is not supported, then no action is performed.
+
+  @param[in] CpuIndex  The index of the CPU to write the SMM register.  The
+                       value must be between 0 and the NumberOfCpus field in
+                       the System Management System Table (SMST).
+  @param[in] RegName   Identifies the SMM register to write.
+                       registers are read-only.
+  @param[in] Value     The value to write to the SMM register.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesSetSmmRegister (
+  IN UINTN         CpuIndex,
+  IN SMM_REG_NAME  RegName,
+  IN UINT64        Value
+  )
+{
+}
+
+/**
+  Check to see if an SMM register is supported by a specified CPU.
+
+  @param[in] CpuIndex  The index of the CPU to check for SMM register support.
+                       The value must be between 0 and the NumberOfCpus field
+                       in the System Management System Table (SMST).
+  @param[in] RegName   Identifies the SMM register to check for support.
+
+  @retval TRUE   The SMM register specified by RegName is supported by the CPU
+                 specified by CpuIndex.
+  @retval FALSE  The SMM register specified by RegName is not supported by the
+                 CPU specified by CpuIndex.
+**/
+BOOLEAN
+EFIAPI
+SmmCpuFeaturesIsSmmRegisterSupported (
+  IN UINTN         CpuIndex,
+  IN SMM_REG_NAME  RegName
+  )
+{
+  return FALSE;
+}
+
+/**
+  This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
+  notification is completely processed.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesCompleteSmmReadyToLock (
+  VOID
+  )
+{
+}
-- 
2.25.1

[PATCH v1 4/5] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family

[Abdul Lateef Attar]

From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182

Implements interfaces to read and write save state
registers of AMD's processor family.
Initializes processor SMMADDR and MASK depends
on PcdSmrrEnable flag.
Program or corrects the IP once control returns from SMM.

Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Garrett Kirkendall <garrett.kirkendall@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
---
 .../AmdSmmCpuFeaturesLib.inf                  |   2 +
 .../SmmCpuFeaturesLib/Amd/SmramSaveState.h    | 109 +++++
 .../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c |  97 ++++-
 .../SmmCpuFeaturesLib/Amd/SmramSaveState.c    | 409 ++++++++++++++++++
 4 files changed, 612 insertions(+), 5 deletions(-)
 create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
 create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.c

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
index 08ac0262022f..95eb31d16ead 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
@@ -21,6 +21,8 @@ [Sources]
   SmmCpuFeaturesLib.c
   SmmCpuFeaturesLibCommon.c
   Amd/SmmCpuFeaturesLib.c
+  Amd/SmramSaveState.c
+  Amd/SmramSaveState.h
 
 [Packages]
   MdePkg/MdePkg.dec
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
new file mode 100644
index 000000000000..290ebdbc9227
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
@@ -0,0 +1,109 @@
+/** @file
+SMRAM Save State Map header file.
+
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SMRAM_SAVESTATE_H_
+#define SMRAM_SAVESTATE_H_
+
+#include <Library/SmmCpuFeaturesLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Register/Amd/SmramSaveStateMap.h>
+
+// EFER register LMA bit
+#define LMA  BIT10
+
+// Machine Specific Registers (MSRs)
+#define SMMADDR_ADDRESS  0xC0010112ul
+#define SMMMASK_ADDRESS  0xC0010113ul
+#define EFER_ADDRESS     0XC0000080ul
+
+// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
+#define SMM_CPU_OFFSET(Field)  OFFSET_OF (AMD_SMRAM_SAVE_STATE_MAP, Field)
+
+// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE
+#define SMM_REGISTER_RANGE(Start, End)  { Start, End, End - Start + 1 }
+
+// Structure used to describe a range of registers
+typedef struct {
+  EFI_SMM_SAVE_STATE_REGISTER    Start;
+  EFI_SMM_SAVE_STATE_REGISTER    End;
+  UINTN                          Length;
+} CPU_SMM_SAVE_STATE_REGISTER_RANGE;
+
+// Structure used to build a lookup table to retrieve the widths and offsets
+// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
+
+#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX  1
+#define SMM_SAVE_STATE_REGISTER_MAX_INDEX       2
+
+typedef struct {
+  UINT8      Width32;
+  UINT8      Width64;
+  UINT16     Offset32;
+  UINT16     Offset64Lo;
+  UINT16     Offset64Hi;
+  BOOLEAN    Writeable;
+} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
+
+/**
+  Read an SMM Save State register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
+  SMM Save Sate register.
+
+  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
+                        value must be between 0 and the NumberOfCpus field in
+                        the System Management System Table (SMST).
+  @param[in]  Register  The SMM Save State register to read.
+  @param[in]  Width     The number of bytes to read from the CPU save state.
+  @param[out] Buffer    Upon return, this holds the CPU register value read
+                        from the save state.
+
+  @retval EFI_SUCCESS           The register was read from Save State.
+  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support reading Register.
+
+**/
+EFI_STATUS
+EFIAPI
+InternalSmmCpuFeaturesReadSaveStateRegister (
+  IN  UINTN                        CpuIndex,
+  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,
+  IN  UINTN                        Width,
+  OUT VOID                         *Buffer
+  );
+
+/**
+  Writes an SMM Save State register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
+  SMM Save Sate register.
+
+  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
+                       value must be between 0 and the NumberOfCpus field in
+                       the System Management System Table (SMST).
+  @param[in] Register  The SMM Save State register to write.
+  @param[in] Width     The number of bytes to write to the CPU save state.
+  @param[in] Buffer    Upon entry, this holds the new CPU register value.
+
+  @retval EFI_SUCCESS           The register was written to Save State.
+  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support writing Register.
+**/
+EFI_STATUS
+EFIAPI
+InternalSmmCpuFeaturesWriteSaveStateRegister (
+  IN UINTN                        CpuIndex,
+  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
+  IN UINTN                        Width,
+  IN CONST VOID                   *Buffer
+  );
+
+#endif
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
index dc3fed0302d2..10bed4116397 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
@@ -9,8 +9,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
-#include <Library/SmmCpuFeaturesLib.h>
-#include <Uefi/UefiBaseType.h>
+#include "SmramSaveState.h"
+
+// The mode of the CPU at the time an SMI occurs
+extern UINT8  mSmmSaveStateRegisterLma;
 
 /**
   Read an SMM Save State register on the target processor.  If this function
@@ -39,7 +41,7 @@ SmmCpuFeaturesReadSaveStateRegister (
   OUT VOID                         *Buffer
   )
 {
-  return EFI_SUCCESS;
+  return InternalSmmCpuFeaturesReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
 }
 
 /**
@@ -67,7 +69,7 @@ SmmCpuFeaturesWriteSaveStateRegister (
   IN CONST VOID                   *Buffer
   )
 {
-  return EFI_SUCCESS;
+  return InternalSmmCpuFeaturesWriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
 }
 
 /**
@@ -82,6 +84,13 @@ CpuFeaturesLibInitialization (
   VOID
   )
 {
+  UINT32  LMAValue;
+
+  LMAValue                 = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
+  mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
+  if (LMAValue) {
+    mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
+  }
 }
 
 /**
@@ -117,6 +126,52 @@ SmmCpuFeaturesInitializeProcessor (
   IN CPU_HOT_PLUG_DATA          *CpuHotPlugData
   )
 {
+  AMD_SMRAM_SAVE_STATE_MAP  *CpuState;
+  UINT32                    LMAValue;
+
+  //
+  // Configure SMBASE.
+  //
+  CpuState             = (AMD_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
+  CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
+
+  // Re-initialize the value of mSmmSaveStateRegisterLma flag which might have been changed in PiCpuSmmDxeSmm Driver
+  // Entry point, to make sure correct value on AMD platform is assigned to be used by SmmCpuFeaturesLib.
+  LMAValue                 = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
+  mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
+  if (LMAValue) {
+    mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
+  }
+
+  //
+  // If SMRR is supported, then program SMRR base/mask MSRs.
+  // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.
+  // The code that initializes SMM environment is running in normal mode
+  // from SMRAM region.  If SMRR is enabled here, then the SMRAM region
+  // is protected and the normal mode code execution will fail.
+  //
+  if (FeaturePcdGet (PcdSmrrEnable)) {
+    //
+    // SMRR size cannot be less than 4-KBytes
+    // SMRR size must be of length 2^n
+    // SMRR base alignment cannot be less than SMRR length
+    //
+    if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||
+        (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||
+        ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase))
+    {
+      //
+      // Print message and halt if CPU is Monarch
+      //
+      if (IsMonarch) {
+        DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));
+        CpuDeadLoop ();
+      }
+    } else {
+      AsmWriteMsr64 (SMMADDR_ADDRESS, CpuHotPlugData->SmrrBase);
+      AsmWriteMsr64 (SMMMASK_ADDRESS, ((~(UINT64)(CpuHotPlugData->SmrrSize - 1)) | 0x6600));
+    }
+  }
 }
 
 /**
@@ -159,7 +214,39 @@ SmmCpuFeaturesHookReturnFromSmm (
   IN UINT64                NewInstructionPointer
   )
 {
-  return 0;
+  UINT64                    OriginalInstructionPointer;
+  AMD_SMRAM_SAVE_STATE_MAP  *AmdCpuState;
+
+  AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState;
+
+  if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
+    OriginalInstructionPointer = (UINT64)AmdCpuState->x86._EIP;
+    AmdCpuState->x86._EIP      = (UINT32)NewInstructionPointer;
+    //
+    // Clear the auto HALT restart flag so the RSM instruction returns
+    // program control to the instruction following the HLT instruction.
+    //
+    if ((AmdCpuState->x86.AutoHALTRestart & BIT0) != 0) {
+      AmdCpuState->x86.AutoHALTRestart &= ~BIT0;
+    }
+  } else {
+    OriginalInstructionPointer = AmdCpuState->x64._RIP;
+    if ((AmdCpuState->x64.EFER & LMA) == 0) {
+      AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer32;
+    } else {
+      AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer;
+    }
+
+    //
+    // Clear the auto HALT restart flag so the RSM instruction returns
+    // program control to the instruction following the HLT instruction.
+    //
+    if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != 0) {
+      AmdCpuState->x64.AutoHALTRestart &= ~BIT0;
+    }
+  }
+
+  return OriginalInstructionPointer;
 }
 
 /**
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.c
new file mode 100644
index 000000000000..c1e7e6d6c6d9
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.c
@@ -0,0 +1,409 @@
+/** @file
+Provides services to access SMRAM Save State Map
+
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "SmramSaveState.h"
+
+// The mode of the CPU at the time an SMI occurs
+extern UINT8  mSmmSaveStateRegisterLma;
+
+// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
+// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
+static CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE  mSmmCpuRegisterRanges[] = {
+  SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),
+  SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES,      EFI_SMM_SAVE_STATE_REGISTER_RIP),
+  SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,  EFI_SMM_SAVE_STATE_REGISTER_CR4),
+  { (EFI_SMM_SAVE_STATE_REGISTER)0,                        (EFI_SMM_SAVE_STATE_REGISTER)0,      0}
+};
+
+// Lookup table used to retrieve the widths and offsets associated with each
+// supported EFI_SMM_SAVE_STATE_REGISTER value
+static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY  mSmmCpuWidthOffset[] = {
+  { 0, 0, 0,                             0,                                     FALSE },                                          //  Reserved
+
+  //
+  // Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.
+  //
+  { 4, 4, SMM_CPU_OFFSET (x86.SMMRevId), SMM_CPU_OFFSET (x64.SMMRevId),         0, FALSE},                                        // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX  = 1
+
+  //
+  // CPU Save State registers defined in PI SMM CPU Protocol.
+  //
+  { 4, 8, SMM_CPU_OFFSET (x86.GDTBase),  SMM_CPU_OFFSET (x64._GDTRBaseLoDword), SMM_CPU_OFFSET (x64._GDTRBaseHiDword), FALSE},    //  EFI_SMM_SAVE_STATE_REGISTER_GDTBASE  = 4
+  { 0, 8, 0,                             SMM_CPU_OFFSET (x64._IDTRBaseLoDword), SMM_CPU_OFFSET (x64._IDTRBaseLoDword), FALSE},    //  EFI_SMM_SAVE_STATE_REGISTER_IDTBASE  = 5
+  { 0, 8, 0,                             SMM_CPU_OFFSET (x64._LDTRBaseLoDword), SMM_CPU_OFFSET (x64._LDTRBaseLoDword), FALSE},    //  EFI_SMM_SAVE_STATE_REGISTER_LDTBASE  = 6
+  { 0, 2, 0,                             SMM_CPU_OFFSET (x64._GDTRLimit),       0, FALSE},                                        //  EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
+  { 0, 2, 0,                             SMM_CPU_OFFSET (x64._IDTRLimit),       0, FALSE},                                        //  EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
+  { 0, 4, 0,                             SMM_CPU_OFFSET (x64._LDTRLimit),       0, FALSE},                                        //  EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
+  { 0, 0, 0,                             0,                                     0, FALSE},                                        //  EFI_SMM_SAVE_STATE_REGISTER_LDTINFO  = 10
+  { 4, 2, SMM_CPU_OFFSET (x86._ES),      SMM_CPU_OFFSET (x64._ES),              0, FALSE},                                        //  EFI_SMM_SAVE_STATE_REGISTER_ES       = 20
+  { 4, 2, SMM_CPU_OFFSET (x86._CS),      SMM_CPU_OFFSET (x64._CS),              0, FALSE},                                        //  EFI_SMM_SAVE_STATE_REGISTER_CS       = 21
+  { 4, 2, SMM_CPU_OFFSET (x86._SS),      SMM_CPU_OFFSET (x64._SS),              0, FALSE},                                        //  EFI_SMM_SAVE_STATE_REGISTER_SS       = 22
+  { 4, 2, SMM_CPU_OFFSET (x86._DS),      SMM_CPU_OFFSET (x64._DS),              0, FALSE},                                        //  EFI_SMM_SAVE_STATE_REGISTER_DS       = 23
+  { 4, 2, SMM_CPU_OFFSET (x86._FS),      SMM_CPU_OFFSET (x64._FS),              0, FALSE},                                        //  EFI_SMM_SAVE_STATE_REGISTER_FS       = 24
+  { 4, 2, SMM_CPU_OFFSET (x86._GS),      SMM_CPU_OFFSET (x64._GS),              0, FALSE},                                        //  EFI_SMM_SAVE_STATE_REGISTER_GS       = 25
+  { 0, 2, 0,                             SMM_CPU_OFFSET (x64._LDTR),            0, FALSE},                                        //  EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
+  { 0, 2, 0,                             SMM_CPU_OFFSET (x64._TR),              0, FALSE},                                        //  EFI_SMM_SAVE_STATE_REGISTER_TR_SEL   = 27
+  { 4, 8, SMM_CPU_OFFSET (x86._DR7),     SMM_CPU_OFFSET (x64._DR7),             SMM_CPU_OFFSET (x64._DR7)         + 4, FALSE},    //  EFI_SMM_SAVE_STATE_REGISTER_DR7      = 28
+  { 4, 8, SMM_CPU_OFFSET (x86._DR6),     SMM_CPU_OFFSET (x64._DR6),             SMM_CPU_OFFSET (x64._DR6)         + 4, FALSE},    //  EFI_SMM_SAVE_STATE_REGISTER_DR6      = 29
+  { 0, 8, 0,                             SMM_CPU_OFFSET (x64._R8),              SMM_CPU_OFFSET (x64._R8)          + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_R8       = 30
+  { 0, 8, 0,                             SMM_CPU_OFFSET (x64._R9),              SMM_CPU_OFFSET (x64._R9)          + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_R9       = 31
+  { 0, 8, 0,                             SMM_CPU_OFFSET (x64._R10),             SMM_CPU_OFFSET (x64._R10)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_R10      = 32
+  { 0, 8, 0,                             SMM_CPU_OFFSET (x64._R11),             SMM_CPU_OFFSET (x64._R11)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_R11      = 33
+  { 0, 8, 0,                             SMM_CPU_OFFSET (x64._R12),             SMM_CPU_OFFSET (x64._R12)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_R12      = 34
+  { 0, 8, 0,                             SMM_CPU_OFFSET (x64._R13),             SMM_CPU_OFFSET (x64._R13)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_R13      = 35
+  { 0, 8, 0,                             SMM_CPU_OFFSET (x64._R14),             SMM_CPU_OFFSET (x64._R14)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_R14      = 36
+  { 0, 8, 0,                             SMM_CPU_OFFSET (x64._R15),             SMM_CPU_OFFSET (x64._R15)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_R15      = 37
+  { 4, 8, SMM_CPU_OFFSET (x86._EAX),     SMM_CPU_OFFSET (x64._RAX),             SMM_CPU_OFFSET (x64._RAX)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_RAX      = 38
+  { 4, 8, SMM_CPU_OFFSET (x86._EBX),     SMM_CPU_OFFSET (x64._RBX),             SMM_CPU_OFFSET (x64._RBX)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_RBX      = 39
+  { 4, 8, SMM_CPU_OFFSET (x86._ECX),     SMM_CPU_OFFSET (x64._RCX),             SMM_CPU_OFFSET (x64._RCX)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_RBX      = 39
+  { 4, 8, SMM_CPU_OFFSET (x86._EDX),     SMM_CPU_OFFSET (x64._RDX),             SMM_CPU_OFFSET (x64._RDX)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_RDX      = 41
+  { 4, 8, SMM_CPU_OFFSET (x86._ESP),     SMM_CPU_OFFSET (x64._RSP),             SMM_CPU_OFFSET (x64._RSP)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_RSP      = 42
+  { 4, 8, SMM_CPU_OFFSET (x86._EBP),     SMM_CPU_OFFSET (x64._RBP),             SMM_CPU_OFFSET (x64._RBP)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_RBP      = 43
+  { 4, 8, SMM_CPU_OFFSET (x86._ESI),     SMM_CPU_OFFSET (x64._RSI),             SMM_CPU_OFFSET (x64._RSI)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_RSI      = 44
+  { 4, 8, SMM_CPU_OFFSET (x86._EDI),     SMM_CPU_OFFSET (x64._RDI),             SMM_CPU_OFFSET (x64._RDI)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_RDI      = 45
+  { 4, 8, SMM_CPU_OFFSET (x86._EIP),     SMM_CPU_OFFSET (x64._RIP),             SMM_CPU_OFFSET (x64._RIP)         + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_RIP      = 46
+
+  { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS),  SMM_CPU_OFFSET (x64._RFLAGS),          SMM_CPU_OFFSET (x64._RFLAGS)      + 4, TRUE},     //  EFI_SMM_SAVE_STATE_REGISTER_RFLAGS   = 51
+  { 4, 8, SMM_CPU_OFFSET (x86._CR0),     SMM_CPU_OFFSET (x64._CR0),             SMM_CPU_OFFSET (x64._CR0)         + 4, FALSE},    //  EFI_SMM_SAVE_STATE_REGISTER_CR0      = 52
+  { 4, 8, SMM_CPU_OFFSET (x86._CR3),     SMM_CPU_OFFSET (x64._CR3),             SMM_CPU_OFFSET (x64._CR3)         + 4, FALSE},    //  EFI_SMM_SAVE_STATE_REGISTER_CR3      = 53
+  { 0, 8, 0,                             SMM_CPU_OFFSET (x64._CR4),             SMM_CPU_OFFSET (x64._CR4)         + 4, FALSE},    //  EFI_SMM_SAVE_STATE_REGISTER_CR4      = 54
+  { 0, 0, 0,                             0,                                     0     }
+};
+
+/**
+  Read information from the CPU save state.
+
+  @param  Register  Specifies the CPU register to read form the save state.
+
+  @retval 0   Register is not valid
+  @retval >0  Index into mSmmCpuWidthOffset[] associated with Register
+
+**/
+STATIC
+UINTN
+EFIAPI
+GetRegisterIndex (
+  IN EFI_SMM_SAVE_STATE_REGISTER  Register
+  )
+{
+  UINTN  Index;
+  UINTN  Offset;
+
+  for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {
+    if ((Register >= mSmmCpuRegisterRanges[Index].Start) && (Register <= mSmmCpuRegisterRanges[Index].End)) {
+      return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
+    }
+
+    Offset += mSmmCpuRegisterRanges[Index].Length;
+  }
+
+  return 0;
+}
+
+/**
+  Read a CPU Save State register on the target processor.
+
+  This function abstracts the differences that whether the CPU Save State register is in the
+  IA32 CPU Save State Map or X64 CPU Save State Map.
+
+  This function supports reading a CPU Save State register in SMBase relocation handler.
+
+  @param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.
+  @param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
+  @param[in]  Width          The number of bytes to read from the CPU save state.
+  @param[out] Buffer         Upon return, this holds the CPU register value read from the save state.
+
+  @retval EFI_SUCCESS           The register was read from Save State.
+  @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
+  @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+ReadSaveStateRegisterByIndex (
+  IN UINTN  CpuIndex,
+  IN UINTN  RegisterIndex,
+  IN UINTN  Width,
+  OUT VOID  *Buffer
+  )
+{
+  AMD_SMRAM_SAVE_STATE_MAP  *CpuSaveState;
+
+  // UINT32                    SmmRevId;
+
+  if (RegisterIndex == 0) {
+    return EFI_NOT_FOUND;
+  }
+
+  CpuSaveState = gSmst->CpuSaveState[CpuIndex];
+  // SmmRevId = CpuSaveState->x86.SMMRevId;
+
+  if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
+    //
+    // If 32-bit mode width is zero, then the specified register can not be accessed
+    //
+    if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
+      return EFI_NOT_FOUND;
+    }
+
+    //
+    // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
+    //
+    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    //
+    // Write return buffer
+    //
+    ASSERT (CpuSaveState != NULL);
+    CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);
+  } else {
+    //
+    // If 64-bit mode width is zero, then the specified register can not be accessed
+    //
+    if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
+      return EFI_NOT_FOUND;
+    }
+
+    //
+    // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
+    //
+    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    //
+    // Write lower 32-bits of return buffer
+    //
+    CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN (4, Width));
+    if (Width >= 4) {
+      //
+      // Write upper 32-bits of return buffer
+      //
+      CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Read an SMM Save State register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
+  SMM Save Sate register.
+
+  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
+                        value must be between 0 and the NumberOfCpus field in
+                        the System Management System Table (SMST).
+  @param[in]  Register  The SMM Save State register to read.
+  @param[in]  Width     The number of bytes to read from the CPU save state.
+  @param[out] Buffer    Upon return, this holds the CPU register value read
+                        from the save state.
+
+  @retval EFI_SUCCESS           The register was read from Save State.
+  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support reading Register.
+
+**/
+EFI_STATUS
+EFIAPI
+InternalSmmCpuFeaturesReadSaveStateRegister (
+  IN  UINTN                        CpuIndex,
+  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,
+  IN  UINTN                        Width,
+  OUT VOID                         *Buffer
+  )
+{
+  UINT32                      SmmRevId;
+  EFI_SMM_SAVE_STATE_IO_INFO  *IoInfo;
+  AMD_SMRAM_SAVE_STATE_MAP    *CpuSaveState;
+  UINT8                       DataWidth;
+
+  // Read CPU State
+  CpuSaveState = (AMD_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
+
+  // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
+  if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
+    // Only byte access is supported for this register
+    if (Width != 1) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    *(UINT8 *)Buffer = mSmmSaveStateRegisterLma;
+
+    return EFI_SUCCESS;
+  }
+
+  // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
+
+  if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
+    //
+    // Get SMM Revision ID
+    //
+    ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId);
+
+    //
+    // See if the CPU supports the IOMisc register in the save state
+    //
+    if (SmmRevId < AMD_SMM_MIN_REV_ID_X64) {
+      return EFI_NOT_FOUND;
+    }
+
+    // Check if IO Restart Dword [IO Trap] is valid or not using bit 1.
+    if (!(CpuSaveState->x64.IO_DWord & 0x02u)) {
+      return EFI_NOT_FOUND;
+    }
+
+    // Zero the IoInfo structure that will be returned in Buffer
+    IoInfo = (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer;
+    ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO));
+
+    IoInfo->IoPort = (UINT16)(CpuSaveState->x64.IO_DWord >> 16u);
+
+    if (CpuSaveState->x64.IO_DWord & 0x10u) {
+      IoInfo->IoWidth = EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8;
+      DataWidth       = 0x01u;
+    } else if (CpuSaveState->x64.IO_DWord & 0x20u) {
+      IoInfo->IoWidth = EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16;
+      DataWidth       = 0x02u;
+    } else {
+      IoInfo->IoWidth = EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32;
+      DataWidth       = 0x04u;
+    }
+
+    if (CpuSaveState->x64.IO_DWord & 0x01u) {
+      IoInfo->IoType = EFI_SMM_SAVE_STATE_IO_TYPE_INPUT;
+    } else {
+      IoInfo->IoType = EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT;
+    }
+
+    if ((IoInfo->IoType == EFI_SMM_SAVE_STATE_IO_TYPE_INPUT) || (IoInfo->IoType == EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT)) {
+      SmmCpuFeaturesReadSaveStateRegister (CpuIndex, EFI_SMM_SAVE_STATE_REGISTER_RAX, DataWidth, &IoInfo->IoData);
+    }
+
+    return EFI_SUCCESS;
+  }
+
+  // Convert Register to a register lookup table index
+  return ReadSaveStateRegisterByIndex (CpuIndex, GetRegisterIndex (Register), Width, Buffer);
+}
+
+/**
+  Writes an SMM Save State register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
+  SMM Save Sate register.
+
+  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
+                       value must be between 0 and the NumberOfCpus field in
+                       the System Management System Table (SMST).
+  @param[in] Register  The SMM Save State register to write.
+  @param[in] Width     The number of bytes to write to the CPU save state.
+  @param[in] Buffer    Upon entry, this holds the new CPU register value.
+
+  @retval EFI_SUCCESS           The register was written to Save State.
+  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support writing Register.
+**/
+EFI_STATUS
+EFIAPI
+InternalSmmCpuFeaturesWriteSaveStateRegister (
+  IN UINTN                        CpuIndex,
+  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
+  IN UINTN                        Width,
+  IN CONST VOID                   *Buffer
+  )
+{
+  UINTN                     RegisterIndex;
+  AMD_SMRAM_SAVE_STATE_MAP  *CpuSaveState;
+
+  //
+  // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
+  //
+  if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
+    return EFI_SUCCESS;
+  }
+
+  //
+  // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
+  //
+  if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
+    return EFI_NOT_FOUND;
+  }
+
+  //
+  // Convert Register to a register lookup table index
+  //
+  RegisterIndex = GetRegisterIndex (Register);
+  if (RegisterIndex == 0) {
+    return EFI_NOT_FOUND;
+  }
+
+  CpuSaveState = gSmst->CpuSaveState[CpuIndex];
+
+  //
+  // Do not write non-writable SaveState, because it will cause exception.
+  //
+  if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // Check CPU mode
+  //
+  if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
+    //
+    // If 32-bit mode width is zero, then the specified register can not be accessed
+    //
+    if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
+      return EFI_NOT_FOUND;
+    }
+
+    //
+    // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
+    //
+    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    //
+    // Write SMM State register
+    //
+    ASSERT (CpuSaveState != NULL);
+    CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
+  } else {
+    //
+    // If 64-bit mode width is zero, then the specified register can not be accessed
+    //
+    if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
+      return EFI_NOT_FOUND;
+    }
+
+    //
+    // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
+    //
+    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    //
+    // Write lower 32-bits of SMM State register
+    //
+    CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
+    if (Width >= 4) {
+      //
+      // Write upper 32-bits of SMM State register
+      //
+      CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
-- 
2.25.1

[PATCH v1 5/5] UefiCpuPkg/AmdSmmCpuFeaturesLib: Handles S3 save state

[Abdul Lateef Attar]

From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182

Handles S3 save state restore condition.
Implements SmmCpuFeaturesCompleteSmmReadyToLock() to
sync all processor and update S3 resume entry point.

Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Garrett Kirkendall <garrett.kirkendall@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
---
 .../AmdSmmCpuFeaturesLib.inf                  |  1 +
 .../SmmCpuFeaturesLib/Amd/SmramSaveState.h    | 19 +++++++++++
 .../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c | 32 +++++++++++++++++++
 3 files changed, 52 insertions(+)

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
index 95eb31d16ead..7fd559e91ad8 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
@@ -27,6 +27,7 @@ [Sources]
 [Packages]
   MdePkg/MdePkg.dec
   UefiCpuPkg/UefiCpuPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
 
 [LibraryClasses]
   BaseLib
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
index 290ebdbc9227..474a5dbd9765 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
@@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/DebugLib.h>
 #include <Library/SmmServicesTableLib.h>
 #include <Register/Amd/SmramSaveStateMap.h>
+#include <Guid/AcpiS3Context.h>
 
 // EFER register LMA bit
 #define LMA  BIT10
@@ -106,4 +107,22 @@ InternalSmmCpuFeaturesWriteSaveStateRegister (
   IN CONST VOID                   *Buffer
   );
 
+/**
+  Initialize MP synchronization data.
+**/
+VOID
+EFIAPI
+InitializeMpSyncData (
+  VOID
+  );
+
+/**
+  Perform SMM MP sync Semaphores re-initialization in the S3 boot path.
+**/
+VOID
+EFIAPI
+SmmS3MpSemaphoreInit (
+  VOID
+  );
+
 #endif
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
index 10bed4116397..b855573d9401 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
@@ -14,6 +14,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 // The mode of the CPU at the time an SMI occurs
 extern UINT8  mSmmSaveStateRegisterLma;
 
+// SMM S3 resume state Ptr
+extern SMM_S3_RESUME_STATE  *mSmmS3ResumeState;
+
 /**
   Read an SMM Save State register on the target processor.  If this function
   returns EFI_UNSUPPORTED, then the caller is responsible for reading the
@@ -441,4 +444,33 @@ SmmCpuFeaturesCompleteSmmReadyToLock (
   VOID
   )
 {
+  if (mSmmS3ResumeState != NULL ) {
+    mSmmS3ResumeState->SmmS3ResumeEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)SmmS3MpSemaphoreInit;
+  }
+}
+
+/**
+  Perform SMM MP sync Semaphores re-initialization in the S3 boot path.
+**/
+VOID
+EFIAPI
+SmmS3MpSemaphoreInit (
+  VOID
+  )
+{
+  InitializeMpSyncData ();
+
+  DEBUG ((DEBUG_INFO, "SMM S3 Return CS                = %x\n", mSmmS3ResumeState->ReturnCs));
+  DEBUG ((DEBUG_INFO, "SMM S3 Return Entry Point       = %x\n", mSmmS3ResumeState->ReturnEntryPoint));
+  DEBUG ((DEBUG_INFO, "SMM S3 Return Context1          = %x\n", mSmmS3ResumeState->ReturnContext1));
+  DEBUG ((DEBUG_INFO, "SMM S3 Return Context2          = %x\n", mSmmS3ResumeState->ReturnContext2));
+  DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer     = %x\n", mSmmS3ResumeState->ReturnStackPointer));
+
+  AsmDisablePaging64 (
+    mSmmS3ResumeState->ReturnCs,
+    (UINT32)mSmmS3ResumeState->ReturnEntryPoint,
+    (UINT32)mSmmS3ResumeState->ReturnContext1,
+    (UINT32)mSmmS3ResumeState->ReturnContext2,
+    (UINT32)mSmmS3ResumeState->ReturnStackPointer
+    );
 }
-- 
2.25.1

Re: [PATCH v1 1/5] UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code

[Chang, Abner]

[AMD Official Use Only - General]

Reviewed-by: Abner Chang <abner.chang@amd.com>

> -----Original Message-----
> From: Abdul Lateef Attar <abdattar@amd.com>
> Sent: Tuesday, December 6, 2022 9:23 PM
> To: devel@edk2.groups.io
> Cc: Attar, AbdulLateef (Abdul Lateef) <AbdulLateef.Attar@amd.com>; Chang,
> Abner <Abner.Chang@amd.com>; Kirkendall, Garrett
> <Garrett.Kirkendall@amd.com>; Grimes, Paul <Paul.Grimes@amd.com>; Eric
> Dong <eric.dong@intel.com>; Ray Ni <ray.ni@intel.com>; Rahul Kumar
> <rahul1.kumar@intel.com>
> Subject: [PATCH v1 1/5] UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-
> dependent code
> 
> From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182
> 
> moves Intel-specific code to the arch-dependent file.
> Other processor families might have different implementation of these
> functions.
> Hence, moving out of the common file.
> 
> Cc: Abner Chang <abner.chang@amd.com>
> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com>
> Cc: Paul Grimes <paul.grimes@amd.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
> ---
>  .../IntelSmmCpuFeaturesLib.c                  | 140 ++++++++++++++++++
>  .../SmmCpuFeaturesLibCommon.c                 | 140 ------------------
>  2 files changed, 140 insertions(+), 140 deletions(-)
> 
> diff --git
> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c
> index d5eaaa7a991e..994267f393b3 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c
> @@ -400,3 +400,143 @@ SmmCpuFeaturesSetSmmRegister (
>      AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL,
> Value);   } }++/**+  This function updates the SMRAM save state on the
> currently executing CPU+  to resume execution at a specific address after an
> RSM instruction.  This+  function must evaluate the SMRAM save state to
> determine the execution mode+  the RSM instruction resumes and update
> the resume execution address with+  either NewInstructionPointer32 or
> NewInstructionPoint.  The auto HALT restart+  flag in the SMRAM save state
> must always be cleared.  This function returns+  the value of the instruction
> pointer from the SMRAM save state that was+  replaced.  If this function
> returns 0, then the SMRAM save state was not+  modified.++  This function is
> called during the very first SMI on each CPU after+
> SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution
> mode+  to signal that the SMBASE of each CPU has been updated before the
> default+  SMBASE address is used for the first SMI to the next CPU.++
> @param[in] CpuIndex                 The index of the CPU to hook.  The value+
> must be between 0 and the NumberOfCpus+                                      field in the
> System Management System Table+                                      (SMST).+  @param[in]
> CpuState                 Pointer to SMRAM Save State Map for the+
> currently executing CPU.+  @param[in] NewInstructionPointer32  Instruction
> pointer to use if resuming to+                                      32-bit execution mode from
> 64-bit SMM.+  @param[in] NewInstructionPointer    Instruction pointer to
> use if resuming to+                                      same execution mode as SMM.++
> @retval 0    This function did modify the SMRAM save state.+  @retval > 0
> The original instruction pointer value from the SMRAM save state+
> before it was
> replaced.+**/+UINT64+EFIAPI+SmmCpuFeaturesHookReturnFromSmm (+
> IN UINTN                 CpuIndex,+  IN SMRAM_SAVE_STATE_MAP  *CpuState,+
> IN UINT64                NewInstructionPointer32,+  IN UINT64
> NewInstructionPointer+  )+{+  return 0;+}++/**+  Read an SMM Save State
> register on the target processor.  If this function+  returns
> EFI_UNSUPPORTED, then the caller is responsible for reading the+  SMM
> Save Sate register.++  @param[in]  CpuIndex  The index of the CPU to read
> the SMM Save State.  The+                        value must be between 0 and the
> NumberOfCpus field in+                        the System Management System Table
> (SMST).+  @param[in]  Register  The SMM Save State register to read.+
> @param[in]  Width     The number of bytes to read from the CPU save state.+
> @param[out] Buffer    Upon return, this holds the CPU register value read+
> from the save state.++  @retval EFI_SUCCESS           The register was read
> from Save State.+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.+
> @retval EFI_UNSUPPORTED       This function does not support reading
> Register.++**/+EFI_STATUS+EFIAPI+SmmCpuFeaturesReadSaveStateRegist
> er (+  IN  UINTN                        CpuIndex,+  IN
> EFI_SMM_SAVE_STATE_REGISTER  Register,+  IN  UINTN                        Width,+
> OUT VOID                         *Buffer+  )+{+  return EFI_UNSUPPORTED;+}++/**+
> Writes an SMM Save State register on the target processor.  If this function+
> returns EFI_UNSUPPORTED, then the caller is responsible for writing the+
> SMM Save Sate register.++  @param[in] CpuIndex  The index of the CPU to
> write the SMM Save State.  The+                       value must be between 0 and
> the NumberOfCpus field in+                       the System Management System
> Table (SMST).+  @param[in] Register  The SMM Save State register to write.+
> @param[in] Width     The number of bytes to write to the CPU save state.+
> @param[in] Buffer    Upon entry, this holds the new CPU register value.++
> @retval EFI_SUCCESS           The register was written to Save State.+  @retval
> EFI_INVALID_PARAMETER  Buffer is NULL.+  @retval EFI_UNSUPPORTED
> This function does not support writing
> Register.+**/+EFI_STATUS+EFIAPI+SmmCpuFeaturesWriteSaveStateRegiste
> r (+  IN UINTN                        CpuIndex,+  IN EFI_SMM_SAVE_STATE_REGISTER
> Register,+  IN UINTN                        Width,+  IN CONST VOID
> *Buffer+  )+{+  return EFI_UNSUPPORTED;+}++/**+  Check to see if an SMM
> register is supported by a specified CPU.++  @param[in] CpuIndex  The index
> of the CPU to check for SMM register support.+                       The value must
> be between 0 and the NumberOfCpus field+                       in the System
> Management System Table (SMST).+  @param[in] RegName   Identifies the
> SMM register to check for support.++  @retval TRUE   The SMM register
> specified by RegName is supported by the CPU+                 specified by
> CpuIndex.+  @retval FALSE  The SMM register specified by RegName is not
> supported by the+                 CPU specified by
> CpuIndex.+**/+BOOLEAN+EFIAPI+SmmCpuFeaturesIsSmmRegisterSupport
> ed (+  IN UINTN         CpuIndex,+  IN SMM_REG_NAME  RegName+  )+{+  if
> (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName ==
> SmmRegFeatureControl)) {+    return TRUE;+  }++  return FALSE;+}++/**+
> This function is hook point called after the
> gEfiSmmReadyToLockProtocolGuid+  notification is completely
> processed.+**/+VOID+EFIAPI+SmmCpuFeaturesCompleteSmmReadyToLoc
> k (+  VOID+  )+{+}diff --git
> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
> index 7777e52740eb..2f8841bbbf77 100644
> ---
> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
> +++
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
> @@ -17,49 +17,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>   #include "CpuFeaturesLib.h" -/**-  This function updates the SMRAM save
> state on the currently executing CPU-  to resume execution at a specific
> address after an RSM instruction.  This-  function must evaluate the SMRAM
> save state to determine the execution mode-  the RSM instruction resumes
> and update the resume execution address with-  either
> NewInstructionPointer32 or NewInstructionPoint.  The auto HALT restart-
> flag in the SMRAM save state must always be cleared.  This function returns-
> the value of the instruction pointer from the SMRAM save state that was-
> replaced.  If this function returns 0, then the SMRAM save state was not-
> modified.--  This function is called during the very first SMI on each CPU
> after-  SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution
> mode-  to signal that the SMBASE of each CPU has been updated before the
> default-  SMBASE address is used for the first SMI to the next CPU.--
> @param[in] CpuIndex                 The index of the CPU to hook.  The value-
> must be between 0 and the NumberOfCpus-                                      field in the
> System Management System Table-                                      (SMST).-  @param[in]
> CpuState                 Pointer to SMRAM Save State Map for the-
> currently executing CPU.-  @param[in] NewInstructionPointer32  Instruction
> pointer to use if resuming to-                                      32-bit execution mode from
> 64-bit SMM.-  @param[in] NewInstructionPointer    Instruction pointer to use
> if resuming to-                                      same execution mode as SMM.--  @retval 0
> This function did modify the SMRAM save state.-  @retval > 0  The original
> instruction pointer value from the SMRAM save state-               before it was
> replaced.-**/-UINT64-EFIAPI-SmmCpuFeaturesHookReturnFromSmm (-  IN
> UINTN                 CpuIndex,-  IN SMRAM_SAVE_STATE_MAP  *CpuState,-  IN
> UINT64                NewInstructionPointer32,-  IN UINT64
> NewInstructionPointer-  )-{-  return 0;-}- /**   Hook point in normal execution
> mode that allows the one CPU that was elected   as monarch during System
> Management Mode initialization to perform additional@@ -90,103 +47,6 @@
> SmmCpuFeaturesRendezvousExit (
>  { } -/**-  Check to see if an SMM register is supported by a specified CPU.--
> @param[in] CpuIndex  The index of the CPU to check for SMM register
> support.-                       The value must be between 0 and the NumberOfCpus
> field-                       in the System Management System Table (SMST).-
> @param[in] RegName   Identifies the SMM register to check for support.--
> @retval TRUE   The SMM register specified by RegName is supported by the
> CPU-                 specified by CpuIndex.-  @retval FALSE  The SMM register
> specified by RegName is not supported by the-                 CPU specified by
> CpuIndex.-**/-BOOLEAN-EFIAPI-SmmCpuFeaturesIsSmmRegisterSupported
> (-  IN UINTN         CpuIndex,-  IN SMM_REG_NAME  RegName-  )-{-  if
> (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName ==
> SmmRegFeatureControl)) {-    return TRUE;-  }--  return FALSE;-}--/**-  Read
> an SMM Save State register on the target processor.  If this function-  returns
> EFI_UNSUPPORTED, then the caller is responsible for reading the-  SMM
> Save Sate register.--  @param[in]  CpuIndex  The index of the CPU to read
> the SMM Save State.  The-                        value must be between 0 and the
> NumberOfCpus field in-                        the System Management System Table
> (SMST).-  @param[in]  Register  The SMM Save State register to read.-
> @param[in]  Width     The number of bytes to read from the CPU save state.-
> @param[out] Buffer    Upon return, this holds the CPU register value read-
> from the save state.--  @retval EFI_SUCCESS           The register was read from
> Save State.-  @retval EFI_INVALID_PARAMETER  Buffer is NULL.-  @retval
> EFI_UNSUPPORTED       This function does not support reading Register.--**/-
> EFI_STATUS-EFIAPI-SmmCpuFeaturesReadSaveStateRegister (-  IN  UINTN
> CpuIndex,-  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,-  IN  UINTN
> Width,-  OUT VOID                         *Buffer-  )-{-  return EFI_UNSUPPORTED;-}--
> /**-  Writes an SMM Save State register on the target processor.  If this
> function-  returns EFI_UNSUPPORTED, then the caller is responsible for
> writing the-  SMM Save Sate register.--  @param[in] CpuIndex  The index of
> the CPU to write the SMM Save State.  The-                       value must be
> between 0 and the NumberOfCpus field in-                       the System
> Management System Table (SMST).-  @param[in] Register  The SMM Save
> State register to write.-  @param[in] Width     The number of bytes to write
> to the CPU save state.-  @param[in] Buffer    Upon entry, this holds the new
> CPU register value.--  @retval EFI_SUCCESS           The register was written to
> Save State.-  @retval EFI_INVALID_PARAMETER  Buffer is NULL.-  @retval
> EFI_UNSUPPORTED       This function does not support writing Register.-**/-
> EFI_STATUS-EFIAPI-SmmCpuFeaturesWriteSaveStateRegister (-  IN UINTN
> CpuIndex,-  IN EFI_SMM_SAVE_STATE_REGISTER  Register,-  IN UINTN
> Width,-  IN CONST VOID                   *Buffer-  )-{-  return EFI_UNSUPPORTED;-}-
> -/**-  This function is hook point called after the
> gEfiSmmReadyToLockProtocolGuid-  notification is completely processed.-
> **/-VOID-EFIAPI-SmmCpuFeaturesCompleteSmmReadyToLock (-  VOID-  )-{-
> }- /**   This API provides a method for a CPU to allocate a specific region for
> storing page tables. --
> 2.25.1

Re: [edk2-devel] [PATCH v1 2/5] MdePkg: Adds AMD SMRAM save state map

[Chang, Abner]

[-- Attachment #1: Type: text/plain, Size: 7838 bytes --]

On Tue, Dec 6, 2022 at 09:23 PM, Abdul Lateef Attar wrote:

> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182
> 
> Adds an SMM SMRAM save-state map for AMD processors.
> SMRAM save state maps for the AMD processor family are now supported.
> 
> Save state map structure is added based on
> AMD64 Architecture Programmer's Manual, Volume 2, Section 10.2.
> 
> The AMD legacy save state map for 32-bit architecture is defined.
> The AMD64 save state map for 64-bit architecture is defined.
> 
> Also added Amd/SmramSaveStateMap.h to IgnoreFiles of EccCheck,
> because structures defined in this file are derived from
> Intel/SmramSaveStateMap.h.
> 
> Cc: Paul Grimes <paul.grimes@amd.com>
> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com>
> Cc: Abner Chang <abner.chang@amd.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> 
> Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
> ---
> .../Include/Register/Amd/SmramSaveStateMap.h | 194 ++++++++++++++++++
> MdePkg/MdePkg.ci.yaml | 3 +-
> 2 files changed, 196 insertions(+), 1 deletion(-)
> create mode 100644 MdePkg/Include/Register/Amd/SmramSaveStateMap.h
> 
> diff --git a/MdePkg/Include/Register/Amd/SmramSaveStateMap.h
> b/MdePkg/Include/Register/Amd/SmramSaveStateMap.h
> new file mode 100644
> index 000000000000..6da1538608cf
> --- /dev/null
> +++ b/MdePkg/Include/Register/Amd/SmramSaveStateMap.h
> @@ -0,0 +1,194 @@
> +/** @file
> + AMD SMRAM Save State Map Definitions.
> +
> + SMRAM Save State Map definitions based on contents of the
> + AMD64 Architecture Programmer Manual:
> + Volume 2, System Programming, Section 10.2 SMM Resources

Hi Abdul,
Could you please confirm there are no extra spaces at the beginning of  "AMD64 Architecture Programmer Manual:" and "Volume 2, System Programming, Section 10.2 SMM Resources" in your source file? I do see the extra spaces in the posted message on group.io, but it disappears when I quoted the post when replying.

Thanks
Abner

> 
> +
> + Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
> + Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved
> .<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef AMD_SMRAM_SAVE_STATE_MAP_H_
> +#define AMD_SMRAM_SAVE_STATE_MAP_H_
> +
> +///
> +/// Default SMBASE address
> +///
> +#define SMM_DEFAULT_SMBASE 0x30000
> +
> +///
> +/// Offset of SMM handler from SMBASE
> +///
> +#define SMM_HANDLER_OFFSET 0x8000
> +
> +// SMM-Revision Identifier for AMD64 Architecture.
> +#define AMD_SMM_MIN_REV_ID_X64 0x30064
> +
> +#pragma pack (1)
> +
> +///
> +/// 32-bit SMRAM Save State Map
> +///
> +typedef struct {
> + // Padded an extra 0x200 bytes to match Intel/EDK2
> + UINT8 Reserved[0x200]; // fc00h
> + // AMD Save State area starts @ 0xfe00
> + UINT8 Reserved1[0xf8]; // fe00h
> + UINT32 SMBASE; // fef8h
> + UINT32 SMMRevId; // fefch
> + UINT16 IORestart; // ff00h
> + UINT16 AutoHALTRestart; // ff02h
> + UINT8 Reserved2[0x84]; // ff04h
> + UINT32 GDTBase; // ff88h
> + UINT64 Reserved3; // ff8ch
> + UINT32 IDTBase; // ff94h
> + UINT8 Reserved4[0x10]; // ff98h
> + UINT32 _ES; // ffa8h
> + UINT32 _CS; // ffach
> + UINT32 _SS; // ffb0h
> + UINT32 _DS; // ffb4h
> + UINT32 _FS; // ffb8h
> + UINT32 _GS; // ffbch
> + UINT32 LDTBase; // ffc0h
> + UINT32 _TR; // ffc4h
> + UINT32 _DR7; // ffc8h
> + UINT32 _DR6; // ffcch
> + UINT32 _EAX; // ffd0h
> + UINT32 _ECX; // ffd4h
> + UINT32 _EDX; // ffd8h
> + UINT32 _EBX; // ffdch
> + UINT32 _ESP; // ffe0h
> + UINT32 _EBP; // ffe4h
> + UINT32 _ESI; // ffe8h
> + UINT32 _EDI; // ffech
> + UINT32 _EIP; // fff0h
> + UINT32 _EFLAGS; // fff4h
> + UINT32 _CR3; // fff8h
> + UINT32 _CR0; // fffch
> +} AMD_SMRAM_SAVE_STATE_MAP32;
> +
> +///
> +/// 64-bit SMRAM Save State Map
> +///
> +typedef struct {
> + // Padded an extra 0x200 bytes to match Intel/EDK2
> + UINT8 Reserved[0x200]; // fc00h
> + // AMD Save State area starts @ 0xfe00
> + UINT16 _ES; // fe00h
> + UINT16 _ESAttributes; // fe02h
> + UINT32 _ESLimit; // fe04h
> + UINT64 _ESBase; // fe08h
> +
> + UINT16 _CS; // fe10h
> + UINT16 _CSAttributes; // fe12h
> + UINT32 _CSLimit; // fe14h
> + UINT64 _CSBase; // fe18h
> +
> + UINT16 _SS; // fe20h
> + UINT16 _SSAttributes; // fe22h
> + UINT32 _SSLimit; // fe24h
> + UINT64 _SSBase; // fe28h
> +
> + UINT16 _DS; // fe30h
> + UINT16 _DSAttributes; // fe32h
> + UINT32 _DSLimit; // fe34h
> + UINT64 _DSBase; // fe38h
> +
> + UINT16 _FS; // fe40h
> + UINT16 _FSAttributes; // fe42h
> + UINT32 _FSLimit; // fe44h
> + UINT64 _FSBase; // fe48h
> +
> + UINT16 _GS; // fe50h
> + UINT16 _GSAttributes; // fe52h
> + UINT32 _GSLimit; // fe54h
> + UINT64 _GSBase; // fe58h
> +
> + UINT32 _GDTRReserved1; // fe60h
> + UINT16 _GDTRLimit; // fe64h
> + UINT16 _GDTRReserved2; // fe66h
> + // UINT64 _GDTRBase; // fe68h
> + UINT32 _GDTRBaseLoDword;
> + UINT32 _GDTRBaseHiDword;
> +
> + UINT16 _LDTR; // fe70h
> + UINT16 _LDTRAttributes; // fe72h
> + UINT32 _LDTRLimit; // fe74h
> + // UINT64 _LDTRBase; // fe78h
> + UINT32 _LDTRBaseLoDword;
> + UINT32 _LDTRBaseHiDword;
> +
> + UINT32 _IDTRReserved1; // fe80h
> + UINT16 _IDTRLimit; // fe84h
> + UINT16 _IDTRReserved2; // fe86h
> + // UINT64 _IDTRBase; // fe88h
> + UINT32 _IDTRBaseLoDword;
> + UINT32 _IDTRBaseHiDword;
> +
> + UINT16 _TR; // fe90h
> + UINT16 _TRAttributes; // fe92h
> + UINT32 _TRLimit; // fe94h
> + UINT64 _TRBase; // fe98h
> +
> + UINT64 IO_RIP; // fea0h
> + UINT64 IO_RCX; // fea8h
> + UINT64 IO_RSI; // feb0h
> + UINT64 IO_RDI; // feb8h
> + UINT32 IO_DWord; // fec0h
> + UINT8 Reserved1[0x04]; // fec4h
> + UINT8 IORestart; // fec8h
> + UINT8 AutoHALTRestart; // fec9h
> + UINT8 Reserved2[0x06]; // fecah
> + UINT64 EFER; // fed0h
> + UINT64 SVM_Guest; // fed8h
> + UINT64 SVM_GuestVMCB; // fee0h
> + UINT64 SVM_GuestVIntr; // fee8h
> + UINT8 Reserved3[0x0c]; // fef0h
> + UINT32 SMMRevId; // fefch
> + UINT32 SMBASE; // ff00h
> + UINT8 Reserved4[0x14]; // ff04h
> + UINT64 SSP; // ff18h
> + UINT64 SVM_GuestPAT; // ff20h
> + UINT64 SVM_HostEFER; // ff28h
> + UINT64 SVM_HostCR4; // ff30h
> + UINT64 SVM_HostCR3; // ff38h
> + UINT64 SVM_HostCR0; // ff40h
> + UINT64 _CR4; // ff48h
> + UINT64 _CR3; // ff50h
> + UINT64 _CR0; // ff58h
> + UINT64 _DR7; // ff60h
> + UINT64 _DR6; // ff68h
> + UINT64 _RFLAGS; // ff70h
> + UINT64 _RIP; // ff78h
> + UINT64 _R15; // ff80h
> + UINT64 _R14; // ff88h
> + UINT64 _R13; // ff90h
> + UINT64 _R12; // ff98h
> + UINT64 _R11; // ffa0h
> + UINT64 _R10; // ffa8h
> + UINT64 _R9; // ffb0h
> + UINT64 _R8; // ffb8h
> + UINT64 _RDI; // ffc0h
> + UINT64 _RSI; // ffc8h
> + UINT64 _RBP; // ffd0h
> + UINT64 _RSP; // ffd8h
> + UINT64 _RBX; // ffe0h
> + UINT64 _RDX; // ffe8h
> + UINT64 _RCX; // fff0h
> + UINT64 _RAX; // fff8h
> +} AMD_SMRAM_SAVE_STATE_MAP64;
> +
> +///
> +/// Union of 32-bit and 64-bit SMRAM Save State Maps
> +///
> +typedef union {
> + AMD_SMRAM_SAVE_STATE_MAP32 x86;
> + AMD_SMRAM_SAVE_STATE_MAP64 x64;
> +} AMD_SMRAM_SAVE_STATE_MAP;
> +
> +#pragma pack ()
> +
> +#endif
> diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml
> index 19bc0138cb76..86c9c502d799 100644
> --- a/MdePkg/MdePkg.ci.yaml
> +++ b/MdePkg/MdePkg.ci.yaml
> @@ -65,7 +65,8 @@
> "Include/Library/PcdLib.h",
> "Include/Library/SafeIntLib.h",
> "Include/Protocol/DebugSupport.h",
> - "Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c"
> + "Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c",
> + "Include/Register/Amd/SmramSaveStateMap.h"
> ]
> },
> ## options defined ci/Plugin/CompilerPlugin
> --
> 2.25.1

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Re: [edk2-devel] [PATCH v1 3/5] UefiCpuPkg: Initial implementation of AMD's SmmCpuFeaturesLib

[Chang, Abner]

[-- Attachment #1: Type: text/plain, Size: 16862 bytes --]

Hi Abdul,
Because SmmCpuFeatureLib is expected to only be used by X86 vendors, we can just have SmmCpuFeaturesLib under the root of module directory and rename it to AmdSmmCpuFeaturesLib.c
Thanks
Abner

On Tue, Dec 6, 2022 at 09:23 PM, Abdul Lateef Attar wrote:

> 
> From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182
> 
> Adds initial defination for AMD's SmmCpuFeaturesLib
> library implementation.
> All function's body either empty or just returns
> value. Its initial skeleton of library implementation.
> 
> Cc: Paul Grimes <paul.grimes@amd.com>
> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com>
> Cc: Abner Chang <abner.chang@amd.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
> ---
> UefiCpuPkg/UefiCpuPkg.dsc | 9 +
> .../AmdSmmCpuFeaturesLib.inf | 37 ++
> .../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c | 357 ++++++++++++++++++
> 3 files changed, 403 insertions(+)
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
> 
> diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
> index 67b0ce46e455..8aeaf992af9b 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dsc
> +++ b/UefiCpuPkg/UefiCpuPkg.dsc
> @@ -2,6 +2,7 @@
> # UefiCpuPkg Package
> #
> # Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>
> +# Copyright (C) 2022 Advanced Micro Devices, Inc. All rights
> reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -160,6 +161,7 @@ [Components.IA32, Components.X64]
> UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.inf
> UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf
> UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf
> 
> + UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf
> @@ -176,6 +178,13 @@ [Components.IA32, Components.X64]
> <LibraryClasses>
> SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> 
> }
> + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {
> + <Defines>
> + FILE_GUID = B7242C74-BD21-49EE-84B4-07162E8C080D
> + <LibraryClasses>
> +
> SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> 
> +
> SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf
> 
> + }
> UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
> UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
> UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> new file mode 100644
> index 000000000000..08ac0262022f
> --- /dev/null
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> @@ -0,0 +1,37 @@
> +## @file
> +# The CPU specific programming for PiSmmCpuDxeSmm module.
> +#
> +# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
> +# Copyright (C) 2022 Advanced Micro Devices, Inc. All rights
> reserved.<BR>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = SmmCpuFeaturesLib
> + MODULE_UNI_FILE = SmmCpuFeaturesLib.uni
> + FILE_GUID = 5849E964-78EC-428E-8CBD-848A7E359134
> + MODULE_TYPE = DXE_SMM_DRIVER
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SmmCpuFeaturesLib
> + CONSTRUCTOR = SmmCpuFeaturesLibConstructor
> +
> +[Sources]
> + SmmCpuFeaturesLib.c
> + SmmCpuFeaturesLibCommon.c
> + Amd/SmmCpuFeaturesLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + UefiCpuPkg/UefiCpuPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + PcdLib
> + MemoryAllocationLib
> + DebugLib
> +
> +[FeaturePcd]
> + gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable ## CONSUMES
> + gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable ## CONSUMES
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
> new file mode 100644
> index 000000000000..dc3fed0302d2
> --- /dev/null
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
> @@ -0,0 +1,357 @@
> +/** @file
> +Implementation specific to the SmmCpuFeatureLib library instance
> +for AMD based platforms.
> +
> +Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) Microsoft Corporation.<BR>
> +Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Library/SmmCpuFeaturesLib.h>
> +#include <Uefi/UefiBaseType.h>
> +
> +/**
> + Read an SMM Save State register on the target processor. If this
> function
> + returns EFI_UNSUPPORTED, then the caller is responsible for reading the
> + SMM Save Sate register.
> +
> + @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
> 
> + value must be between 0 and the NumberOfCpus field in
> + the System Management System Table (SMST).
> + @param[in] Register The SMM Save State register to read.
> + @param[in] Width The number of bytes to read from the CPU save state.
> + @param[out] Buffer Upon return, this holds the CPU register value read
> + from the save state.
> +
> + @retval EFI_SUCCESS The register was read from Save State.
> + @retval EFI_INVALID_PARAMTER Buffer is NULL.
> + @retval EFI_UNSUPPORTED This function does not support reading Register.
> 
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SmmCpuFeaturesReadSaveStateRegister (
> + IN UINTN CpuIndex,
> + IN EFI_SMM_SAVE_STATE_REGISTER Register,
> + IN UINTN Width,
> + OUT VOID *Buffer
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Writes an SMM Save State register on the target processor. If this
> function
> + returns EFI_UNSUPPORTED, then the caller is responsible for writing the
> + SMM Save Sate register.
> +
> + @param[in] CpuIndex The index of the CPU to write the SMM Save State.
> The
> + value must be between 0 and the NumberOfCpus field in
> + the System Management System Table (SMST).
> + @param[in] Register The SMM Save State register to write.
> + @param[in] Width The number of bytes to write to the CPU save state.
> + @param[in] Buffer Upon entry, this holds the new CPU register value.
> +
> + @retval EFI_SUCCESS The register was written to Save State.
> + @retval EFI_INVALID_PARAMTER Buffer is NULL.
> + @retval EFI_UNSUPPORTED This function does not support writing Register.
> 
> +**/
> +EFI_STATUS
> +EFIAPI
> +SmmCpuFeaturesWriteSaveStateRegister (
> + IN UINTN CpuIndex,
> + IN EFI_SMM_SAVE_STATE_REGISTER Register,
> + IN UINTN Width,
> + IN CONST VOID *Buffer
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Performs library initialization.
> +
> + This initialization function contains common functionality shared betwen
> all
> + library instance constructors.
> +
> +**/
> +VOID
> +CpuFeaturesLibInitialization (
> + VOID
> + )
> +{
> +}
> +
> +/**
> + Called during the very first SMI into System Management Mode to
> initialize
> + CPU features, including SMBASE, for the currently executing CPU. Since
> this
> + is the first SMI, the SMRAM Save State Map is at the default address of
> + AMD_SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently
> executing
> + CPU is specified by CpuIndex and CpuIndex can be used to access
> information
> + about the currently executing CPU in the ProcessorInfo array and the
> + HotPlugCpuData data structure.
> +
> + @param[in] CpuIndex The index of the CPU to initialize. The value
> + must be between 0 and the NumberOfCpus field in
> + the System Management System Table (SMST).
> + @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
> + was elected as monarch during System Management
> + Mode initialization.
> + FALSE if the CpuIndex is not the index of the CPU
> + that was elected as monarch during System
> + Management Mode initialization.
> + @param[in] ProcessorInfo Pointer to an array of
> EFI_PROCESSOR_INFORMATION
> + structures. ProcessorInfo[CpuIndex] contains the
> + information for the currently executing CPU.
> + @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure
> that
> + contains the ApidId and SmBase arrays.
> +**/
> +VOID
> +EFIAPI
> +SmmCpuFeaturesInitializeProcessor (
> + IN UINTN CpuIndex,
> + IN BOOLEAN IsMonarch,
> + IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,
> + IN CPU_HOT_PLUG_DATA *CpuHotPlugData
> + )
> +{
> +}
> +
> +/**
> + This function updates the SMRAM save state on the currently executing
> CPU
> + to resume execution at a specific address after an RSM instruction. This
> 
> + function must evaluate the SMRAM save state to determine the execution
> mode
> + the RSM instruction resumes and update the resume execution address with
> 
> + either NewInstructionPointer32 or NewInstructionPoint. The auto HALT
> restart
> + flag in the SMRAM save state must always be cleared. This function
> returns
> + the value of the instruction pointer from the SMRAM save state that was
> + replaced. If this function returns 0, then the SMRAM save state was not
> + modified.
> +
> + This function is called during the very first SMI on each CPU after
> + SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution
> mode
> + to signal that the SMBASE of each CPU has been updated before the
> default
> + SMBASE address is used for the first SMI to the next CPU.
> +
> + @param[in] CpuIndex The index of the CPU to hook. The value
> + must be between 0 and the NumberOfCpus
> + field in the System Management System Table
> + (SMST).
> + @param[in] CpuState Pointer to SMRAM Save State Map for the
> + currently executing CPU.
> + @param[in] NewInstructionPointer32 Instruction pointer to use if
> resuming to
> + 32-bit execution mode from 64-bit SMM.
> + @param[in] NewInstructionPointer Instruction pointer to use if resuming
> to
> + same execution mode as SMM.
> +
> + @retval 0 This function did modify the SMRAM save state.
> + @retval > 0 The original instruction pointer value from the SMRAM save
> state
> + before it was replaced.
> +**/
> +UINT64
> +EFIAPI
> +SmmCpuFeaturesHookReturnFromSmm (
> + IN UINTN CpuIndex,
> + IN SMRAM_SAVE_STATE_MAP *CpuState,
> + IN UINT64 NewInstructionPointer32,
> + IN UINT64 NewInstructionPointer
> + )
> +{
> + return 0;
> +}
> +
> +/**
> + Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
> + returned, then a custom SMI handler is not provided by this library,
> + and the default SMI handler must be used.
> +
> + @retval 0 Use the default SMI handler.
> + @retval > 0 Use the SMI handler installed by
> SmmCpuFeaturesInstallSmiHandler()
> + The caller is required to allocate enough SMRAM for each CPU to
> + support the size of the custom SMI handler.
> +**/
> +UINTN
> +EFIAPI
> +SmmCpuFeaturesGetSmiHandlerSize (
> + VOID
> + )
> +{
> + return 0;
> +}
> +
> +/**
> + Install a custom SMI handler for the CPU specified by CpuIndex. This
> function
> + is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is
> greater
> + than zero and is called by the CPU that was elected as monarch during
> System
> + Management Mode initialization.
> +
> + @param[in] CpuIndex The index of the CPU to install the custom SMI
> handler.
> + The value must be between 0 and the NumberOfCpus field
> + in the System Management System Table (SMST).
> + @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
> + @param[in] SmiStack The stack to use when an SMI is processed by the
> + the CPU specified by CpuIndex.
> + @param[in] StackSize The size, in bytes, if the stack used when an SMI
> is
> + processed by the CPU specified by CpuIndex.
> + @param[in] GdtBase The base address of the GDT to use when an SMI is
> + processed by the CPU specified by CpuIndex.
> + @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
> + processed by the CPU specified by CpuIndex.
> + @param[in] IdtBase The base address of the IDT to use when an SMI is
> + processed by the CPU specified by CpuIndex.
> + @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
> + processed by the CPU specified by CpuIndex.
> + @param[in] Cr3 The base address of the page tables to use when an SMI
> + is processed by the CPU specified by CpuIndex.
> +**/
> +VOID
> +EFIAPI
> +SmmCpuFeaturesInstallSmiHandler (
> + IN UINTN CpuIndex,
> + IN UINT32 SmBase,
> + IN VOID *SmiStack,
> + IN UINTN StackSize,
> + IN UINTN GdtBase,
> + IN UINTN GdtSize,
> + IN UINTN IdtBase,
> + IN UINTN IdtSize,
> + IN UINT32 Cr3
> + )
> +{
> +}
> +
> +/**
> + Determines if MTRR registers must be configured to set SMRAM
> cache-ability
> + when executing in System Management Mode.
> +
> + @retval TRUE MTRR registers must be configured to set SMRAM
> cache-ability.
> + @retval FALSE MTRR registers do not need to be configured to set SMRAM
> + cache-ability.
> +**/
> +BOOLEAN
> +EFIAPI
> +SmmCpuFeaturesNeedConfigureMtrrs (
> + VOID
> + )
> +{
> + return FALSE;
> +}
> +
> +/**
> + Disable SMRR register if SMRR is supported and
> SmmCpuFeaturesNeedConfigureMtrrs()
> + returns TRUE.
> +**/
> +VOID
> +EFIAPI
> +SmmCpuFeaturesDisableSmrr (
> + VOID
> + )
> +{
> +}
> +
> +/**
> + Enable SMRR register if SMRR is supported and
> SmmCpuFeaturesNeedConfigureMtrrs()
> + returns TRUE.
> +**/
> +VOID
> +EFIAPI
> +SmmCpuFeaturesReenableSmrr (
> + VOID
> + )
> +{
> +}
> +
> +/**
> + Processor specific hook point each time a CPU enters System Management
> Mode.
> +
> + @param[in] CpuIndex The index of the CPU that has entered SMM. The value
> 
> + must be between 0 and the NumberOfCpus field in the
> + System Management System Table (SMST).
> +**/
> +VOID
> +EFIAPI
> +SmmCpuFeaturesRendezvousEntry (
> + IN UINTN CpuIndex
> + )
> +{
> +}
> +
> +/**
> + Returns the current value of the SMM register for the specified CPU.
> + If the SMM register is not supported, then 0 is returned.
> +
> + @param[in] CpuIndex The index of the CPU to read the SMM register. The
> + value must be between 0 and the NumberOfCpus field in
> + the System Management System Table (SMST).
> + @param[in] RegName Identifies the SMM register to read.
> +
> + @return The value of the SMM register specified by RegName from the CPU
> + specified by CpuIndex.
> +**/
> +UINT64
> +EFIAPI
> +SmmCpuFeaturesGetSmmRegister (
> + IN UINTN CpuIndex,
> + IN SMM_REG_NAME RegName
> + )
> +{
> + return 0;
> +}
> +
> +/**
> + Sets the value of an SMM register on a specified CPU.
> + If the SMM register is not supported, then no action is performed.
> +
> + @param[in] CpuIndex The index of the CPU to write the SMM register. The
> + value must be between 0 and the NumberOfCpus field in
> + the System Management System Table (SMST).
> + @param[in] RegName Identifies the SMM register to write.
> + registers are read-only.
> + @param[in] Value The value to write to the SMM register.
> +**/
> +VOID
> +EFIAPI
> +SmmCpuFeaturesSetSmmRegister (
> + IN UINTN CpuIndex,
> + IN SMM_REG_NAME RegName,
> + IN UINT64 Value
> + )
> +{
> +}
> +
> +/**
> + Check to see if an SMM register is supported by a specified CPU.
> +
> + @param[in] CpuIndex The index of the CPU to check for SMM register
> support.
> + The value must be between 0 and the NumberOfCpus field
> + in the System Management System Table (SMST).
> + @param[in] RegName Identifies the SMM register to check for support.
> +
> + @retval TRUE The SMM register specified by RegName is supported by the
> CPU
> + specified by CpuIndex.
> + @retval FALSE The SMM register specified by RegName is not supported by
> the
> + CPU specified by CpuIndex.
> +**/
> +BOOLEAN
> +EFIAPI
> +SmmCpuFeaturesIsSmmRegisterSupported (
> + IN UINTN CpuIndex,
> + IN SMM_REG_NAME RegName
> + )
> +{
> + return FALSE;
> +}
> +
> +/**
> + This function is hook point called after the
> gEfiSmmReadyToLockProtocolGuid
> + notification is completely processed.
> +**/
> +VOID
> +EFIAPI
> +SmmCpuFeaturesCompleteSmmReadyToLock (
> + VOID
> + )
> +{
> +}
> --
> 2.25.1

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Re: [edk2-devel] [PATCH v1 4/5] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family

[Chang, Abner]

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Hi Abdul,
This is a little bit confusing because there is one SmramSaveStae.c under PismmCpuDxeSmm however another one is under SmmCpuFeaturesLib for AMD.
I would suggest we introduce SmramSaveState library under UefiCpuPkg/Library which is used by both PismmCpuDxeSmm and SmmCpuFeaturesLib. This makes the library reference clear without duplication.
We can have AMD SmramSaveStateLib instance and just name it as SmramSaveStateLib.c. That is Intel's decision if they want to move their implementation from PismmCpuDxeSmm to SmramSaveState or not.
Thanks
Abner

On Tue, Dec 6, 2022 at 09:23 PM, Abdul Lateef Attar wrote:

> 
> From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182
> 
> Implements interfaces to read and write save state
> registers of AMD's processor family.
> Initializes processor SMMADDR and MASK depends
> on PcdSmrrEnable flag.
> Program or corrects the IP once control returns from SMM.
> 
> Cc: Paul Grimes <paul.grimes@amd.com>
> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com>
> Cc: Abner Chang <abner.chang@amd.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
> ---
> .../AmdSmmCpuFeaturesLib.inf | 2 +
> .../SmmCpuFeaturesLib/Amd/SmramSaveState.h | 109 +++++
> .../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c | 97 ++++-
> .../SmmCpuFeaturesLib/Amd/SmramSaveState.c | 409 ++++++++++++++++++
> 4 files changed, 612 insertions(+), 5 deletions(-)
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.c
> 
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> index 08ac0262022f..95eb31d16ead 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> @@ -21,6 +21,8 @@ [Sources]
> SmmCpuFeaturesLib.c
> SmmCpuFeaturesLibCommon.c
> Amd/SmmCpuFeaturesLib.c
> + Amd/SmramSaveState.c
> + Amd/SmramSaveState.h
> 
> [Packages]
> MdePkg/MdePkg.dec
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
> new file mode 100644
> index 000000000000..290ebdbc9227
> --- /dev/null
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
> @@ -0,0 +1,109 @@
> +/** @file
> +SMRAM Save State Map header file.
> +
> +Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
> +Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef SMRAM_SAVESTATE_H_
> +#define SMRAM_SAVESTATE_H_
> +
> +#include <Library/SmmCpuFeaturesLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/SmmServicesTableLib.h>
> +#include <Register/Amd/SmramSaveStateMap.h>
> +
> +// EFER register LMA bit
> +#define LMA BIT10
> +
> +// Machine Specific Registers (MSRs)
> +#define SMMADDR_ADDRESS 0xC0010112ul
> +#define SMMMASK_ADDRESS 0xC0010113ul
> +#define EFER_ADDRESS 0XC0000080ul
> +
> +// Macro used to simplify the lookup table entries of type
> CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
> +#define SMM_CPU_OFFSET(Field) OFFSET_OF (AMD_SMRAM_SAVE_STATE_MAP, Field)
> 
> +
> +// Macro used to simplify the lookup table entries of type
> CPU_SMM_SAVE_STATE_REGISTER_RANGE
> +#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
> +
> +// Structure used to describe a range of registers
> +typedef struct {
> + EFI_SMM_SAVE_STATE_REGISTER Start;
> + EFI_SMM_SAVE_STATE_REGISTER End;
> + UINTN Length;
> +} CPU_SMM_SAVE_STATE_REGISTER_RANGE;
> +
> +// Structure used to build a lookup table to retrieve the widths and
> offsets
> +// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
> +
> +#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1
> +#define SMM_SAVE_STATE_REGISTER_MAX_INDEX 2
> +
> +typedef struct {
> + UINT8 Width32;
> + UINT8 Width64;
> + UINT16 Offset32;
> + UINT16 Offset64Lo;
> + UINT16 Offset64Hi;
> + BOOLEAN Writeable;
> +} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
> +
> +/**
> + Read an SMM Save State register on the target processor. If this
> function
> + returns EFI_UNSUPPORTED, then the caller is responsible for reading the
> + SMM Save Sate register.
> +
> + @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
> 
> + value must be between 0 and the NumberOfCpus field in
> + the System Management System Table (SMST).
> + @param[in] Register The SMM Save State register to read.
> + @param[in] Width The number of bytes to read from the CPU save state.
> + @param[out] Buffer Upon return, this holds the CPU register value read
> + from the save state.
> +
> + @retval EFI_SUCCESS The register was read from Save State.
> + @retval EFI_INVALID_PARAMTER Buffer is NULL.
> + @retval EFI_UNSUPPORTED This function does not support reading Register.
> 
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InternalSmmCpuFeaturesReadSaveStateRegister (
> + IN UINTN CpuIndex,
> + IN EFI_SMM_SAVE_STATE_REGISTER Register,
> + IN UINTN Width,
> + OUT VOID *Buffer
> + );
> +
> +/**
> + Writes an SMM Save State register on the target processor. If this
> function
> + returns EFI_UNSUPPORTED, then the caller is responsible for writing the
> + SMM Save Sate register.
> +
> + @param[in] CpuIndex The index of the CPU to write the SMM Save State.
> The
> + value must be between 0 and the NumberOfCpus field in
> + the System Management System Table (SMST).
> + @param[in] Register The SMM Save State register to write.
> + @param[in] Width The number of bytes to write to the CPU save state.
> + @param[in] Buffer Upon entry, this holds the new CPU register value.
> +
> + @retval EFI_SUCCESS The register was written to Save State.
> + @retval EFI_INVALID_PARAMTER Buffer is NULL.
> + @retval EFI_UNSUPPORTED This function does not support writing Register.
> 
> +**/
> +EFI_STATUS
> +EFIAPI
> +InternalSmmCpuFeaturesWriteSaveStateRegister (
> + IN UINTN CpuIndex,
> + IN EFI_SMM_SAVE_STATE_REGISTER Register,
> + IN UINTN Width,
> + IN CONST VOID *Buffer
> + );
> +
> +#endif
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
> index dc3fed0302d2..10bed4116397 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
> @@ -9,8 +9,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> **/
> 
> -#include <Library/SmmCpuFeaturesLib.h>
> -#include <Uefi/UefiBaseType.h>
> +#include "SmramSaveState.h"
> +
> +// The mode of the CPU at the time an SMI occurs
> +extern UINT8 mSmmSaveStateRegisterLma;
> 
> /**
> Read an SMM Save State register on the target processor. If this function
> @@ -39,7 +41,7 @@ SmmCpuFeaturesReadSaveStateRegister (
> OUT VOID *Buffer
> )
> {
> - return EFI_SUCCESS;
> + return InternalSmmCpuFeaturesReadSaveStateRegister (CpuIndex, Register,
> Width, Buffer);
> }
> 
> /**
> @@ -67,7 +69,7 @@ SmmCpuFeaturesWriteSaveStateRegister (
> IN CONST VOID *Buffer
> )
> {
> - return EFI_SUCCESS;
> + return InternalSmmCpuFeaturesWriteSaveStateRegister (CpuIndex, Register,
> Width, Buffer);
> }
> 
> /**
> @@ -82,6 +84,13 @@ CpuFeaturesLibInitialization (
> VOID
> )
> {
> + UINT32 LMAValue;
> +
> + LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
> + mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
> + if (LMAValue) {
> + mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
> + }
> }
> 
> /**
> @@ -117,6 +126,52 @@ SmmCpuFeaturesInitializeProcessor (
> IN CPU_HOT_PLUG_DATA *CpuHotPlugData
> )
> {
> + AMD_SMRAM_SAVE_STATE_MAP *CpuState;
> + UINT32 LMAValue;
> +
> + //
> + // Configure SMBASE.
> + //
> + CpuState = (AMD_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE +
> SMRAM_SAVE_STATE_MAP_OFFSET);
> + CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
> +
> + // Re-initialize the value of mSmmSaveStateRegisterLma flag which might
> have been changed in PiCpuSmmDxeSmm Driver
> + // Entry point, to make sure correct value on AMD platform is assigned
> to be used by SmmCpuFeaturesLib.
> + LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
> + mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
> + if (LMAValue) {
> + mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
> + }
> +
> + //
> + // If SMRR is supported, then program SMRR base/mask MSRs.
> + // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first
> normal SMI.
> + // The code that initializes SMM environment is running in normal mode
> + // from SMRAM region. If SMRR is enabled here, then the SMRAM region
> + // is protected and the normal mode code execution will fail.
> + //
> + if (FeaturePcdGet (PcdSmrrEnable)) {
> + //
> + // SMRR size cannot be less than 4-KBytes
> + // SMRR size must be of length 2^n
> + // SMRR base alignment cannot be less than SMRR length
> + //
> + if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||
> + (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize))
> ||
> + ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) !=
> CpuHotPlugData->SmrrBase))
> + {
> + //
> + // Print message and halt if CPU is Monarch
> + //
> + if (IsMonarch) {
> + DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size
> requirement!\n"));
> + CpuDeadLoop ();
> + }
> + } else {
> + AsmWriteMsr64 (SMMADDR_ADDRESS, CpuHotPlugData->SmrrBase);
> + AsmWriteMsr64 (SMMMASK_ADDRESS, ((~(UINT64)(CpuHotPlugData->SmrrSize -
> 1)) | 0x6600));
> + }
> + }
> }
> 
> /**
> @@ -159,7 +214,39 @@ SmmCpuFeaturesHookReturnFromSmm (
> IN UINT64 NewInstructionPointer
> )
> {
> - return 0;
> + UINT64 OriginalInstructionPointer;
> + AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState;
> +
> + AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState;
> +
> + if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
> 
> + OriginalInstructionPointer = (UINT64)AmdCpuState->x86._EIP;
> + AmdCpuState->x86._EIP = (UINT32)NewInstructionPointer;
> + //
> + // Clear the auto HALT restart flag so the RSM instruction returns
> + // program control to the instruction following the HLT instruction.
> + //
> + if ((AmdCpuState->x86.AutoHALTRestart & BIT0) != 0) {
> + AmdCpuState->x86.AutoHALTRestart &= ~BIT0;
> + }
> + } else {
> + OriginalInstructionPointer = AmdCpuState->x64._RIP;
> + if ((AmdCpuState->x64.EFER & LMA) == 0) {
> + AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer32;
> + } else {
> + AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer;
> + }
> +
> + //
> + // Clear the auto HALT restart flag so the RSM instruction returns
> + // program control to the instruction following the HLT instruction.
> + //
> + if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != 0) {
> + AmdCpuState->x64.AutoHALTRestart &= ~BIT0;
> + }
> + }
> +
> + return OriginalInstructionPointer;
> }
> 
> /**
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.c
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.c
> new file mode 100644
> index 000000000000..c1e7e6d6c6d9
> --- /dev/null
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.c
> @@ -0,0 +1,409 @@
> +/** @file
> +Provides services to access SMRAM Save State Map
> +
> +Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
> +Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "SmramSaveState.h"
> +
> +// The mode of the CPU at the time an SMI occurs
> +extern UINT8 mSmmSaveStateRegisterLma;
> +
> +// Table used by GetRegisterIndex() to convert an
> EFI_SMM_SAVE_STATE_REGISTER
> +// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
> 
> +static CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] =
> {
> + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,
> EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),
> + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES,
> EFI_SMM_SAVE_STATE_REGISTER_RIP),
> + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,
> EFI_SMM_SAVE_STATE_REGISTER_CR4),
> + { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0}
> +};
> +
> +// Lookup table used to retrieve the widths and offsets associated with
> each
> +// supported EFI_SMM_SAVE_STATE_REGISTER value
> +static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
> + { 0, 0, 0, 0, FALSE }, // Reserved
> +
> + //
> + // Internally defined CPU Save State Registers. Not defined in PI SMM
> CPU Protocol.
> + //
> + { 4, 4, SMM_CPU_OFFSET (x86.SMMRevId), SMM_CPU_OFFSET (x64.SMMRevId), 0,
> FALSE}, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1
> +
> + //
> + // CPU Save State registers defined in PI SMM CPU Protocol.
> + //
> + { 4, 8, SMM_CPU_OFFSET (x86.GDTBase), SMM_CPU_OFFSET
> (x64._GDTRBaseLoDword), SMM_CPU_OFFSET (x64._GDTRBaseHiDword), FALSE}, //
> EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
> + { 0, 8, 0, SMM_CPU_OFFSET (x64._IDTRBaseLoDword), SMM_CPU_OFFSET
> (x64._IDTRBaseLoDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
> 
> + { 0, 8, 0, SMM_CPU_OFFSET (x64._LDTRBaseLoDword), SMM_CPU_OFFSET
> (x64._LDTRBaseLoDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
> 
> + { 0, 2, 0, SMM_CPU_OFFSET (x64._GDTRLimit), 0, FALSE}, //
> EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
> + { 0, 2, 0, SMM_CPU_OFFSET (x64._IDTRLimit), 0, FALSE}, //
> EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
> + { 0, 4, 0, SMM_CPU_OFFSET (x64._LDTRLimit), 0, FALSE}, //
> EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
> + { 0, 0, 0, 0, 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
> + { 4, 2, SMM_CPU_OFFSET (x86._ES), SMM_CPU_OFFSET (x64._ES), 0, FALSE},
> // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
> + { 4, 2, SMM_CPU_OFFSET (x86._CS), SMM_CPU_OFFSET (x64._CS), 0, FALSE},
> // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
> + { 4, 2, SMM_CPU_OFFSET (x86._SS), SMM_CPU_OFFSET (x64._SS), 0, FALSE},
> // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
> + { 4, 2, SMM_CPU_OFFSET (x86._DS), SMM_CPU_OFFSET (x64._DS), 0, FALSE},
> // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
> + { 4, 2, SMM_CPU_OFFSET (x86._FS), SMM_CPU_OFFSET (x64._FS), 0, FALSE},
> // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
> + { 4, 2, SMM_CPU_OFFSET (x86._GS), SMM_CPU_OFFSET (x64._GS), 0, FALSE},
> // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
> + { 0, 2, 0, SMM_CPU_OFFSET (x64._LDTR), 0, FALSE}, //
> EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
> + { 0, 2, 0, SMM_CPU_OFFSET (x64._TR), 0, FALSE}, //
> EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
> + { 4, 8, SMM_CPU_OFFSET (x86._DR7), SMM_CPU_OFFSET (x64._DR7),
> SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7
> = 28
> + { 4, 8, SMM_CPU_OFFSET (x86._DR6), SMM_CPU_OFFSET (x64._DR6),
> SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6
> = 29
> + { 0, 8, 0, SMM_CPU_OFFSET (x64._R8), SMM_CPU_OFFSET (x64._R8) + 4,
> TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
> + { 0, 8, 0, SMM_CPU_OFFSET (x64._R9), SMM_CPU_OFFSET (x64._R9) + 4,
> TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
> + { 0, 8, 0, SMM_CPU_OFFSET (x64._R10), SMM_CPU_OFFSET (x64._R10) + 4,
> TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
> + { 0, 8, 0, SMM_CPU_OFFSET (x64._R11), SMM_CPU_OFFSET (x64._R11) + 4,
> TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
> + { 0, 8, 0, SMM_CPU_OFFSET (x64._R12), SMM_CPU_OFFSET (x64._R12) + 4,
> TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
> + { 0, 8, 0, SMM_CPU_OFFSET (x64._R13), SMM_CPU_OFFSET (x64._R13) + 4,
> TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
> + { 0, 8, 0, SMM_CPU_OFFSET (x64._R14), SMM_CPU_OFFSET (x64._R14) + 4,
> TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
> + { 0, 8, 0, SMM_CPU_OFFSET (x64._R15), SMM_CPU_OFFSET (x64._R15) + 4,
> TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
> + { 4, 8, SMM_CPU_OFFSET (x86._EAX), SMM_CPU_OFFSET (x64._RAX),
> SMM_CPU_OFFSET (x64._RAX) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RAX =
> 38
> + { 4, 8, SMM_CPU_OFFSET (x86._EBX), SMM_CPU_OFFSET (x64._RBX),
> SMM_CPU_OFFSET (x64._RBX) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RBX =
> 39
> + { 4, 8, SMM_CPU_OFFSET (x86._ECX), SMM_CPU_OFFSET (x64._RCX),
> SMM_CPU_OFFSET (x64._RCX) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RBX =
> 39
> + { 4, 8, SMM_CPU_OFFSET (x86._EDX), SMM_CPU_OFFSET (x64._RDX),
> SMM_CPU_OFFSET (x64._RDX) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RDX =
> 41
> + { 4, 8, SMM_CPU_OFFSET (x86._ESP), SMM_CPU_OFFSET (x64._RSP),
> SMM_CPU_OFFSET (x64._RSP) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RSP =
> 42
> + { 4, 8, SMM_CPU_OFFSET (x86._EBP), SMM_CPU_OFFSET (x64._RBP),
> SMM_CPU_OFFSET (x64._RBP) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RBP =
> 43
> + { 4, 8, SMM_CPU_OFFSET (x86._ESI), SMM_CPU_OFFSET (x64._RSI),
> SMM_CPU_OFFSET (x64._RSI) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RSI =
> 44
> + { 4, 8, SMM_CPU_OFFSET (x86._EDI), SMM_CPU_OFFSET (x64._RDI),
> SMM_CPU_OFFSET (x64._RDI) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RDI =
> 45
> + { 4, 8, SMM_CPU_OFFSET (x86._EIP), SMM_CPU_OFFSET (x64._RIP),
> SMM_CPU_OFFSET (x64._RIP) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RIP =
> 46
> +
> + { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS), SMM_CPU_OFFSET (x64._RFLAGS),
> SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE}, //
> EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
> + { 4, 8, SMM_CPU_OFFSET (x86._CR0), SMM_CPU_OFFSET (x64._CR0),
> SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0
> = 52
> + { 4, 8, SMM_CPU_OFFSET (x86._CR3), SMM_CPU_OFFSET (x64._CR3),
> SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3
> = 53
> + { 0, 8, 0, SMM_CPU_OFFSET (x64._CR4), SMM_CPU_OFFSET (x64._CR4) + 4,
> FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
> + { 0, 0, 0, 0, 0 }
> +};
> +
> +/**
> + Read information from the CPU save state.
> +
> + @param Register Specifies the CPU register to read form the save state.
> +
> + @retval 0 Register is not valid
> + @retval >0 Index into mSmmCpuWidthOffset[] associated with Register
> +
> +**/
> +STATIC
> +UINTN
> +EFIAPI
> +GetRegisterIndex (
> + IN EFI_SMM_SAVE_STATE_REGISTER Register
> + )
> +{
> + UINTN Index;
> + UINTN Offset;
> +
> + for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX;
> mSmmCpuRegisterRanges[Index].Length != 0; Index++) {
> + if ((Register >= mSmmCpuRegisterRanges[Index].Start) && (Register <=
> mSmmCpuRegisterRanges[Index].End)) {
> + return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
> + }
> +
> + Offset += mSmmCpuRegisterRanges[Index].Length;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + Read a CPU Save State register on the target processor.
> +
> + This function abstracts the differences that whether the CPU Save State
> register is in the
> + IA32 CPU Save State Map or X64 CPU Save State Map.
> +
> + This function supports reading a CPU Save State register in SMBase
> relocation handler.
> +
> + @param[in] CpuIndex Specifies the zero-based index of the CPU save
> state.
> + @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
> + @param[in] Width The number of bytes to read from the CPU save state.
> + @param[out] Buffer Upon return, this holds the CPU register value read
> from the save state.
> +
> + @retval EFI_SUCCESS The register was read from Save State.
> + @retval EFI_NOT_FOUND The register is not defined for the Save State of
> Processor.
> + @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +ReadSaveStateRegisterByIndex (
> + IN UINTN CpuIndex,
> + IN UINTN RegisterIndex,
> + IN UINTN Width,
> + OUT VOID *Buffer
> + )
> +{
> + AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState;
> +
> + // UINT32 SmmRevId;
> +
> + if (RegisterIndex == 0) {
> + return EFI_NOT_FOUND;
> + }
> +
> + CpuSaveState = gSmst->CpuSaveState[CpuIndex];
> + // SmmRevId = CpuSaveState->x86.SMMRevId;
> +
> + if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
> 
> + //
> + // If 32-bit mode width is zero, then the specified register can not be
> accessed
> + //
> + if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // If Width is bigger than the 32-bit mode width, then the specified
> register can not be accessed
> + //
> + if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Write return buffer
> + //
> + ASSERT (CpuSaveState != NULL);
> + CopyMem (Buffer, (UINT8 *)CpuSaveState +
> mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);
> + } else {
> + //
> + // If 64-bit mode width is zero, then the specified register can not be
> accessed
> + //
> + if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // If Width is bigger than the 64-bit mode width, then the specified
> register can not be accessed
> + //
> + if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Write lower 32-bits of return buffer
> + //
> + CopyMem (Buffer, (UINT8 *)CpuSaveState +
> mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN (4, Width));
> + if (Width >= 4) {
> + //
> + // Write upper 32-bits of return buffer
> + //
> + CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState +
> mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Read an SMM Save State register on the target processor. If this
> function
> + returns EFI_UNSUPPORTED, then the caller is responsible for reading the
> + SMM Save Sate register.
> +
> + @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
> 
> + value must be between 0 and the NumberOfCpus field in
> + the System Management System Table (SMST).
> + @param[in] Register The SMM Save State register to read.
> + @param[in] Width The number of bytes to read from the CPU save state.
> + @param[out] Buffer Upon return, this holds the CPU register value read
> + from the save state.
> +
> + @retval EFI_SUCCESS The register was read from Save State.
> + @retval EFI_INVALID_PARAMTER Buffer is NULL.
> + @retval EFI_UNSUPPORTED This function does not support reading Register.
> 
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InternalSmmCpuFeaturesReadSaveStateRegister (
> + IN UINTN CpuIndex,
> + IN EFI_SMM_SAVE_STATE_REGISTER Register,
> + IN UINTN Width,
> + OUT VOID *Buffer
> + )
> +{
> + UINT32 SmmRevId;
> + EFI_SMM_SAVE_STATE_IO_INFO *IoInfo;
> + AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState;
> + UINT8 DataWidth;
> +
> + // Read CPU State
> + CpuSaveState = (AMD_SMRAM_SAVE_STATE_MAP
> *)gSmst->CpuSaveState[CpuIndex];
> +
> + // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
> + if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
> + // Only byte access is supported for this register
> + if (Width != 1) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + *(UINT8 *)Buffer = mSmmSaveStateRegisterLma;
> +
> + return EFI_SUCCESS;
> + }
> +
> + // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
> +
> + if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
> + //
> + // Get SMM Revision ID
> + //
> + ReadSaveStateRegisterByIndex (CpuIndex,
> SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId);
> +
> + //
> + // See if the CPU supports the IOMisc register in the save state
> + //
> + if (SmmRevId < AMD_SMM_MIN_REV_ID_X64) {
> + return EFI_NOT_FOUND;
> + }
> +
> + // Check if IO Restart Dword [IO Trap] is valid or not using bit 1.
> + if (!(CpuSaveState->x64.IO_DWord & 0x02u)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + // Zero the IoInfo structure that will be returned in Buffer
> + IoInfo = (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer;
> + ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO));
> +
> + IoInfo->IoPort = (UINT16)(CpuSaveState->x64.IO_DWord >> 16u);
> +
> + if (CpuSaveState->x64.IO_DWord & 0x10u) {
> + IoInfo->IoWidth = EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8;
> + DataWidth = 0x01u;
> + } else if (CpuSaveState->x64.IO_DWord & 0x20u) {
> + IoInfo->IoWidth = EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16;
> + DataWidth = 0x02u;
> + } else {
> + IoInfo->IoWidth = EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32;
> + DataWidth = 0x04u;
> + }
> +
> + if (CpuSaveState->x64.IO_DWord & 0x01u) {
> + IoInfo->IoType = EFI_SMM_SAVE_STATE_IO_TYPE_INPUT;
> + } else {
> + IoInfo->IoType = EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT;
> + }
> +
> + if ((IoInfo->IoType == EFI_SMM_SAVE_STATE_IO_TYPE_INPUT) ||
> (IoInfo->IoType == EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT)) {
> + SmmCpuFeaturesReadSaveStateRegister (CpuIndex,
> EFI_SMM_SAVE_STATE_REGISTER_RAX, DataWidth, &IoInfo->IoData);
> + }
> +
> + return EFI_SUCCESS;
> + }
> +
> + // Convert Register to a register lookup table index
> + return ReadSaveStateRegisterByIndex (CpuIndex, GetRegisterIndex
> (Register), Width, Buffer);
> +}
> +
> +/**
> + Writes an SMM Save State register on the target processor. If this
> function
> + returns EFI_UNSUPPORTED, then the caller is responsible for writing the
> + SMM Save Sate register.
> +
> + @param[in] CpuIndex The index of the CPU to write the SMM Save State.
> The
> + value must be between 0 and the NumberOfCpus field in
> + the System Management System Table (SMST).
> + @param[in] Register The SMM Save State register to write.
> + @param[in] Width The number of bytes to write to the CPU save state.
> + @param[in] Buffer Upon entry, this holds the new CPU register value.
> +
> + @retval EFI_SUCCESS The register was written to Save State.
> + @retval EFI_INVALID_PARAMTER Buffer is NULL.
> + @retval EFI_UNSUPPORTED This function does not support writing Register.
> 
> +**/
> +EFI_STATUS
> +EFIAPI
> +InternalSmmCpuFeaturesWriteSaveStateRegister (
> + IN UINTN CpuIndex,
> + IN EFI_SMM_SAVE_STATE_REGISTER Register,
> + IN UINTN Width,
> + IN CONST VOID *Buffer
> + )
> +{
> + UINTN RegisterIndex;
> + AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState;
> +
> + //
> + // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
> + //
> + if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
> + return EFI_SUCCESS;
> + }
> +
> + //
> + // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
> + //
> + if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // Convert Register to a register lookup table index
> + //
> + RegisterIndex = GetRegisterIndex (Register);
> + if (RegisterIndex == 0) {
> + return EFI_NOT_FOUND;
> + }
> +
> + CpuSaveState = gSmst->CpuSaveState[CpuIndex];
> +
> + //
> + // Do not write non-writable SaveState, because it will cause exception.
> 
> + //
> + if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Check CPU mode
> + //
> + if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
> 
> + //
> + // If 32-bit mode width is zero, then the specified register can not be
> accessed
> + //
> + if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // If Width is bigger than the 32-bit mode width, then the specified
> register can not be accessed
> + //
> + if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Write SMM State register
> + //
> + ASSERT (CpuSaveState != NULL);
> + CopyMem ((UINT8 *)CpuSaveState +
> mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
> + } else {
> + //
> + // If 64-bit mode width is zero, then the specified register can not be
> accessed
> + //
> + if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // If Width is bigger than the 64-bit mode width, then the specified
> register can not be accessed
> + //
> + if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Write lower 32-bits of SMM State register
> + //
> + CopyMem ((UINT8 *)CpuSaveState +
> mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
> + if (Width >= 4) {
> + //
> + // Write upper 32-bits of SMM State register
> + //
> + CopyMem ((UINT8 *)CpuSaveState +
> mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width -
> 4);
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> --
> 2.25.1

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Re: [edk2-devel] [PATCH v1 5/5] UefiCpuPkg/AmdSmmCpuFeaturesLib: Handles S3 save state

[Chang, Abner]

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Apart from the comment given to 4/5, I am afraid those extern variables in C file is not obey the section 5.4.2.1 extern in CCS.

Regards,
Abner

Abner
On Tue, Dec 6, 2022 at 09:23 PM, Abdul Lateef Attar wrote:

> 
> ---
> .../AmdSmmCpuFeaturesLib.inf | 1 +
> .../SmmCpuFeaturesLib/Amd/SmramSaveState.h | 19 +++++++++++
> .../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c | 32 +++++++++++++++++++
> 3 files changed, 52 insertions(+)
> 
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> index 95eb31d16ead..7fd559e91ad8 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> @@ -27,6 +27,7 @@ [Sources]
> [Packages]
> MdePkg/MdePkg.dec
> UefiCpuPkg/UefiCpuPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> 
> [LibraryClasses]
> BaseLib
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
> index 290ebdbc9227..474a5dbd9765 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
> @@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include <Library/DebugLib.h>
> #include <Library/SmmServicesTableLib.h>
> #include <Register/Amd/SmramSaveStateMap.h>
> +#include <Guid/AcpiS3Context.h>
> 
> // EFER register LMA bit
> #define LMA BIT10
> @@ -106,4 +107,22 @@ InternalSmmCpuFeaturesWriteSaveStateRegister (
> IN CONST VOID *Buffer
> );
> 
> +/**
> + Initialize MP synchronization data.
> +**/
> +VOID
> +EFIAPI
> +InitializeMpSyncData (
> + VOID
> + );
> +
> +/**
> + Perform SMM MP sync Semaphores re-initialization in the S3 boot path.
> +**/
> +VOID
> +EFIAPI
> +SmmS3MpSemaphoreInit (
> + VOID
> + );
> +
> #endif
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
> index 10bed4116397..b855573d9401 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
> @@ -14,6 +14,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> // The mode of the CPU at the time an SMI occurs
> extern UINT8 mSmmSaveStateRegisterLma;
> 
> +// SMM S3 resume state Ptr
> +extern SMM_S3_RESUME_STATE *mSmmS3ResumeState;
> +
> /**
> Read an SMM Save State register on the target processor. If this function
> returns EFI_UNSUPPORTED, then the caller is responsible for reading the
> @@ -441,4 +444,33 @@ SmmCpuFeaturesCompleteSmmReadyToLock (
> VOID
> )
> {
> + if (mSmmS3ResumeState != NULL ) {
> + mSmmS3ResumeState->SmmS3ResumeEntryPoint =
> (EFI_PHYSICAL_ADDRESS)(UINTN)SmmS3MpSemaphoreInit;
> + }
> +}
> +
> +/**
> + Perform SMM MP sync Semaphores re-initialization in the S3 boot path.
> +**/
> +VOID
> +EFIAPI
> +SmmS3MpSemaphoreInit (
> + VOID
> + )
> +{
> + InitializeMpSyncData ();
> +
> + DEBUG ((DEBUG_INFO, "SMM S3 Return CS = %x\n",
> mSmmS3ResumeState->ReturnCs));
> + DEBUG ((DEBUG_INFO, "SMM S3 Return Entry Point = %x\n",
> mSmmS3ResumeState->ReturnEntryPoint));
> + DEBUG ((DEBUG_INFO, "SMM S3 Return Context1 = %x\n",
> mSmmS3ResumeState->ReturnContext1));
> + DEBUG ((DEBUG_INFO, "SMM S3 Return Context2 = %x\n",
> mSmmS3ResumeState->ReturnContext2));
> + DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n",
> mSmmS3ResumeState->ReturnStackPointer));
> +
> + AsmDisablePaging64 (
> + mSmmS3ResumeState->ReturnCs,
> + (UINT32)mSmmS3ResumeState->ReturnEntryPoint,
> + (UINT32)mSmmS3ResumeState->ReturnContext1,
> + (UINT32)mSmmS3ResumeState->ReturnContext2,
> + (UINT32)mSmmS3ResumeState->ReturnStackPointer
> + );
> }
> --

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Re: [edk2-devel] [PATCH v1 4/5] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family

[Attar, AbdulLateef (Abdul Lateef)]

[-- Attachment #1: Type: text/plain, Size: 28775 bytes --]

[AMD Official Use Only - General]

Hi Abner,
                Thanks for quick review. I'll create a new library and submit the patch.
Thanks
AbduL

From: abner.chang via groups.io <abner.chang=amd.com@groups.io>
Sent: 08 December 2022 10:38
To: Attar, AbdulLateef (Abdul Lateef) <AbdulLateef.Attar@amd.com>; devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH v1 4/5] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family

Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.

Hi Abdul,
This is a little bit confusing because there is one SmramSaveStae.c under PismmCpuDxeSmm however another one is under SmmCpuFeaturesLib for AMD.
I would suggest we introduce SmramSaveState library under UefiCpuPkg/Library which is used by both PismmCpuDxeSmm and SmmCpuFeaturesLib. This makes the library reference clear without duplication.
We can have AMD SmramSaveStateLib instance and just name it as SmramSaveStateLib.c. That is Intel's decision if they want to move their implementation from PismmCpuDxeSmm to SmramSaveState or not.
Thanks
Abner

On Tue, Dec 6, 2022 at 09:23 PM, Abdul Lateef Attar wrote:
From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com<mailto:AbdulLateef.Attar@amd.com>>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182<https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D4182&data=05%7C01%7CAbdulLateef.Attar%40amd.com%7C32f4892e39954cbdc31d08dad8da1d95%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C638060728564261470%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=np1IkSMu3ZBp2tWmKsIO07FFLATLhpDY6JaWiFjluQU%3D&reserved=0>

Implements interfaces to read and write save state
registers of AMD's processor family.
Initializes processor SMMADDR and MASK depends
on PcdSmrrEnable flag.
Program or corrects the IP once control returns from SMM.

Cc: Paul Grimes <paul.grimes@amd.com<mailto:paul.grimes@amd.com>>
Cc: Garrett Kirkendall <garrett.kirkendall@amd.com<mailto:garrett.kirkendall@amd.com>>
Cc: Abner Chang <abner.chang@amd.com<mailto:abner.chang@amd.com>>
Cc: Eric Dong <eric.dong@intel.com<mailto:eric.dong@intel.com>>
Cc: Ray Ni <ray.ni@intel.com<mailto:ray.ni@intel.com>>
Cc: Rahul Kumar <rahul1.kumar@intel.com<mailto:rahul1.kumar@intel.com>>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com<mailto:AbdulLateef.Attar@amd.com>>
---
.../AmdSmmCpuFeaturesLib.inf | 2 +
.../SmmCpuFeaturesLib/Amd/SmramSaveState.h | 109 +++++
.../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c | 97 ++++-
.../SmmCpuFeaturesLib/Amd/SmramSaveState.c | 409 ++++++++++++++++++
4 files changed, 612 insertions(+), 5 deletions(-)
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.c

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
index 08ac0262022f..95eb31d16ead 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
@@ -21,6 +21,8 @@ [Sources]
SmmCpuFeaturesLib.c
SmmCpuFeaturesLibCommon.c
Amd/SmmCpuFeaturesLib.c
+ Amd/SmramSaveState.c
+ Amd/SmramSaveState.h

[Packages]
MdePkg/MdePkg.dec
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
new file mode 100644
index 000000000000..290ebdbc9227
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
@@ -0,0 +1,109 @@
+/** @file
+SMRAM Save State Map header file.
+
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SMRAM_SAVESTATE_H_
+#define SMRAM_SAVESTATE_H_
+
+#include <Library/SmmCpuFeaturesLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Register/Amd/SmramSaveStateMap.h>
+
+// EFER register LMA bit
+#define LMA BIT10
+
+// Machine Specific Registers (MSRs)
+#define SMMADDR_ADDRESS 0xC0010112ul
+#define SMMMASK_ADDRESS 0xC0010113ul
+#define EFER_ADDRESS 0XC0000080ul
+
+// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
+#define SMM_CPU_OFFSET(Field) OFFSET_OF (AMD_SMRAM_SAVE_STATE_MAP, Field)
+
+// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE
+#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
+
+// Structure used to describe a range of registers
+typedef struct {
+ EFI_SMM_SAVE_STATE_REGISTER Start;
+ EFI_SMM_SAVE_STATE_REGISTER End;
+ UINTN Length;
+} CPU_SMM_SAVE_STATE_REGISTER_RANGE;
+
+// Structure used to build a lookup table to retrieve the widths and offsets
+// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
+
+#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1
+#define SMM_SAVE_STATE_REGISTER_MAX_INDEX 2
+
+typedef struct {
+ UINT8 Width32;
+ UINT8 Width64;
+ UINT16 Offset32;
+ UINT16 Offset64Lo;
+ UINT16 Offset64Hi;
+ BOOLEAN Writeable;
+} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
+
+/**
+ Read an SMM Save State register on the target processor. If this function
+ returns EFI_UNSUPPORTED, then the caller is responsible for reading the
+ SMM Save Sate register.
+
+ @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
+ value must be between 0 and the NumberOfCpus field in
+ the System Management System Table (SMST).
+ @param[in] Register The SMM Save State register to read.
+ @param[in] Width The number of bytes to read from the CPU save state.
+ @param[out] Buffer Upon return, this holds the CPU register value read
+ from the save state.
+
+ @retval EFI_SUCCESS The register was read from Save State.
+ @retval EFI_INVALID_PARAMTER Buffer is NULL.
+ @retval EFI_UNSUPPORTED This function does not support reading Register.
+
+**/
+EFI_STATUS
+EFIAPI
+InternalSmmCpuFeaturesReadSaveStateRegister (
+ IN UINTN CpuIndex,
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,
+ IN UINTN Width,
+ OUT VOID *Buffer
+ );
+
+/**
+ Writes an SMM Save State register on the target processor. If this function
+ returns EFI_UNSUPPORTED, then the caller is responsible for writing the
+ SMM Save Sate register.
+
+ @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
+ value must be between 0 and the NumberOfCpus field in
+ the System Management System Table (SMST).
+ @param[in] Register The SMM Save State register to write.
+ @param[in] Width The number of bytes to write to the CPU save state.
+ @param[in] Buffer Upon entry, this holds the new CPU register value.
+
+ @retval EFI_SUCCESS The register was written to Save State.
+ @retval EFI_INVALID_PARAMTER Buffer is NULL.
+ @retval EFI_UNSUPPORTED This function does not support writing Register.
+**/
+EFI_STATUS
+EFIAPI
+InternalSmmCpuFeaturesWriteSaveStateRegister (
+ IN UINTN CpuIndex,
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,
+ IN UINTN Width,
+ IN CONST VOID *Buffer
+ );
+
+#endif
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
index dc3fed0302d2..10bed4116397 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
@@ -9,8 +9,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent

**/

-#include <Library/SmmCpuFeaturesLib.h>
-#include <Uefi/UefiBaseType.h>
+#include "SmramSaveState.h"
+
+// The mode of the CPU at the time an SMI occurs
+extern UINT8 mSmmSaveStateRegisterLma;

/**
Read an SMM Save State register on the target processor. If this function
@@ -39,7 +41,7 @@ SmmCpuFeaturesReadSaveStateRegister (
OUT VOID *Buffer
)
{
- return EFI_SUCCESS;
+ return InternalSmmCpuFeaturesReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
}

/**
@@ -67,7 +69,7 @@ SmmCpuFeaturesWriteSaveStateRegister (
IN CONST VOID *Buffer
)
{
- return EFI_SUCCESS;
+ return InternalSmmCpuFeaturesWriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
}

/**
@@ -82,6 +84,13 @@ CpuFeaturesLibInitialization (
VOID
)
{
+ UINT32 LMAValue;
+
+ LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
+ mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
+ if (LMAValue) {
+ mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
+ }
}

/**
@@ -117,6 +126,52 @@ SmmCpuFeaturesInitializeProcessor (
IN CPU_HOT_PLUG_DATA *CpuHotPlugData
)
{
+ AMD_SMRAM_SAVE_STATE_MAP *CpuState;
+ UINT32 LMAValue;
+
+ //
+ // Configure SMBASE.
+ //
+ CpuState = (AMD_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
+ CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
+
+ // Re-initialize the value of mSmmSaveStateRegisterLma flag which might have been changed in PiCpuSmmDxeSmm Driver
+ // Entry point, to make sure correct value on AMD platform is assigned to be used by SmmCpuFeaturesLib.
+ LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
+ mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
+ if (LMAValue) {
+ mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
+ }
+
+ //
+ // If SMRR is supported, then program SMRR base/mask MSRs.
+ // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.
+ // The code that initializes SMM environment is running in normal mode
+ // from SMRAM region. If SMRR is enabled here, then the SMRAM region
+ // is protected and the normal mode code execution will fail.
+ //
+ if (FeaturePcdGet (PcdSmrrEnable)) {
+ //
+ // SMRR size cannot be less than 4-KBytes
+ // SMRR size must be of length 2^n
+ // SMRR base alignment cannot be less than SMRR length
+ //
+ if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||
+ (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||
+ ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase))
+ {
+ //
+ // Print message and halt if CPU is Monarch
+ //
+ if (IsMonarch) {
+ DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));
+ CpuDeadLoop ();
+ }
+ } else {
+ AsmWriteMsr64 (SMMADDR_ADDRESS, CpuHotPlugData->SmrrBase);
+ AsmWriteMsr64 (SMMMASK_ADDRESS, ((~(UINT64)(CpuHotPlugData->SmrrSize - 1)) | 0x6600));
+ }
+ }
}

/**
@@ -159,7 +214,39 @@ SmmCpuFeaturesHookReturnFromSmm (
IN UINT64 NewInstructionPointer
)
{
- return 0;
+ UINT64 OriginalInstructionPointer;
+ AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState;
+
+ AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState;
+
+ if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
+ OriginalInstructionPointer = (UINT64)AmdCpuState->x86._EIP;
+ AmdCpuState->x86._EIP = (UINT32)NewInstructionPointer;
+ //
+ // Clear the auto HALT restart flag so the RSM instruction returns
+ // program control to the instruction following the HLT instruction.
+ //
+ if ((AmdCpuState->x86.AutoHALTRestart & BIT0) != 0) {
+ AmdCpuState->x86.AutoHALTRestart &= ~BIT0;
+ }
+ } else {
+ OriginalInstructionPointer = AmdCpuState->x64._RIP;
+ if ((AmdCpuState->x64.EFER & LMA) == 0) {
+ AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer32;
+ } else {
+ AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer;
+ }
+
+ //
+ // Clear the auto HALT restart flag so the RSM instruction returns
+ // program control to the instruction following the HLT instruction.
+ //
+ if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != 0) {
+ AmdCpuState->x64.AutoHALTRestart &= ~BIT0;
+ }
+ }
+
+ return OriginalInstructionPointer;
}

/**
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.c
new file mode 100644
index 000000000000..c1e7e6d6c6d9
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.c
@@ -0,0 +1,409 @@
+/** @file
+Provides services to access SMRAM Save State Map
+
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "SmramSaveState.h"
+
+// The mode of the CPU at the time an SMI occurs
+extern UINT8 mSmmSaveStateRegisterLma;
+
+// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
+// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
+static CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
+ SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),
+ SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP),
+ SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4),
+ { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0}
+};
+
+// Lookup table used to retrieve the widths and offsets associated with each
+// supported EFI_SMM_SAVE_STATE_REGISTER value
+static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
+ { 0, 0, 0, 0, FALSE }, // Reserved
+
+ //
+ // Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.
+ //
+ { 4, 4, SMM_CPU_OFFSET (x86.SMMRevId), SMM_CPU_OFFSET (x64.SMMRevId), 0, FALSE}, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1
+
+ //
+ // CPU Save State registers defined in PI SMM CPU Protocol.
+ //
+ { 4, 8, SMM_CPU_OFFSET (x86.GDTBase), SMM_CPU_OFFSET (x64._GDTRBaseLoDword), SMM_CPU_OFFSET (x64._GDTRBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._IDTRBaseLoDword), SMM_CPU_OFFSET (x64._IDTRBaseLoDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._LDTRBaseLoDword), SMM_CPU_OFFSET (x64._LDTRBaseLoDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
+ { 0, 2, 0, SMM_CPU_OFFSET (x64._GDTRLimit), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
+ { 0, 2, 0, SMM_CPU_OFFSET (x64._IDTRLimit), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
+ { 0, 4, 0, SMM_CPU_OFFSET (x64._LDTRLimit), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
+ { 0, 0, 0, 0, 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
+ { 4, 2, SMM_CPU_OFFSET (x86._ES), SMM_CPU_OFFSET (x64._ES), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
+ { 4, 2, SMM_CPU_OFFSET (x86._CS), SMM_CPU_OFFSET (x64._CS), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
+ { 4, 2, SMM_CPU_OFFSET (x86._SS), SMM_CPU_OFFSET (x64._SS), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
+ { 4, 2, SMM_CPU_OFFSET (x86._DS), SMM_CPU_OFFSET (x64._DS), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
+ { 4, 2, SMM_CPU_OFFSET (x86._FS), SMM_CPU_OFFSET (x64._FS), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
+ { 4, 2, SMM_CPU_OFFSET (x86._GS), SMM_CPU_OFFSET (x64._GS), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
+ { 0, 2, 0, SMM_CPU_OFFSET (x64._LDTR), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
+ { 0, 2, 0, SMM_CPU_OFFSET (x64._TR), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
+ { 4, 8, SMM_CPU_OFFSET (x86._DR7), SMM_CPU_OFFSET (x64._DR7), SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
+ { 4, 8, SMM_CPU_OFFSET (x86._DR6), SMM_CPU_OFFSET (x64._DR6), SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R8), SMM_CPU_OFFSET (x64._R8) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R9), SMM_CPU_OFFSET (x64._R9) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R10), SMM_CPU_OFFSET (x64._R10) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R11), SMM_CPU_OFFSET (x64._R11) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R12), SMM_CPU_OFFSET (x64._R12) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R13), SMM_CPU_OFFSET (x64._R13) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R14), SMM_CPU_OFFSET (x64._R14) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R15), SMM_CPU_OFFSET (x64._R15) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
+ { 4, 8, SMM_CPU_OFFSET (x86._EAX), SMM_CPU_OFFSET (x64._RAX), SMM_CPU_OFFSET (x64._RAX) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
+ { 4, 8, SMM_CPU_OFFSET (x86._EBX), SMM_CPU_OFFSET (x64._RBX), SMM_CPU_OFFSET (x64._RBX) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
+ { 4, 8, SMM_CPU_OFFSET (x86._ECX), SMM_CPU_OFFSET (x64._RCX), SMM_CPU_OFFSET (x64._RCX) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
+ { 4, 8, SMM_CPU_OFFSET (x86._EDX), SMM_CPU_OFFSET (x64._RDX), SMM_CPU_OFFSET (x64._RDX) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
+ { 4, 8, SMM_CPU_OFFSET (x86._ESP), SMM_CPU_OFFSET (x64._RSP), SMM_CPU_OFFSET (x64._RSP) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
+ { 4, 8, SMM_CPU_OFFSET (x86._EBP), SMM_CPU_OFFSET (x64._RBP), SMM_CPU_OFFSET (x64._RBP) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
+ { 4, 8, SMM_CPU_OFFSET (x86._ESI), SMM_CPU_OFFSET (x64._RSI), SMM_CPU_OFFSET (x64._RSI) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
+ { 4, 8, SMM_CPU_OFFSET (x86._EDI), SMM_CPU_OFFSET (x64._RDI), SMM_CPU_OFFSET (x64._RDI) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
+ { 4, 8, SMM_CPU_OFFSET (x86._EIP), SMM_CPU_OFFSET (x64._RIP), SMM_CPU_OFFSET (x64._RIP) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
+
+ { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS), SMM_CPU_OFFSET (x64._RFLAGS), SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
+ { 4, 8, SMM_CPU_OFFSET (x86._CR0), SMM_CPU_OFFSET (x64._CR0), SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
+ { 4, 8, SMM_CPU_OFFSET (x86._CR3), SMM_CPU_OFFSET (x64._CR3), SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._CR4), SMM_CPU_OFFSET (x64._CR4) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
+ { 0, 0, 0, 0, 0 }
+};
+
+/**
+ Read information from the CPU save state.
+
+ @param Register Specifies the CPU register to read form the save state.
+
+ @retval 0 Register is not valid
+ @retval >0 Index into mSmmCpuWidthOffset[] associated with Register
+
+**/
+STATIC
+UINTN
+EFIAPI
+GetRegisterIndex (
+ IN EFI_SMM_SAVE_STATE_REGISTER Register
+ )
+{
+ UINTN Index;
+ UINTN Offset;
+
+ for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {
+ if ((Register >= mSmmCpuRegisterRanges[Index].Start) && (Register <= mSmmCpuRegisterRanges[Index].End)) {
+ return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
+ }
+
+ Offset += mSmmCpuRegisterRanges[Index].Length;
+ }
+
+ return 0;
+}
+
+/**
+ Read a CPU Save State register on the target processor.
+
+ This function abstracts the differences that whether the CPU Save State register is in the
+ IA32 CPU Save State Map or X64 CPU Save State Map.
+
+ This function supports reading a CPU Save State register in SMBase relocation handler.
+
+ @param[in] CpuIndex Specifies the zero-based index of the CPU save state.
+ @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
+ @param[in] Width The number of bytes to read from the CPU save state.
+ @param[out] Buffer Upon return, this holds the CPU register value read from the save state.
+
+ @retval EFI_SUCCESS The register was read from Save State.
+ @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
+ @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+ReadSaveStateRegisterByIndex (
+ IN UINTN CpuIndex,
+ IN UINTN RegisterIndex,
+ IN UINTN Width,
+ OUT VOID *Buffer
+ )
+{
+ AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState;
+
+ // UINT32 SmmRevId;
+
+ if (RegisterIndex == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ CpuSaveState = gSmst->CpuSaveState[CpuIndex];
+ // SmmRevId = CpuSaveState->x86.SMMRevId;
+
+ if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
+ //
+ // If 32-bit mode width is zero, then the specified register can not be accessed
+ //
+ if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
+ //
+ if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Write return buffer
+ //
+ ASSERT (CpuSaveState != NULL);
+ CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);
+ } else {
+ //
+ // If 64-bit mode width is zero, then the specified register can not be accessed
+ //
+ if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
+ //
+ if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Write lower 32-bits of return buffer
+ //
+ CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN (4, Width));
+ if (Width >= 4) {
+ //
+ // Write upper 32-bits of return buffer
+ //
+ CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Read an SMM Save State register on the target processor. If this function
+ returns EFI_UNSUPPORTED, then the caller is responsible for reading the
+ SMM Save Sate register.
+
+ @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
+ value must be between 0 and the NumberOfCpus field in
+ the System Management System Table (SMST).
+ @param[in] Register The SMM Save State register to read.
+ @param[in] Width The number of bytes to read from the CPU save state.
+ @param[out] Buffer Upon return, this holds the CPU register value read
+ from the save state.
+
+ @retval EFI_SUCCESS The register was read from Save State.
+ @retval EFI_INVALID_PARAMTER Buffer is NULL.
+ @retval EFI_UNSUPPORTED This function does not support reading Register.
+
+**/
+EFI_STATUS
+EFIAPI
+InternalSmmCpuFeaturesReadSaveStateRegister (
+ IN UINTN CpuIndex,
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,
+ IN UINTN Width,
+ OUT VOID *Buffer
+ )
+{
+ UINT32 SmmRevId;
+ EFI_SMM_SAVE_STATE_IO_INFO *IoInfo;
+ AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState;
+ UINT8 DataWidth;
+
+ // Read CPU State
+ CpuSaveState = (AMD_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
+
+ // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
+ if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
+ // Only byte access is supported for this register
+ if (Width != 1) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *(UINT8 *)Buffer = mSmmSaveStateRegisterLma;
+
+ return EFI_SUCCESS;
+ }
+
+ // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
+
+ if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
+ //
+ // Get SMM Revision ID
+ //
+ ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId);
+
+ //
+ // See if the CPU supports the IOMisc register in the save state
+ //
+ if (SmmRevId < AMD_SMM_MIN_REV_ID_X64) {
+ return EFI_NOT_FOUND;
+ }
+
+ // Check if IO Restart Dword [IO Trap] is valid or not using bit 1.
+ if (!(CpuSaveState->x64.IO_DWord & 0x02u)) {
+ return EFI_NOT_FOUND;
+ }
+
+ // Zero the IoInfo structure that will be returned in Buffer
+ IoInfo = (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer;
+ ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO));
+
+ IoInfo->IoPort = (UINT16)(CpuSaveState->x64.IO_DWord >> 16u);
+
+ if (CpuSaveState->x64.IO_DWord & 0x10u) {
+ IoInfo->IoWidth = EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8;
+ DataWidth = 0x01u;
+ } else if (CpuSaveState->x64.IO_DWord & 0x20u) {
+ IoInfo->IoWidth = EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16;
+ DataWidth = 0x02u;
+ } else {
+ IoInfo->IoWidth = EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32;
+ DataWidth = 0x04u;
+ }
+
+ if (CpuSaveState->x64.IO_DWord & 0x01u) {
+ IoInfo->IoType = EFI_SMM_SAVE_STATE_IO_TYPE_INPUT;
+ } else {
+ IoInfo->IoType = EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT;
+ }
+
+ if ((IoInfo->IoType == EFI_SMM_SAVE_STATE_IO_TYPE_INPUT) || (IoInfo->IoType == EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT)) {
+ SmmCpuFeaturesReadSaveStateRegister (CpuIndex, EFI_SMM_SAVE_STATE_REGISTER_RAX, DataWidth, &IoInfo->IoData);
+ }
+
+ return EFI_SUCCESS;
+ }
+
+ // Convert Register to a register lookup table index
+ return ReadSaveStateRegisterByIndex (CpuIndex, GetRegisterIndex (Register), Width, Buffer);
+}
+
+/**
+ Writes an SMM Save State register on the target processor. If this function
+ returns EFI_UNSUPPORTED, then the caller is responsible for writing the
+ SMM Save Sate register.
+
+ @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
+ value must be between 0 and the NumberOfCpus field in
+ the System Management System Table (SMST).
+ @param[in] Register The SMM Save State register to write.
+ @param[in] Width The number of bytes to write to the CPU save state.
+ @param[in] Buffer Upon entry, this holds the new CPU register value.
+
+ @retval EFI_SUCCESS The register was written to Save State.
+ @retval EFI_INVALID_PARAMTER Buffer is NULL.
+ @retval EFI_UNSUPPORTED This function does not support writing Register.
+**/
+EFI_STATUS
+EFIAPI
+InternalSmmCpuFeaturesWriteSaveStateRegister (
+ IN UINTN CpuIndex,
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,
+ IN UINTN Width,
+ IN CONST VOID *Buffer
+ )
+{
+ UINTN RegisterIndex;
+ AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState;
+
+ //
+ // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
+ //
+ if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
+ //
+ if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // Convert Register to a register lookup table index
+ //
+ RegisterIndex = GetRegisterIndex (Register);
+ if (RegisterIndex == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ CpuSaveState = gSmst->CpuSaveState[CpuIndex];
+
+ //
+ // Do not write non-writable SaveState, because it will cause exception.
+ //
+ if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Check CPU mode
+ //
+ if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
+ //
+ // If 32-bit mode width is zero, then the specified register can not be accessed
+ //
+ if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
+ //
+ if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Write SMM State register
+ //
+ ASSERT (CpuSaveState != NULL);
+ CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
+ } else {
+ //
+ // If 64-bit mode width is zero, then the specified register can not be accessed
+ //
+ if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
+ //
+ if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Write lower 32-bits of SMM State register
+ //
+ CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
+ if (Width >= 4) {
+ //
+ // Write upper 32-bits of SMM State register
+ //
+ CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
--
2.25.1

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Re: [edk2-devel] [PATCH v1 5/5] UefiCpuPkg/AmdSmmCpuFeaturesLib: Handles S3 save state

[Attar, AbdulLateef (Abdul Lateef)]

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[AMD Official Use Only - General]

Hi Abner,
                I’ll drop this patch from the patch list. We will investigate and submit a separate patch for handling the S3 save stage.
Thanks
AbduL

From: abner.chang via groups.io <abner.chang=amd.com@groups.io>
Sent: 08 December 2022 11:17
To: Attar, AbdulLateef (Abdul Lateef) <AbdulLateef.Attar@amd.com>; devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH v1 5/5] UefiCpuPkg/AmdSmmCpuFeaturesLib: Handles S3 save state

Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.

Apart from the comment given to 4/5, I am afraid those extern variables in C file is not obey the section 5.4.2.1 extern in CCS.

Regards,
Abner


Abner
On Tue, Dec 6, 2022 at 09:23 PM, Abdul Lateef Attar wrote:
---
.../AmdSmmCpuFeaturesLib.inf | 1 +
.../SmmCpuFeaturesLib/Amd/SmramSaveState.h | 19 +++++++++++
.../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c | 32 +++++++++++++++++++
3 files changed, 52 insertions(+)

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
index 95eb31d16ead..7fd559e91ad8 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
@@ -27,6 +27,7 @@ [Sources]
[Packages]
MdePkg/MdePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
+ MdeModulePkg/MdeModulePkg.dec

[LibraryClasses]
BaseLib
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
index 290ebdbc9227..474a5dbd9765 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h
@@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DebugLib.h>
#include <Library/SmmServicesTableLib.h>
#include <Register/Amd/SmramSaveStateMap.h>
+#include <Guid/AcpiS3Context.h>

// EFER register LMA bit
#define LMA BIT10
@@ -106,4 +107,22 @@ InternalSmmCpuFeaturesWriteSaveStateRegister (
IN CONST VOID *Buffer
);

+/**
+ Initialize MP synchronization data.
+**/
+VOID
+EFIAPI
+InitializeMpSyncData (
+ VOID
+ );
+
+/**
+ Perform SMM MP sync Semaphores re-initialization in the S3 boot path.
+**/
+VOID
+EFIAPI
+SmmS3MpSemaphoreInit (
+ VOID
+ );
+
#endif
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
index 10bed4116397..b855573d9401 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c
@@ -14,6 +14,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// The mode of the CPU at the time an SMI occurs
extern UINT8 mSmmSaveStateRegisterLma;

+// SMM S3 resume state Ptr
+extern SMM_S3_RESUME_STATE *mSmmS3ResumeState;
+
/**
Read an SMM Save State register on the target processor. If this function
returns EFI_UNSUPPORTED, then the caller is responsible for reading the
@@ -441,4 +444,33 @@ SmmCpuFeaturesCompleteSmmReadyToLock (
VOID
)
{
+ if (mSmmS3ResumeState != NULL ) {
+ mSmmS3ResumeState->SmmS3ResumeEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)SmmS3MpSemaphoreInit;
+ }
+}
+
+/**
+ Perform SMM MP sync Semaphores re-initialization in the S3 boot path.
+**/
+VOID
+EFIAPI
+SmmS3MpSemaphoreInit (
+ VOID
+ )
+{
+ InitializeMpSyncData ();
+
+ DEBUG ((DEBUG_INFO, "SMM S3 Return CS = %x\n", mSmmS3ResumeState->ReturnCs));
+ DEBUG ((DEBUG_INFO, "SMM S3 Return Entry Point = %x\n", mSmmS3ResumeState->ReturnEntryPoint));
+ DEBUG ((DEBUG_INFO, "SMM S3 Return Context1 = %x\n", mSmmS3ResumeState->ReturnContext1));
+ DEBUG ((DEBUG_INFO, "SMM S3 Return Context2 = %x\n", mSmmS3ResumeState->ReturnContext2));
+ DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", mSmmS3ResumeState->ReturnStackPointer));
+
+ AsmDisablePaging64 (
+ mSmmS3ResumeState->ReturnCs,
+ (UINT32)mSmmS3ResumeState->ReturnEntryPoint,
+ (UINT32)mSmmS3ResumeState->ReturnContext1,
+ (UINT32)mSmmS3ResumeState->ReturnContext2,
+ (UINT32)mSmmS3ResumeState->ReturnStackPointer
+ );
}
--

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