From: "Brian J. Johnson via groups.io" <brian.johnson=hpe.com@groups.io>
To: <devel@edk2.groups.io>, <kraxel@redhat.com>,
<mitchell.augustin@canonical.com>
Subject: Re: [edk2-devel] [BUG] Extremely slow boot times with CPU and GPU passthrough and host phys-bits > 40
Date: Fri, 22 Nov 2024 11:38:26 -0600 [thread overview]
Message-ID: <24c2f7dd-1042-4109-b761-3f013e95b503@hpe.com> (raw)
In-Reply-To: <sqpqbftklcx24l4sjngsb2tgan6k4a2mnhpd3t2iz6pdqjzy57@o3mbmyjwgqkb>
On 11/22/24 04:35, Gerd Hoffmann via groups.io wrote:
> On Thu, Nov 21, 2024 at 04:23:32PM -0800, mitchell.augustin via groups.io wrote:
>> Thanks for the suggestions, Gerd.
>>
>>> '-global ICH9-LPC.acpi-pci-hotplug-with-bridge-support=off'
>>
>> Unfortunatly, this did not result in any change in boot time.
>>
>>> '-cpu $name,host-phys-bits=on,host-phys-bits-limit=$bits'
>>
>> -cpu host,host-phys-bits=on,host-phys-bits-limit=40 does result in the desired very fast boot time, but I get errors when I try to load the GPU driver:
>>
>> NVRM: BAR0 is 0M @ 0x0 (PCI:0000:06:00.0)
>
> OVMF scales the pcie root port bridge windows with the address space.
>
> So you can try increase host-phys-bits-limit. Values between 40 and 46
> should have an effect.
>
> The opt/ovmf/X-PciMmio64Mb setting already mentioned elsewhere in this
> thread should also work with the dynamic mmio window.
>
>> * *I ask this because I notice that when I disable host passthrough *(which works with my GPUs and results in a fast boot if `pci=realloc pci=nocrs` are used)* , my VM shows "Address sizes: 40 bits physical, 48 bits virtual", but when I use host passthrough and only override the physbits (which fails as described above), my VM shows "Address sizes: 40 bits physical, 57 bits virtual". (so I'm wondering if that could be a factor here.)*
>
> It's 5-level paging support, and the qemu option name for that is la57
> (-cpu $name,la57={on|off})
>
> take care,
> Gerd
I'm not familiar with passing through devices, but I'll mention that
900+ GB of memory will take 40 PA bits just for that, with little room
left above the RAM for PCI BARs in MMIOH. So I wouldn't be surprised if
you need more PA bits, which would push you into 5-level paging.
Gerd's suggestion to check if the MTRRs and page attributes are getting
set properly is a good one. That has caused this type of problem in the
past.
--
Brian J. Johnson
Hewlett Packard Enterprise
brian.johnson@hpe.com
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next prev parent reply other threads:[~2024-11-22 17:38 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-14 16:46 [edk2-devel] [BUG] Extremely slow boot times with CPU and GPU passthrough and host phys-bits > 40 mitchell.augustin via groups.io
2024-11-18 21:14 ` xpahos via groups.io
2024-11-19 22:25 ` mitchell.augustin via groups.io
2024-11-20 9:35 ` xpahos via groups.io
2024-11-20 11:26 ` Gerd Hoffmann via groups.io
2024-11-20 15:20 ` mitchell.augustin via groups.io
2024-11-20 20:00 ` mitchell.augustin via groups.io
2024-11-21 12:32 ` Gerd Hoffmann via groups.io
2024-11-22 0:23 ` mitchell.augustin via groups.io
2024-11-22 10:35 ` Gerd Hoffmann via groups.io
2024-11-22 17:38 ` Brian J. Johnson via groups.io [this message]
2024-11-22 22:32 ` mitchell.augustin via groups.io
2024-11-24 2:05 ` mitchell.augustin via groups.io
2024-11-25 11:47 ` Gerd Hoffmann via groups.io
2024-11-25 19:58 ` mitchell.augustin via groups.io
2024-11-26 8:09 ` Gerd Hoffmann via groups.io
2024-11-26 22:27 ` mitchell.augustin via groups.io
2024-12-04 14:56 ` mitchell.augustin via groups.io
2024-11-25 11:18 ` Gerd Hoffmann via groups.io
2024-11-18 21:32 ` Ard Biesheuvel via groups.io
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