From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web11.195354.1673960144968972434 for ; Tue, 17 Jan 2023 04:55:45 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@quicinc.com header.s=qcppdkim1 header.b=Rfwpx/oJ; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 205.220.180.131, mailfrom: quic_rcran@quicinc.com) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30HBcrTn001374; Tue, 17 Jan 2023 12:55:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=hLFcW0I2TTfqUkc35g+2vJXF8QmyoCHFRahUHo2E7Qw=; b=Rfwpx/oJJaxW1/q0i7+tIfZckKyxQWizcLdHC+Y5Rk9mJ0vza/p94L42/dJeL3VFcxX6 FqT/tMi84fghCVB4IQQOh9TCYFSk7zNR/0LvrAxd/u2X5s6X4Zn2QKKqfInjQYbq5Uyl v1SmJpr/fw+AFZLjUrPYXlIVF3oJq5j/vabqS4268BSDA99Tyos0GSbEbsuCPn6Y47Pv E2at8Vy+gMsEytDkUqmip/HzfjdEI5m4JdCOfxGrmG6JSMe0fN0UQ1WYZTGT4m6SyTAT LqHymg+i2y2Re2cJYZB50YDaM7mkFETTMyO4ENP/sNEzMhSu3LNQkOtS17wRwfpsU5zS WA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3n5nkq8pg7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Jan 2023 12:55:41 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30HCteUo024779 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Jan 2023 12:55:40 GMT Received: from [10.110.4.184] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 17 Jan 2023 04:55:39 -0800 Message-ID: <25ee195f-85ee-d783-7e5c-f0da8b9972b4@quicinc.com> Date: Tue, 17 Jan 2023 05:55:39 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [edk2-devel] [edk2-platforms][PATCH 1/1] AmpereAltraPkg: Update ArmPlatformLib to work with changed ARM_CORE_INFO To: Nhi Pham , , CC: , , , Tinh Nguyen References: <20230113042126.3107135-1-nhi@os.amperecomputing.com> <7d401f29-56d9-d754-88a6-684ce329a727@quicinc.com> From: "Rebecca Cran" In-Reply-To: X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rlkbWRZTkMmHpgKIU-Ex42SAjySCW3nO X-Proofpoint-ORIG-GUID: rlkbWRZTkMmHpgKIU-Ex42SAjySCW3nO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.923,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-17_05,2023-01-17_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 impostorscore=0 mlxscore=0 adultscore=0 mlxlogscore=596 bulkscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 phishscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301170106 X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-0031df01.pphosted.com id 30HBcrTn001374 Content-Language: en-US Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: quoted-printable I was under the impression that this is becoming a more standard format? For example, the Neoverse N2 has AFF0 always 0 (it's not hyperthreaded),=20 it puts the core ID in AFF1, the cluster ID in AFF2, but since it only=20 has a single socket AFF3 is always 0. This differs from older cores=20 where the core ID was in AFF0 and the cluster ID in AFF1. https://developer.arm.com/documentation/102099/0000/AArch64-registers/AAr= ch64-identification-registers/MPIDR-EL1--Multiprocessor-Affinity-Register Am I mistaken? --=20 Rebecca Cran On 1/17/23 02:53, Nhi Pham wrote: > Hi Rebecca, >=20 > That's Ampere Altra Family specific MPIDR encoding. So, we could not=20 > leverage the definitions in the ArmPkg/Include/Library/ArmLib.h. >=20 > -Nhi >=20 > On 1/13/2023 9:40 PM, Rebecca Cran wrote: >> On 1/12/23 21:21, Nhi Pham via groups.io wrote: >> >>> +// >>> +// MPIDR manipulation >>> +// >>> +#define AC01_GET_MPIDR(SocketId, ClusterId, CoreId) \ >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (((SocketId) = << 32) | ((ClusterId) << 16) | ((CoreId) << 8)) >>> +#define AC01_GET_SOCKET_ID(Mpidr)=C2=A0 (((Mpidr) & ARM_CORE_AFF3) >= > 32) >>> +#define AC01_GET_CLUSTER_ID(Mpidr) (((Mpidr) & ARM_CORE_AFF2) >> 16) >>> +#define AC01_GET_CORE_ID(Mpidr)=C2=A0=C2=A0=C2=A0 (((Mpidr) & ARM_CO= RE_AFF1) >> 8) >>> + >> >> Ideally, this should go in ArmPkg/Include/Library/ArmLib.h, but I'm=20 >> not sure how we should handle the older format where the the core was=20 >> in the first 8 bits. >>