From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web09.2024.1652346773361127443 for ; Thu, 12 May 2022 02:12:53 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=YopTgxBA; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: chinni.b.duggapu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652346773; x=1683882773; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=g4RAN6gfH1jflEXr7YDztPYu6z1wYyablS96S6mR7Rw=; b=YopTgxBAUfaEtfeboUQP99kpYUVN32OjIHYaTKL0yeYtIZxpD/VSFdU1 GgX6qwiQQ7ctLywtqAElJFQZgSApg4oN8y8q/3BT/spb/zUyadpGe9PNR EmYYv+0eS/LJShOKdqcIJ80I7G35GQTrYSMWl3XHpnzj0yeKRjIFq28cI AaZOwWelfK2/gPglWfGzdXd+q8XePUJ5RS7/zGP/w1WkyGMIZX0pGK7iZ 798WKwPDJmXBUXbGbABg309M805ZmCWouOG4LpwNNZR2FmLzyNFc7qRY/ fAH+hu+PLaaEdK/p+wif1+MOhJNj6fA3V5x7FjaBlLzqFo4JHMJX1yERm w==; X-IronPort-AV: E=McAfee;i="6400,9594,10344"; a="330548234" X-IronPort-AV: E=Sophos;i="5.91,219,1647327600"; d="scan'208";a="330548234" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2022 02:12:52 -0700 X-IronPort-AV: E=Sophos;i="5.91,219,1647327600"; d="scan'208";a="542693381" Received: from cbduggap-mobl1.gar.corp.intel.com ([10.215.202.133]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2022 02:12:51 -0700 From: "cbduggap" To: devel@edk2.groups.io Subject: [PATCH v2] FSP_TEMP_RAM_INIT API call must follow X64 Calling Convention Date: Thu, 12 May 2022 14:42:33 +0530 Message-Id: <269758c0ceee3f742ab7d178112229be447d30d9.1652346714.git.chinni.b.duggapu@intel.com> X-Mailer: git-send-email 2.36.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This API accept one parameter using RCX and this is consumed in mutiple sub functions. Signed-off-by: cbduggap --- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 21 ++++++++------ .../Include/SaveRestoreSseAvxNasm.inc | 28 +++++++++++++++++++ 2 files changed, 40 insertions(+), 9 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index a9f5f28ed7..cddc41125e 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault): =0D cmp rsp, 0=0D jz ParamError=0D - mov eax, dword [rsp + 8] ; Parameter pointer=0D - cmp eax, 0=0D + cmp ecx, 0=0D jz ParamError=0D - mov esp, eax=0D + mov esp, ecx=0D =0D ; skip loading Microcode if the MicrocodeCodeSize is zero=0D ; and report error if size is less than 2k=0D @@ -321,8 +320,7 @@ ASM_PFX(EstablishStackFsp): ;=0D ; Save parameter pointer in rdx=0D ;=0D - mov rdx, qword [rsp + 8]=0D -=0D + mov rdx, rcx=0D ;=0D ; Enable FSP STACK=0D ;=0D @@ -420,7 +418,10 @@ ASM_PFX(TempRamInitApi): ;=0D ENABLE_SSE=0D ENABLE_AVX=0D -=0D + ;=0D + ; Save Input Parameter in YMM10=0D + ;=0D + SAVE_RCX=0D ;=0D ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6=0D ;=0D @@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi): ;=0D ; Check Parameter=0D ;=0D - mov rax, qword [rsp + 8]=0D - cmp rax, 0=0D - mov rax, 08000000000000002h=0D + cmp rcx, 0=0D + mov rcx, 08000000000000002h=0D jz TempRamInitExit=0D =0D ;=0D @@ -456,17 +456,20 @@ ASM_PFX(TempRamInitApi): =0D ; Load microcode=0D LOAD_RSP=0D + LOAD_RCX=0D CALL_YMM ASM_PFX(LoadMicrocodeDefault)=0D SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT= 0 in YMM9 (upper 128bits).=0D ; @note If return value rax is not 0, microcode did not load, but contin= ue and attempt to boot.=0D =0D ; Call Sec CAR Init=0D LOAD_RSP=0D + LOAD_RCX=0D CALL_YMM ASM_PFX(SecCarInit)=0D cmp rax, 0=0D jnz TempRamInitExit=0D =0D LOAD_RSP=0D + LOAD_RCX=0D CALL_YMM ASM_PFX(EstablishStackFsp)=0D cmp rax, 0=0D jnz TempRamInitExit=0D diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/= Include/SaveRestoreSseAvxNasm.inc index e8bd91669d..38c807a311 100644 --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc @@ -177,6 +177,30 @@ LXMMN xmm5, %1, 1=0D %endmacro=0D =0D +;=0D +; Upper half of YMM10 to save/restore RCX=0D +;=0D +;=0D +; Save RCX to YMM10[128:191]=0D +; Modified: XMM5 and YMM10=0D +;=0D +=0D +%macro SAVE_RCX 0=0D + LYMMN ymm10, xmm5, 1=0D + SXMMN xmm5, 0, rcx=0D + SYMMN ymm10, 1, xmm5=0D + %endmacro=0D +=0D +;=0D +; Restore RCX from YMM10[128:191]=0D +; Modified: XMM5 and RCX=0D +;=0D +=0D +%macro LOAD_RCX 0=0D + LYMMN ymm10, xmm5, 1=0D + movq rcx, xmm5=0D + %endmacro=0D +=0D ;=0D ; YMM7[128:191] for calling stack=0D ; arg 1:Entry=0D @@ -231,6 +255,7 @@ NextAddress: ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to t= est=0D ; whether the processor supports SSE instruction.=0D ;=0D + mov r10, rcx=0D mov rax, 1=0D cpuid=0D bt rdx, 25=0D @@ -241,6 +266,7 @@ NextAddress: ;=0D bt ecx, 19=0D jnc SseError=0D + mov rcx, r10=0D =0D ;=0D ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)=0D @@ -258,6 +284,7 @@ NextAddress: %endmacro=0D =0D %macro ENABLE_AVX 0=0D + mov r10, rcx=0D mov eax, 1=0D cpuid=0D and ecx, 10000000h=0D @@ -280,5 +307,6 @@ EnableAvx: xgetbv ; result in edx:eax=0D or eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable = SSE state and AVX state=0D xsetbv=0D + mov rcx, r10=0D %endmacro=0D =0D --=20 2.36.0.windows.1