From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.132.183.28, mailfrom: lersek@redhat.com) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Mon, 12 Aug 2019 07:13:48 -0700 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 0C985306E187; Mon, 12 Aug 2019 14:13:48 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-247.ams2.redhat.com [10.36.116.247]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2FAFC69FAE; Mon, 12 Aug 2019 14:13:46 +0000 (UTC) Subject: Re: [Patch v2 3/6] UefiCpuPkg/PiSmmCpuDxeSmm: Supports test then write new value logic. To: Eric Dong , devel@edk2.groups.io Cc: Ray Ni References: <20190812103152.35164-1-eric.dong@intel.com> <20190812103152.35164-4-eric.dong@intel.com> From: "Laszlo Ersek" Message-ID: <26c00f3a-dbf4-0f33-0a36-7c9700516f77@redhat.com> Date: Mon, 12 Aug 2019 16:13:46 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20190812103152.35164-4-eric.dong@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.47]); Mon, 12 Aug 2019 14:13:48 +0000 (UTC) Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 08/12/19 12:31, Eric Dong wrote: > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040 > > Supports new logic which test current value before write new value. > Only write new value when current value not same as new value. > > Signed-off-by: Eric Dong > Cc: Ray Ni > Cc: Laszlo Ersek > --- > UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c > index b20992d5ab..61541838e8 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c > @@ -241,6 +241,7 @@ ProgramProcessorRegister ( > UINTN ValidThreadCount; > UINT32 *ValidCoreCountPerPackage; > EFI_STATUS Status; > + UINT64 CurrentValue; > > // > // Traverse Register Table of this logical processor > @@ -263,6 +264,16 @@ ProgramProcessorRegister ( > if (EFI_ERROR (Status)) { > continue; > } > + if (RegisterTableEntry->TestThenWrite) { > + CurrentValue = BitFieldRead64 ( > + Value, > + RegisterTableEntry->ValidBitStart, > + RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1 > + ); > + if (CurrentValue == RegisterTableEntry->Value) { > + continue; > + } > + } > Value = (UINTN) BitFieldWrite64 ( > Value, > RegisterTableEntry->ValidBitStart, > @@ -275,6 +286,24 @@ ProgramProcessorRegister ( > // The specified register is Model Specific Register > // > case Msr: > + if (RegisterTableEntry->TestThenWrite) { > + Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index); > + if (RegisterTableEntry->ValidBitLength >= 64) { > + if (Value == RegisterTableEntry->Value) { > + continue; > + } > + } else { > + CurrentValue = BitFieldRead64 ( > + Value, > + RegisterTableEntry->ValidBitStart, > + RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1 > + ); > + if (CurrentValue == RegisterTableEntry->Value) { > + continue; > + } > + } > + } > + > // > // If this function is called to restore register setting after INIT signal, > // there is no need to restore MSRs in register table. > I assume that "RegisterTableEntry->Value" has all bits clear that fall outside of the bitmask defined by ValidBitStart and ValidBitLength. With that assumption: Reviewed-by: Laszlo Ersek Thanks Laszlo