From mboxrd@z Thu Jan 1 00:00:00 1970 Subject: Re: [edk2-devel] UefiPayloadPkg: assert error in PciHostBridgeDxe To: Andrew Fish ,devel@edk2.groups.io From: "King Sumo" X-Originating-Location: BR (165.225.214.127) X-Originating-Platform: Windows Chrome 83 User-Agent: GROUPS.IO Web Poster MIME-Version: 1.0 Date: Mon, 06 Jul 2020 12:58:07 -0700 References: <8D20B013-24B7-4447-8B9D-469016992898@apple.com> In-Reply-To: <8D20B013-24B7-4447-8B9D-469016992898@apple.com> Message-ID: <27945.1594065487881381394@groups.io> Content-Type: multipart/alternative; boundary="LWdjt1bACOVlHcD6tcUO" --LWdjt1bACOVlHcD6tcUO Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Fri, Jul 3, 2020 at 11:30 AM, Andrew Fish wrote: >=20 > At the same time, the platform's PciHostBridgeLib instance reported a > root bridge with an MMIO aperture at [D4000000, FE100000), with > capabilities 1. >=20 > This is a conflict. The capabilities don't even matter (we don't even > check whether the existent GCD descriptor's capabilities are a superset > of the aperture's), because the aperture requires GCD memory type > EfiGcdMemoryTypeMemoryMappedIo, but the GCD descriptor has type > EfiGcdMemoryTypeReserved. >=20 > In brief, the failure is due to the platform reporting a PCI root bridge > aperture such that it overlaps an area that is already listed as > "reserved" in the GCD memory space map. So this is a platform bug; > either in the "PciHostBridgeLib" instance, or in the module that > populates the GCD memory space map. Thanks Andrew and Laszlo! The map (E0000000, F0000000) is the PCIE Base Address, maybe BlSupportPeim= of UefiPayloadPkg have added this in the GCD - I'm not sure if this is cor= rect / normal. Looks like BlSupportPeim is adding to GCD several memory reg= ions during the initialization. Anyway, the PCIe root bridge MMIO aperture (D4000000, FE100000) looks pret= ty weird, I'll double check if coreboot is configuring the root port correc= tly. Thanks, Sumo --LWdjt1bACOVlHcD6tcUO Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Fri, Jul 3, 2020 at 11:30 AM, Andrew Fish wrote:
At the same time, the platform's PciHostBridgeLib instance reported a
= root bridge with an MMIO aperture at [D4000000, FE100000), with
capabilit= ies 1.

This is a conflict. The capabilities don't even matter (we d= on't even
check whether the existent GCD descriptor's capabilities are a = superset
of the aperture's), because the aperture requires GCD memory typ= e
EfiGcdMemoryTypeMemoryMappedIo, but the GCD descriptor has type<= br />EfiGc= dMemoryTypeReserved.

In brief, the failure is due to the platform r= eporting a PCI root bridge
aperture such that it overlaps an area that is= already listed as
"reserved" in the GCD memory space map. So this is a p= latform bug;
either in the "PciHostBridgeLib" instance, or in the module = that
populates the GCD memory space map.
Thanks Andrew and Laszlo!
 
The map (E0000000, F0000000) is the PCIE Base Address, maybe BlSuppor= tPeim of UefiPayloadPkg have added this in the GCD - I'm not sure if this i= s correct / normal. Looks like BlSupportPeim is adding to GCD several memor= y regions during the initialization.
Anyway, the PCIe root bridge MMIO aperture (D4000000, FE100000) looks= pretty weird, I'll double check if coreboot is configuring the root port c= orrectly.

Thanks,
Sumo
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