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Wed, 20 May 2020 16:07:11 +0000 Subject: Re: [edk2-devel] [PATCH v2 0/3] New RISC-V Patches - Why in edk2-platforms From: "Daniel Schaefer" To: Leif Lindholm , CC: Abner Chang , Gilbert Chen , Michael D Kinney , , References: <20200515133937.29909-1-daniel.schaefer@hpe.com> <20200520114336.GK1923@vanye> <6f0d755e-4e69-5080-ef69-caf7259ce9ee@hpe.com> Message-ID: <27d3bf55-eb2e-75e1-e5fa-17af59e105aa@hpe.com> Date: Wed, 20 May 2020 18:07:04 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 In-Reply-To: <6f0d755e-4e69-5080-ef69-caf7259ce9ee@hpe.com> X-ClientProxiedBy: AM4PR0701CA0019.eurprd07.prod.outlook.com (2603:10a6:200:42::29) To CS1PR8401MB0726.NAMPRD84.PROD.OUTLOOK.COM (2a01:111:e400:750c::23) X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [192.168.178.165] (93.215.202.37) by AM4PR0701CA0019.eurprd07.prod.outlook.com (2603:10a6:200:42::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3045.7 via Frontend Transport; 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charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: quoted-printable please reply here, fixed Mike's email address, sorry... On 5/20/20 6:03 PM, Daniel Schaefer wrote: > On 5/20/20 1:43 PM, Leif Lindholm wrote: >> On Fri, May 15, 2020 at 15:39:34 +0200, Daniel Schaefer wrote: >>> Previously we had two packages just for RISC-V on our edk2 branch: >>> =C2=A0=C2=A0 RiscVPkg and RiscVPlatformPkg >>> They are now under >>> =C2=A0=C2=A0 Platform/RISC-V/PlatformPkg and Silicon/RISC-V/Processor= Pkg >>> in edk2-platforms. >> >> Understood. I took my eye off the ball there for a while, but I'm a >> bit confused as to why RiscVPkg isn't going into EDK2. That is very >> counterintuitive. And clearly it will need revisiting if we are to add >> first-class CI checks like those we do with OvmfPkg/ArmVirtPkg. >=20 > Yes, I understand your concern. Personally I'd like it also to be in=20 > EDK2 straight away, however Mike, Bret and Sean have raised valid conce= rns: >=20 > 1. RISC-V is very new and potentially unstable - it's quicker to make=20 > changes in edk2-platforms. >=20 > 2. If we define new interfaces and libraries in edk2, we can't remove=20 > them easily because it would be a backwards-incompatible change.=20 > edk2-platforms isn't quite as strict. >=20 > 3. Long-term, I think many agree, we should aim to move much of the=20 > RISC-V code into UefiCpuPkg and OvmfPkg. Mike mentioned that would need= =20 > coordination with ARM maintainers because it might make sense to move=20 > their code there as well. >=20 > Maybe Mike, Bret or Sean would like to provide some more comments? >=20 >> I *did* have some outstanding comments specifically with regards to >> large amounts of code duplication between the SMBIOS implementation of >> some closely related RISC-V platforms. That now needs to be revisited. >=20 > The SMBIOS code hasn't changed. It has moved to > =C2=A0 Silicon/SiFive/{E51,U54,U54MCCoreplex}/Library/PeiCoreInfoHobLi= b > You're referring to this library, right? >=20 > They build the SMBIOS entries for a particular processor. Yes, the=20 > values do have a lot of overlap but these files are like configuration=20 > files. They don't do much, they only set the values of the properties. >=20 > Currently it is not possible to let the UEFI firmware get this=20 > information from the hardware at runtime, especially now, since we're=20 > running in S-Mode. > To allow that, we created a RISC-V working group to be able to retrieve= =20 > all of this information dynamically from the processor (among other=20 > goals). Then the vendor will not have to modify these files and hardcod= e=20 > the values anymore. Which enables us to create a single library for all= =20 > processors. > See: https://github.com/riscv/configuration-structure >=20 > I hope I described everything properly, please correct me otherwise, Ab= ner. >=20 >> >>> In the previous version of this patchseries I forgot to attach the=20 >>> biggest new >>> commit, which adds RiscVEdk2SbiLib. It wraps the ecall interface for=20 >>> calling >>> SBI in a C API and lets PEI and DXE call SBI interfaces. Because we=20 >>> need more >>> M-Mode capabilities in PEI and DXE than SBI gives us, we register=20 >>> another SBI >>> extension, that gives us access to the mscratch register. >> >> Without looking at it yet, it sounds like that may resolve the only >> remaining major issue I had with RiscVPkg. >> >>> I hope now it makes more sense. >> >> It is more clear, as per above I am not sure it makes more sense :) >> Thanks! >=20 > Your concerns are very valid, however due to the mentioned trade-offs i= t=20 > might not make sense to address them. >=20 > - Daniel