From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.8480.1648454962517853012 for ; Mon, 28 Mar 2022 01:09:43 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=D8gEv5f6; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: min.m.xu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648454983; x=1679990983; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZGKowqbK3ZfUEwJnAYnfDDiBBLskCPqrfE7x7Kw7rhI=; b=D8gEv5f6ZAcmA8BAlqeYjkdFbPKWNlf3RjONmtDlFiutDTBEBVDR43dY bkhLgUa5uMA56KPOuAPqbjCQI6uGZpvF4/X7IASkcDn6RfN27VVhppwX8 Nr137whFPLyhhk8lnDM1W/BbJtQ7HfAns6UM9yR8YGSWSE8OkZ4Wpu4I4 H2Xc7qsxrWqb/XuE09uPJnlwIUcNh2hYjDXj4rJbnXwCMTIJ/fZ3nj3w9 pslVDp82OvomYezDQpAwzvxQ62lP+DLbd1Rkfzzto7mU7xfKEgrOR8sGg 0pw9MeO3BhtQNYCVy1TOMQKr2XxoVOu9K4v8s5ilyg3R0xjrgzRn6NCaL w==; X-IronPort-AV: E=McAfee;i="6200,9189,10299"; a="257770921" X-IronPort-AV: E=Sophos;i="5.90,216,1643702400"; d="scan'208";a="257770921" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Mar 2022 01:09:38 -0700 X-IronPort-AV: E=Sophos;i="5.90,216,1643702400"; d="scan'208";a="563427302" Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.167]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Mar 2022 01:09:35 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [PATCH V11 18/47] OvmfPkg/PlatformInitLib: Add hob functions Date: Mon, 28 Mar 2022 16:07:57 +0800 Message-Id: <287146caf64347370cd9c1b21815c89eb7ed641e.1648454441.git.min.m.xu@intel.com> X-Mailer: git-send-email 2.29.2.windows.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 In this patch of PlatformInitLib, below hob functions are introduced: - PlatformAddIoMemoryBaseSizeHob - PlatformAddIoMemoryRangeHob - PlatformAddMemoryBaseSizeHob - PlatformAddMemoryRangeHob - PlatformAddReservedMemoryBaseSizeHob They correspond the below functions in OvmfPkg/PlatformPei: - AddIoMemoryBaseSizeHob - AddIoMemoryRangeHob - AddMemoryBaseSizeHob - AddMemoryRangeHob - AddReservedMemoryBaseSizeHob After above hob functions are introduced in PlatformInitLib, OvmfPkg/PlatformPei is refactored with this library. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/Include/Library/PlatformInitLib.h | 36 ++++++ OvmfPkg/Library/PlatformInitLib/Platform.c | 106 ++++++++++++++++++ .../PlatformInitLib/PlatformInitLib.inf | 2 + OvmfPkg/PlatformPei/MemDetect.c | 20 ++-- OvmfPkg/PlatformPei/Platform.c | 101 ++--------------- OvmfPkg/PlatformPei/Platform.h | 31 ----- 6 files changed, 165 insertions(+), 131 deletions(-) create mode 100644 OvmfPkg/Library/PlatformInitLib/Platform.c diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Library/PlatformInitLib.h index 2ebac5ccb013..9b99d4c1f514 100644 --- a/OvmfPkg/Include/Library/PlatformInitLib.h +++ b/OvmfPkg/Include/Library/PlatformInitLib.h @@ -96,4 +96,40 @@ PlatformDebugDumpCmos ( VOID ); +VOID +EFIAPI +PlatformAddIoMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ); + +VOID +EFIAPI +PlatformAddIoMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +EFIAPI +PlatformAddMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ); + +VOID +EFIAPI +PlatformAddMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +EFIAPI +PlatformAddReservedMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize, + IN BOOLEAN Cacheable + ); + #endif // PLATFORM_INIT_LIB_H_ diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/PlatformInitLib/Platform.c new file mode 100644 index 000000000000..e41f230ff563 --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/Platform.c @@ -0,0 +1,106 @@ +/**@file + + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2011, Andrei Warkentin + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include + +VOID +EFIAPI +PlatformAddIoMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +EFIAPI +PlatformAddReservedMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize, + IN BOOLEAN Cacheable + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_RESERVED, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + (Cacheable ? + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE : + 0 + ) | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +EFIAPI +PlatformAddIoMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + PlatformAddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + +VOID +EFIAPI +PlatformAddMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +EFIAPI +PlatformAddMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + PlatformAddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf index 4ea2da86274f..21813458cb59 100644 --- a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf +++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf @@ -24,6 +24,7 @@ [Sources] Cmos.c + Platform.c [Packages] MdeModulePkg/MdeModulePkg.dec @@ -34,3 +35,4 @@ BaseLib DebugLib IoLib + HobLib diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c index 9c5bf240e3ba..e5e105f377dd 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -275,10 +275,10 @@ ScanOrAdd64BitE820Ram ( End = (E820Entry.BaseAddr + E820Entry.Length) & ~(UINT64)EFI_PAGE_MASK; if (Base < End) { - AddMemoryRangeHob (Base, End); + PlatformAddMemoryRangeHob (Base, End); DEBUG (( DEBUG_VERBOSE, - "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n", + "%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n", __FUNCTION__, Base, End @@ -816,8 +816,8 @@ QemuInitializeRamBelow1gb ( ) { if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) { - AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE); - AddReservedMemoryBaseSizeHob ( + PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE); + PlatformAddReservedMemoryBaseSizeHob ( SMM_DEFAULT_SMBASE, MCH_DEFAULT_SMBASE_SIZE, TRUE /* Cacheable */ @@ -826,12 +826,12 @@ QemuInitializeRamBelow1gb ( SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128KB, "end of SMRAM at default SMBASE ends at, or exceeds, 640KB" ); - AddMemoryRangeHob ( + PlatformAddMemoryRangeHob ( SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE, BASE_512KB + BASE_128KB ); } else { - AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); + PlatformAddMemoryRangeHob (0, BASE_512KB + BASE_128KB); } } @@ -889,14 +889,14 @@ QemuInitializeRam ( UINT32 TsegSize; TsegSize = mQ35TsegMbytes * SIZE_1MB; - AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); - AddReservedMemoryBaseSizeHob ( + PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); + PlatformAddReservedMemoryBaseSizeHob ( LowerMemorySize - TsegSize, TsegSize, TRUE ); } else { - AddMemoryRangeHob (BASE_1MB, LowerMemorySize); + PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize); } // @@ -908,7 +908,7 @@ QemuInitializeRam ( if (EFI_ERROR (Status)) { UpperMemorySize = GetSystemMemorySizeAbove4gb (); if (UpperMemorySize != 0) { - AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); + PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); } } } diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 594891786440..62480c3c40e5 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -57,85 +57,6 @@ BOOLEAN mS3Supported = FALSE; UINT32 mMaxCpuCount; -VOID -AddIoMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_MEMORY_MAPPED_IO, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddReservedMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize, - BOOLEAN Cacheable - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_MEMORY_RESERVED, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - (Cacheable ? - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE : - 0 - ) | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddIoMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ) -{ - AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); -} - -VOID -AddMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_SYSTEM_MEMORY, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ) -{ - AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); -} - VOID MemMapInitialization ( VOID @@ -155,12 +76,12 @@ MemMapInitialization ( // // Video memory + Legacy BIOS region // - AddIoMemoryRangeHob (0x0A0000, BASE_1MB); + PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB); if (mHostBridgeDevId == 0xffff /* microvm */) { - AddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); - AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */ - AddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */ + PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); + PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */ + PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */ return; } @@ -194,20 +115,20 @@ MemMapInitialization ( // 0xFEE00000 LAPIC 1 MB // PciSize = 0xFC000000 - PciBase; - AddIoMemoryBaseSizeHob (PciBase, PciSize); + PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize); PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase); ASSERT_RETURN_ERROR (PcdStatus); PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize); ASSERT_RETURN_ERROR (PcdStatus); - AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); - AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); + PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); + PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { - AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); + PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); // // Note: there should be an // - // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB); + // PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB); // // call below, just like the one above for RCBA. However, Linux insists // that the MMCONFIG area be marked in the E820 or UEFI memory map as @@ -225,7 +146,7 @@ MemMapInitialization ( // is most definitely not RAM; so, as an exception, cover it with // uncacheable reserved memory right here. // - AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); + PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); BuildMemoryAllocationHob ( PciExBarBase, SIZE_256MB, @@ -233,7 +154,7 @@ MemMapInitialization ( ); } - AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB); + PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB); // // On Q35, the IO Port space is available for PCI resource allocations from diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 24e4da4e1d93..f193ff736549 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -11,37 +11,6 @@ #include -VOID -AddIoMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ); - -VOID -AddIoMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ); - -VOID -AddMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ); - -VOID -AddMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ); - -VOID -AddReservedMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize, - BOOLEAN Cacheable - ); - VOID AddressWidthInitialization ( VOID -- 2.29.2.windows.2