From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from NAM04-SN1-obe.outbound.protection.outlook.com (NAM04-SN1-obe.outbound.protection.outlook.com [40.107.70.76]) by mx.groups.io with SMTP id smtpd.web11.58095.1595863704120569322 for ; Mon, 27 Jul 2020 08:28:24 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@amdcloud.onmicrosoft.com header.s=selector2-amdcloud-onmicrosoft-com header.b=XxEGifQ5; spf=none, err=SPF record not found (domain: amd.com, ip: 40.107.70.76, mailfrom: thomas.lendacky@amd.com) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fJlCwkrVeEf2J2Ub6D59Ba0qMQCsRrxFH/0PtwTgVgNurwRjnO4pXCb/B1gJrCPnSA1KCvZ3ulndVW2HAhG2G+FZKtXECtCIXaihVGRMD10+rGqYzT6Qpp+/kGMddKUGYEp5HjFQtHsqB+FboVqttLXILinAWLCA3pq5b+OEO9ctRWekkdUh3i6XXDp7CaZFGieAsuY3hPhfUwbI5jNm9FiRlNus/vE1rjCxukGF2MJ/yH2GS4SxD3Kb3XosVVuZtH2Sx51jEXKIt0nWsSREm3a9EdovSD+v8sXVyFIBnM3tWOHdGQpXl4G9T+XTrmGE1FFftusdu6qEFxeL1CqU1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YLiynLfWPYBI3p6aciiysyOQa+ljPEYq8UZEiba60Qk=; b=MW3uyHPksvOczaAPnaUthB0E7Qdd5sHs0Hw2ZH2isp0+21Kfx+znhXpajwsZVXaoU8OxdbCiLQBTYtr7dBx/u4llGBah5BatKFE9BPuVNPyo0+MnMLAVCfspdIS0L3TtWo2GPu0uQ87fD0s8xiC+D8648hVk590qJSV/Rac5lCnmrMl01egwYFbjkQ8Qpm+MEtwGmE/x/VarexRraYU0Wg9TyaR1qCcPE965YgatrgrchUpLwrpEGDnTWzpZnAR4rXmzYXYYnRzfDJpIyIaAEkHGsZuD5zaxrQpbtQZpeb990j3l4mOYXHCiU/wZn2CR0PcEHaR46Yb6u8TthBFeNQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YLiynLfWPYBI3p6aciiysyOQa+ljPEYq8UZEiba60Qk=; b=XxEGifQ55Vs6bLA4UiU6TZ9QmFVazS+GEIuFHW7Natk5RcRzspwsyOGNeFiqn+8fFHzpJuHsvmwHxPxYWMezGIbTy5//o2GIP6ZEbh3sR0GAdK+H2USQm4izW4EnLMK6Q/hpMAOG9stVbmLYlY3n0pGzlHb67TW9I0mW41UPBRk= Authentication-Results: edk2.groups.io; dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=amd.com; Received: from DM5PR12MB1355.namprd12.prod.outlook.com (2603:10b6:3:6e::7) by DM5PR12MB1163.namprd12.prod.outlook.com (2603:10b6:3:7a::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3216.25; Mon, 27 Jul 2020 15:28:22 +0000 Received: from DM5PR12MB1355.namprd12.prod.outlook.com ([fe80::25ec:e6ba:197c:4eb0]) by DM5PR12MB1355.namprd12.prod.outlook.com ([fe80::25ec:e6ba:197c:4eb0%8]) with mapi id 15.20.3216.031; Mon, 27 Jul 2020 15:28:22 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io CC: Brijesh Singh , Ard Biesheuvel , Eric Dong , Jordan Justen , Laszlo Ersek , Liming Gao , Michael D Kinney , Ray Ni Subject: [PATCH v12 13/46] OvmfPkg/VmgExitLib: Add support for IOIO_PROT NAE events Date: Mon, 27 Jul 2020 10:25:54 -0500 Message-ID: <28a4c22643ec1e2e064e5706e95a8d17ba3ef07f.1595863587.git.thomas.lendacky@amd.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: X-ClientProxiedBy: SN1PR12CA0112.namprd12.prod.outlook.com (2603:10b6:802:21::47) To DM5PR12MB1355.namprd12.prod.outlook.com (2603:10b6:3:6e::7) Return-Path: thomas.lendacky@amd.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from tlendack-t1.amd.com (165.204.77.1) by SN1PR12CA0112.namprd12.prod.outlook.com (2603:10b6:802:21::47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3216.23 via Frontend Transport; Mon, 27 Jul 2020 15:28:21 +0000 X-Mailer: git-send-email 2.27.0 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: f9add37c-67ed-4e68-de12-08d83241b274 X-MS-TrafficTypeDiagnostic: DM5PR12MB1163: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YCtz4rVyZy+SW8W3Y87q4ahXfezoAI1DNvkJ1QDjiWTkBkX3dHQUTSG6LUF1KD+E3/MgwzDP9wFy87ZhTFEqHhvbC3A9EMLAq22guHWZalFx21TticuwdM6gmxRvVnBnrDBTwdUtqIyBg3e6fkErF8bX9XF9Q/Rb2Y3QSKNKJnUs/R3jYpWiHeAqaVHoPVGIMuPGGrFyqw7xOnGa4TSfaFvO9K2H0r3Q2qBOtSEMGwPW25URfzskzo3+dFn8ZTSM08HHXPF4KvAyH4Hxt9+/05FZlYqooKQ24J62F00z1+DgbYCpnRYHb8POEi33lmrdsJHoga8EJ4TW77LW2yz39EUvpy1KDCCbOHvP9Mx7Ttdc85kN3ZfmFoq6LZtecNzXs17FNRxrP4Kd3QyuVpus4bEUmz/NUyAksBPHn3X1AQ/8vpv3mIWDkd3WUAVYAViFQ4Pg4dUFkyM4XYSvgk17lg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM5PR12MB1355.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(4636009)(376002)(39860400002)(346002)(396003)(136003)(366004)(26005)(7696005)(16526019)(52116002)(186003)(66946007)(2616005)(66556008)(316002)(36756003)(956004)(966005)(5660300002)(66476007)(54906003)(6666004)(478600001)(2906002)(30864003)(4326008)(6486002)(8676002)(8936002)(6916009)(83380400001)(86362001)(136400200001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData: QGHRclY04leBw/w5pWlLTTXD4AEj7CQ54PfJ6sfH+V5Qyr3YAU3rKjOkKnYEF+Cm7OmNNIp+k7tDY7F+D8Hsd5zZJlrSvnTm7do/8WYI1KqUo75wTtCi8E5Q5jMPlfG4Eq3l9eIY0lwCuy8gXUJRfk6bL3HfS1oeFhSlWjHuq1h8MDNOnuNZ3CcZt7LWd15PHuGKHzODodrZ0tv4DmCepVwIMD/mJbYlZk3we7LGlsLsMD09DP+M2dTCrvHG5p/pVM+e5RC+JhyZK5myAuf3xZSWckBuPU3aYmAvbGx291m94VmOT9yFRdOo6/qQOVbQLaBUlOHQRpti76wyEyD+D2I5BbrITGK41tCUIeiBPYeSb+7/tzbzmUBh5bIUnAwSJNZe25feCPjidWoqGLct+a4vieEmcaNouU0LJ8b6aQlAD/gbHwiEgA0JXHGRtsOUxARTK1QVLAwhoopVCy+3BNWaV+BhMtvCjrdHz95/ps0= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: f9add37c-67ed-4e68-de12-08d83241b274 X-MS-Exchange-CrossTenant-AuthSource: DM5PR12MB1355.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jul 2020 15:28:22.2751 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kRpHDMkDgWi/PcDTYNYNgra5xqwXbpKfTY+OMUuoUNOEbeTxKc+EkNMoGvs8fKf9j4D2FshHoOBJLwM8LqBJbg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1163 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a IOIO_PROT intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support a IOIO_PROT NAE event. Parse the instruction that generated the #VC exception, setting the required register values in the GHCB and creating the proper SW_EXITINFO1 value in the GHCB. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../IndustryStandard/InstructionParsing.h | 83 +++ OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 560 +++++++++++++++++- 2 files changed, 629 insertions(+), 14 deletions(-) create mode 100644 OvmfPkg/Include/IndustryStandard/InstructionParsing.h diff --git a/OvmfPkg/Include/IndustryStandard/InstructionParsing.h b/OvmfPk= g/Include/IndustryStandard/InstructionParsing.h new file mode 100644 index 000000000000..149ff328e06c --- /dev/null +++ b/OvmfPkg/Include/IndustryStandard/InstructionParsing.h @@ -0,0 +1,83 @@ +/** @file + Instruction parsing support definitions. + + Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __INSTRUCTION_PARSING_H__ +#define __INSTRUCTION_PARSING_H__ + +#include +#include + +// +// Instruction REX prefix definition +// +typedef union { + struct { + UINT8 BitB:1; + UINT8 BitX:1; + UINT8 BitR:1; + UINT8 BitW:1; + UINT8 Rex:4; + } Bits; + + UINT8 Uint8; +} INSTRUCTION_REX_PREFIX; + +// +// Instruction ModRM definition +// +typedef union { + struct { + UINT8 Rm:3; + UINT8 Reg:3; + UINT8 Mod:2; + } Bits; + + UINT8 Uint8; +} INSTRUCTION_MODRM; + +// +// Instruction SIB definition +// +typedef union { + struct { + UINT8 Base:3; + UINT8 Index:3; + UINT8 Scale:2; + } Bits; + + UINT8 Uint8; +} INSTRUCTION_SIB; + +// +// Legacy Instruction Prefixes +// +#define OVERRIDE_SEGMENT_CS 0x2E +#define OVERRIDE_SEGMENT_DS 0x3E +#define OVERRIDE_SEGMENT_ES 0x26 +#define OVERRIDE_SEGMENT_SS 0x36 +#define OVERRIDE_SEGMENT_FS 0x64 +#define OVERRIDE_SEGMENT_GS 0x65 +#define OVERRIDE_OPERAND_SIZE 0x66 +#define OVERRIDE_ADDRESS_SIZE 0x67 +#define LOCK_PREFIX 0xF0 +#define REPNZ_PREFIX 0xF2 +#define REPZ_PREFIX 0xF3 + +// +// REX Prefixes +// +#define REX_PREFIX_START 0x40 +#define REX_PREFIX_STOP 0x4F +#define REX_64BIT_OPERAND_SIZE_MASK 0x08 + +// +// Two-byte Opcode Flag +// +#define TWO_BYTE_OPCODE_ESCAPE 0x0F + +#endif diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index b6a955ed8088..04e8b8aebf7d 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -11,6 +11,529 @@ #include #include #include +#include + +// +// Instruction execution mode definition +// +typedef enum { + LongMode64Bit =3D 0, + LongModeCompat32Bit, + LongModeCompat16Bit, +} SEV_ES_INSTRUCTION_MODE; + +// +// Instruction size definition (for operand and address) +// +typedef enum { + Size8Bits =3D 0, + Size16Bits, + Size32Bits, + Size64Bits, +} SEV_ES_INSTRUCTION_SIZE; + +// +// Intruction segment definition +// +typedef enum { + SegmentEs =3D 0, + SegmentCs, + SegmentSs, + SegmentDs, + SegmentFs, + SegmentGs, +} SEV_ES_INSTRUCTION_SEGMENT; + +// +// Instruction rep function definition +// +typedef enum { + RepNone =3D 0, + RepZ, + RepNZ, +} SEV_ES_INSTRUCTION_REP; + +typedef struct { + UINT8 Rm; + UINT8 Reg; + UINT8 Mod; +} SEV_ES_INSTRUCTION_MODRM_EXT; + +typedef struct { + UINT8 Base; + UINT8 Index; + UINT8 Scale; +} SEV_ES_INSTRUCTION_SIB_EXT; + +// +// Instruction opcode definition +// +typedef struct { + SEV_ES_INSTRUCTION_MODRM_EXT ModRm; + + SEV_ES_INSTRUCTION_SIB_EXT Sib; + + UINTN RegData; + UINTN RmData; +} SEV_ES_INSTRUCTION_OPCODE_EXT; + +// +// Instruction parsing context definition +// +typedef struct { + GHCB *Ghcb; + + SEV_ES_INSTRUCTION_MODE Mode; + SEV_ES_INSTRUCTION_SIZE DataSize; + SEV_ES_INSTRUCTION_SIZE AddrSize; + BOOLEAN SegmentSpecified; + SEV_ES_INSTRUCTION_SEGMENT Segment; + SEV_ES_INSTRUCTION_REP RepMode; + + UINT8 *Begin; + UINT8 *End; + + UINT8 *Prefixes; + UINT8 *OpCodes; + UINT8 *Displacement; + UINT8 *Immediate; + + INSTRUCTION_REX_PREFIX RexPrefix; + + BOOLEAN ModRmPresent; + INSTRUCTION_MODRM ModRm; + + BOOLEAN SibPresent; + INSTRUCTION_SIB Sib; + + UINTN PrefixSize; + UINTN OpCodeSize; + UINTN DisplacementSize; + UINTN ImmediateSize; + + SEV_ES_INSTRUCTION_OPCODE_EXT Ext; +} SEV_ES_INSTRUCTION_DATA; + +// +// Non-automatic Exit function prototype +// +typedef +UINT64 +(*NAE_EXIT) ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ); + + +/** + Checks the GHCB to determine if the specified register has been marked v= alid. + + The ValidBitmap area represents the areas of the GHCB that have been mar= ked + valid. Return an indication of whether the area of the GHCB that holds t= he + specified register has been marked valid. + + @param[in] Ghcb Pointer to the Guest-Hypervisor Communication Block + @param[in] Reg Offset in the GHCB of the register to check + + @retval TRUE Register has been marked vald in the GHCB + @retval FALSE Register has not been marked valid in the GHCB + +**/ +STATIC +BOOLEAN +GhcbIsRegValid ( + IN GHCB *Ghcb, + IN GHCB_REGISTER Reg + ) +{ + UINT32 RegIndex; + UINT32 RegBit; + + RegIndex =3D Reg / 8; + RegBit =3D Reg & 0x07; + + return ((Ghcb->SaveArea.ValidBitmap[RegIndex] & (1 << RegBit)) !=3D 0); +} + +/** + Marks a register as valid in the GHCB. + + The ValidBitmap area represents the areas of the GHCB that have been mar= ked + valid. Set the area of the GHCB that holds the specified register as val= id. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communication Bl= ock + @param[in] Reg Offset in the GHCB of the register to mark valid + +**/ +STATIC +VOID +GhcbSetRegValid ( + IN OUT GHCB *Ghcb, + IN GHCB_REGISTER Reg + ) +{ + UINT32 RegIndex; + UINT32 RegBit; + + RegIndex =3D Reg / 8; + RegBit =3D Reg & 0x07; + + Ghcb->SaveArea.ValidBitmap[RegIndex] |=3D (1 << RegBit); +} + +/** + Decode instruction prefixes. + + Parse the instruction data to track the instruction prefixes that have + been used. + + @param[in] Regs x64 processor context + @param[in, out] InstructionData Instruction parsing context + +**/ +STATIC +VOID +DecodePrefixes ( + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN OUT SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_MODE Mode; + SEV_ES_INSTRUCTION_SIZE ModeDataSize; + SEV_ES_INSTRUCTION_SIZE ModeAddrSize; + UINT8 *Byte; + + // + // Always in 64-bit mode + // + Mode =3D LongMode64Bit; + ModeDataSize =3D Size32Bits; + ModeAddrSize =3D Size64Bits; + + InstructionData->Mode =3D Mode; + InstructionData->DataSize =3D ModeDataSize; + InstructionData->AddrSize =3D ModeAddrSize; + + InstructionData->Prefixes =3D InstructionData->Begin; + + Byte =3D InstructionData->Prefixes; + for ( ; ; Byte++, InstructionData->PrefixSize++) { + // + // Check the 0x40 to 0x4F range using an if statement here since some + // compilers don't like the "case 0x40 ... 0x4F:" syntax. This avoids + // 16 case statements below. + // + if ((*Byte >=3D REX_PREFIX_START) && (*Byte <=3D REX_PREFIX_STOP)) { + InstructionData->RexPrefix.Uint8 =3D *Byte; + if ((*Byte & REX_64BIT_OPERAND_SIZE_MASK) !=3D 0) { + InstructionData->DataSize =3D Size64Bits; + } + continue; + } + + switch (*Byte) { + case OVERRIDE_SEGMENT_CS: + case OVERRIDE_SEGMENT_DS: + case OVERRIDE_SEGMENT_ES: + case OVERRIDE_SEGMENT_SS: + if (Mode !=3D LongMode64Bit) { + InstructionData->SegmentSpecified =3D TRUE; + InstructionData->Segment =3D (*Byte >> 3) & 3; + } + break; + + case OVERRIDE_SEGMENT_FS: + case OVERRIDE_SEGMENT_GS: + InstructionData->SegmentSpecified =3D TRUE; + InstructionData->Segment =3D *Byte & 7; + break; + + case OVERRIDE_OPERAND_SIZE: + if (InstructionData->RexPrefix.Uint8 =3D=3D 0) { + InstructionData->DataSize =3D + (Mode =3D=3D LongMode64Bit) ? Size16Bits : + (Mode =3D=3D LongModeCompat32Bit) ? Size16Bits : + (Mode =3D=3D LongModeCompat16Bit) ? Size32Bits : 0; + } + break; + + case OVERRIDE_ADDRESS_SIZE: + InstructionData->AddrSize =3D + (Mode =3D=3D LongMode64Bit) ? Size32Bits : + (Mode =3D=3D LongModeCompat32Bit) ? Size16Bits : + (Mode =3D=3D LongModeCompat16Bit) ? Size32Bits : 0; + break; + + case LOCK_PREFIX: + break; + + case REPZ_PREFIX: + InstructionData->RepMode =3D RepZ; + break; + + case REPNZ_PREFIX: + InstructionData->RepMode =3D RepNZ; + break; + + default: + InstructionData->OpCodes =3D Byte; + InstructionData->OpCodeSize =3D (*Byte =3D=3D TWO_BYTE_OPCODE_ESCAPE= ) ? 2 : 1; + + InstructionData->End =3D Byte + InstructionData->OpCodeSize; + InstructionData->Displacement =3D InstructionData->End; + InstructionData->Immediate =3D InstructionData->End; + return; + } + } +} + +/** + Determine instruction length + + Return the total length of the parsed instruction. + + @param[in] InstructionData Instruction parsing context + + @return Length of parsed instruction + +**/ +STATIC +UINT64 +InstructionLength ( + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + return (UINT64) (InstructionData->End - InstructionData->Begin); +} + +/** + Initialize the instruction parsing context. + + Initialize the instruction parsing context, which includes decoding the + instruction prefixes. + + @param[in, out] InstructionData Instruction parsing context + @param[in] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in] Regs x64 processor context + +**/ +STATIC +VOID +InitInstructionData ( + IN OUT SEV_ES_INSTRUCTION_DATA *InstructionData, + IN GHCB *Ghcb, + IN EFI_SYSTEM_CONTEXT_X64 *Regs + ) +{ + SetMem (InstructionData, sizeof (*InstructionData), 0); + InstructionData->Ghcb =3D Ghcb; + InstructionData->Begin =3D (UINT8 *) Regs->Rip; + InstructionData->End =3D (UINT8 *) Regs->Rip; + + DecodePrefixes (Regs, InstructionData); +} + +/** + Report an unsupported event to the hypervisor + + Use the VMGEXIT support to report an unsupported event to the hypervisor= . + + @param[in] Ghcb Pointer to the Guest-Hypervisor Communicatio= n + Block + @param[in] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @return New exception value to propagate + +**/ +STATIC +UINT64 +UnsupportedExit ( + IN GHCB *Ghcb, + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + Status =3D VmgExit (Ghcb, SVM_EXIT_UNSUPPORTED, Regs->ExceptionData, 0); + if (Status =3D=3D 0) { + GHCB_EVENT_INJECTION Event; + + Event.Uint64 =3D 0; + Event.Elements.Vector =3D GP_EXCEPTION; + Event.Elements.Type =3D GHCB_EVENT_INJECTION_TYPE_EXCEPTION; + Event.Elements.Valid =3D 1; + + Status =3D Event.Uint64; + } + + return Status; +} + +/** + Build the IOIO event information. + + The IOIO event information identifies the type of IO operation to be per= formed + by the hypervisor. Build this information based on the instruction data. + + @param[in] Regs x64 processor context + @param[in, out] InstructionData Instruction parsing context + + @return IOIO event information value + +**/ +STATIC +UINT64 +IoioExitInfo ( + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN OUT SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 ExitInfo; + + ExitInfo =3D 0; + + switch (*(InstructionData->OpCodes)) { + // + // IN immediate opcodes + // + case 0xE4: + case 0xE5: + InstructionData->ImmediateSize =3D 1; + InstructionData->End++; + ExitInfo |=3D IOIO_TYPE_IN; + ExitInfo |=3D ((*(InstructionData->OpCodes + 1)) << 16); + break; + + // + // OUT immediate opcodes + // + case 0xE6: + case 0xE7: + InstructionData->ImmediateSize =3D 1; + InstructionData->End++; + ExitInfo |=3D IOIO_TYPE_OUT; + ExitInfo |=3D ((*(InstructionData->OpCodes + 1)) << 16) | IOIO_TYPE_OU= T; + break; + + // + // IN register opcodes + // + case 0xEC: + case 0xED: + ExitInfo |=3D IOIO_TYPE_IN; + ExitInfo |=3D ((Regs->Rdx & 0xffff) << 16); + break; + + // + // OUT register opcodes + // + case 0xEE: + case 0xEF: + ExitInfo |=3D IOIO_TYPE_OUT; + ExitInfo |=3D ((Regs->Rdx & 0xffff) << 16); + break; + + default: + return 0; + } + + switch (*(InstructionData->OpCodes)) { + // + // Single-byte opcodes + // + case 0xE4: + case 0xE6: + case 0xEC: + case 0xEE: + ExitInfo |=3D IOIO_DATA_8; + break; + + // + // Length determined by instruction parsing + // + default: + ExitInfo |=3D (InstructionData->DataSize =3D=3D Size16Bits) ? IOIO_DAT= A_16 + : IOIO_DATA_32; + } + + switch (InstructionData->AddrSize) { + case Size16Bits: + ExitInfo |=3D IOIO_ADDR_16; + break; + + case Size32Bits: + ExitInfo |=3D IOIO_ADDR_32; + break; + + case Size64Bits: + ExitInfo |=3D IOIO_ADDR_64; + break; + + default: + break; + } + + if (InstructionData->RepMode !=3D 0) { + ExitInfo |=3D IOIO_REP; + } + + return ExitInfo; +} + +/** + Handle an IOIO event. + + Use the VMGEXIT instruction to handle an IOIO event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +IoioExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 ExitInfo1, Status; + + ExitInfo1 =3D IoioExitInfo (Regs, InstructionData); + if (ExitInfo1 =3D=3D 0) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + + if ((ExitInfo1 & IOIO_TYPE_IN) !=3D 0) { + Ghcb->SaveArea.Rax =3D 0; + } else { + CopyMem (&Ghcb->SaveArea.Rax, &Regs->Rax, IOIO_DATA_BYTES (ExitInfo1))= ; + } + GhcbSetRegValid (Ghcb, GhcbRax); + + Status =3D VmgExit (Ghcb, SVM_EXIT_IOIO_PROT, ExitInfo1, 0); + if (Status !=3D 0) { + return Status; + } + + if ((ExitInfo1 & IOIO_TYPE_IN) !=3D 0) { + if (!GhcbIsRegValid (Ghcb, GhcbRax)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + CopyMem (&Regs->Rax, &Ghcb->SaveArea.Rax, IOIO_DATA_BYTES (ExitInfo1))= ; + } + + return 0; +} =20 /** Handle a #VC exception. @@ -38,6 +561,8 @@ VmgExitHandleVc ( MSR_SEV_ES_GHCB_REGISTER Msr; EFI_SYSTEM_CONTEXT_X64 *Regs; GHCB *Ghcb; + NAE_EXIT NaeExit; + SEV_ES_INSTRUCTION_DATA InstructionData; UINT64 ExitCode, Status; EFI_STATUS VcRet; =20 @@ -54,24 +579,31 @@ VmgExitHandleVc ( =20 ExitCode =3D Regs->ExceptionData; switch (ExitCode) { + case SVM_EXIT_IOIO_PROT: + NaeExit =3D IoioExit; + break; + default: - Status =3D VmgExit (Ghcb, SVM_EXIT_UNSUPPORTED, ExitCode, 0); - if (Status =3D=3D 0) { - Regs->ExceptionData =3D 0; - *ExceptionType =3D GP_EXCEPTION; + NaeExit =3D UnsupportedExit; + } + + InitInstructionData (&InstructionData, Ghcb, Regs); + + Status =3D NaeExit (Ghcb, Regs, &InstructionData); + if (Status =3D=3D 0) { + Regs->Rip +=3D InstructionLength (&InstructionData); + } else { + GHCB_EVENT_INJECTION Event; + + Event.Uint64 =3D Status; + if (Event.Elements.ErrorCodeValid !=3D 0) { + Regs->ExceptionData =3D Event.Elements.ErrorCode; } else { - GHCB_EVENT_INJECTION Event; - - Event.Uint64 =3D Status; - if (Event.Elements.ErrorCodeValid !=3D 0) { - Regs->ExceptionData =3D Event.Elements.ErrorCode; - } else { - Regs->ExceptionData =3D 0; - } - - *ExceptionType =3D Event.Elements.Vector; + Regs->ExceptionData =3D 0; } =20 + *ExceptionType =3D Event.Elements.Vector; + VcRet =3D EFI_PROTOCOL_ERROR; } =20 --=20 2.27.0