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charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: quoted-printable On 6/2/21 10:16 AM, gaoliming wrote: > Laszlo: > Thanks for the detail information about QemuFwCfgLib. So, this librar= y is arch generic. Now, it is only consumed by ARM and AARCH64. >=20 > Daniel: > Can you show more on how RiscV64 uses this QemuFwCfgLib? See below. QEMU for the generic RISCV64 platform is implemented almost=20 like Arm with device tree and fw-cfg device, quite unlike X64 which uses= =20 port-mapped I/O and doesn't have device trees. > Thanks > Liming >> -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- >> =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io =E4=BB=A3=E8=A1=A8 Laszlo Ersek >> =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2021=E5=B9=B46=E6=9C=881=E6=97=A5= 15:58 >> =E6=94=B6=E4=BB=B6=E4=BA=BA: gaoliming ; deve= l@edk2.groups.io; >> daniel.schaefer@hpe.com; ardb@kernel.org >> =E6=8A=84=E9=80=81: 'Chang, Abner (HPS SW/FW Technologist)' ; >> 'Michael D Kinney' ; 'Zhiguang Liu' >> ; 'Leif Lindholm' >> =E4=B8=BB=E9=A2=98: Re: =E5=9B=9E=E5=A4=8D: =E5=9B=9E=E5=A4=8D: [edk2-d= evel] [PATCH v1 1/1] Add MemoryFence >> implementation for RiscV64 >> >> On 06/01/21 02:56, gaoliming wrote: >>> Seemly, Edk2\ArmVirtPkg\Library\QemuFwCfgLib\QemuFwCfgLib.inf is not >> arch >>> specific library. It can also be used in RISCV64. >>> >>> >>> >>> Ard and Laszlo: >>> >>> If ArmVirtPkg\Library\QemuFwCfgLib is arch generic, can it be moved >> from >>> ArmVirtPkg into OvmfPkg? >> >> ArmVirtPkg/Library/QemuFwCfgLib is a QemuFwCfgLib instance that is >> currently only used by the ArmVirtQemu and ArmVirtQemuKernel platforms. =E2=80=8BYes, but we're in the process of Creating RiscvVirtPkg that just = like=20 ArmVirtPkg supports the generic "virt" machine type of qemu-system-riscv64= . >> It depends on the FDT_CLIENT_PROTOCOL, from >> "ArmVirtPkg/ArmVirtPkg.dec" >> and "ArmVirtPkg/Include/Protocol/FdtClient.h", to locate the fw_cfg >> device. The protocol is ArmVirtPkg specific. Due to the protocol depex, >> the library is also DXE_DRIVER and UEFI_DRIVER only. =E2=80=8BYes, we also use that in our RiscvVirtPkg ;) >> The library uses the MMIO data registers of the fw_cfg device by >> default; if the DMA interface is supported, then it uses the DMA >> interface. In both cases, some registers are accessed with 64-bit >> accesses if MDE_CPU_AARCH64 is defined, and with 32-bit accesses >> otherwise. >> >> I don't see how RISCV could reuse this library verbatim. =E2=80=8BWhy not? We can boot perfectly fine from virtio (which is PCI) wi= th=20 these lines in our RIscvVirt.dsc: # Flattened Device Tree (FDT) access library FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf # PCI Libraries PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf PciExpressLib|ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciEx= pressLib.inf PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciS= egmentLib.inf PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf # Virtio Support VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLi= b.inf QemuFwCfgLib|ArmVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/BaseQemuFwCfgS3LibNull.inf QemuFwCfgSimpleParserLib|OvmfPkg/Library/QemuFwCfgSimpleParserLib/QemuFwCf= gSimpleParserLib.inf QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadIm= ageLib.inf # PCI support PciPcdProducerLib|ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProduce= rLib.inf PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf PciHostBridgeLib|ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLi= b.inf PciHostBridgeUtilityLib|OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBri= dgeUtilityLib.inf Excerpt from the edk2 boot log: InvalidateInstructionCacheRange:RISC-V unsupported function. Loading driver at 0x000BF7EC000 EntryPoint=3D0x000BF7EC28A=20 PciHostBridgeDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF BF31EF18 ProtectUefiImageCommon - 0xBF334BC0 - 0x00000000BF7EC000 - 0x0000000000014080 PROGRESS CODE: V03040002 I0 Found FwCfg @ 0x10100008/0x10100000 Found FwCfg DMA @ 0x10100010 ProcessPciHost: Config[0x30000000+0x10000000) Bus[0x0..0xFF]=20 Io[0x0+0x10000)@0x3000000 Mem32[0x40000000+0x40000000)@00 =E2=80=8BIf you look at the source code of the QEMU implementation of risc= v64=20 virt and compare it to aarch64 they are very similar, but quite=20 different from x64. >> The linked patch at >> > cbb308a> >> is a no-go; the MDE_CPU_RISCV64 macro has no place in an ArmVirtPkg >> library. >> >> The library can be moved to the new directory >> >> OvmfPkg/Library/DxeQemuFwCfgLibFdtMmio >> >> (note the rename in the last pathname component), but it needs to be >> done in multiple steps. The FDT protocol GUID and structure definition >> has to be moved at first, separately from the library, and every move >> operation (i.e., each one of the protocol move and the library muve) >> must be implemented with *at least* three steps -- copy the original to >> OvmfPkg (updating BASE_NAME at once), update DSC references under >> ArmVirtPkg, remove the original under ArmVirtPkg. Only then can you add >> customizations. Okay, I understand and agree. We'll think about all of the Arm modules=20 and libraries we're currently using, how to move those and send an RFC=20 soon. We have not encountered any other issues, other than this change,=20 when using the Arm code. >> Regarding the processor type macros, I believe Mike recently introduced >> ISA-independent macros, for expressing 64-bit vs. 32-bit. I'm not >> exactly sure about the details, but I think we now have a macro under >> MdePkg that says "64-bit processor" without having to state AARCH64 or >> RISCV64. I found some at CryptoPkg/Library/Include/CrtLibSupport.h and RedfishPkg/PrivateInclude/Library/RedfishCrtLib.h called SIXTY_FOUR_BIT and THIRTY_TWO_BIT. Not sure if they are for general consumption? It seems that Mike suggests those to be defined in the platform's DSC? See d0bf83e1cca >> Thanks >> Laszlo >> >> >>> >>> >>> >>> Thanks >>> >>> Liming >>> >>> =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io =E4=BB=A3=E8=A1=A8 Daniel >> Schaefer >>> =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2021=E5=B9=B45=E6=9C=8821=E6=97= =A5 20:46 >>> =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io; gaoliming@byosoft.c= om.cn >>> =E6=8A=84=E9=80=81: Chang, Abner (HPS SW/FW Technologist) ; >> 'Michael >>> D Kinney' ; 'Zhiguang Liu' >>> ; 'Leif Lindholm' >>> =E4=B8=BB=E9=A2=98: Re: =E5=9B=9E=E5=A4=8D: [edk2-devel] [PATCH v1 1/1= ] Add MemoryFence >> implementation >>> for RiscV64 >>> >>> >>> >>> It's not required to go into that tag. >>> >>> We need two more patches that we haven't submitted yet to boot on >> Qemu. >>> >>> >>> >>> Would it be okay if we used a library from ArmVirtPkg for RISCV64? >>> >>> See: >>> >> https://github.com/riscv/riscv-edk2/commit/8c7960ef860c65f2646912c3dcc >> bb308a >>> 98e0cc3 >>> >>> Or does it have to be moved to some other place first? >>> >>> _____ >>> >>> From: devel@edk2.groups.io >>> > on behalf of >> gaoliming >>> > >>> Sent: Friday, May 21, 2021 14:35 >>> To: devel@edk2.groups.io >>> >; Schaefer, Danie= l >>> > >>> Cc: Chang, Abner (HPS SW/FW Technologist) >> >; 'Michael D Kinney' >>> >; >> 'Zhiguang >>> Liu' >; 'Leif >>> Lindholm' > >>> Subject: =E5=9B=9E=E5=A4=8D: =E5=9B=9E=E5=A4=8D: [edk2-devel] [PATCH v= 1 1/1] Add MemoryFence >>> implementation for RiscV64 >>> >>> >>> >>> Daniel: >>> >>> Thanks for your information. Acked-by: Liming Gao >> >> > >>> >>> >>> >>> And, do you request to merge this patch for edk2 stable tag 202105? >>> >>> >>> >>> Thanks >>> >>> Liming >>> >>> =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io >>> > =E4=BB=A3=E8=A1= =A8 Daniel >> Schaefer >>> =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2021=E5=B9=B45=E6=9C=8821=E6=97= =A5 13:27 >>> =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io ; >>> gaoliming@byosoft.com.cn >>> =E6=8A=84=E9=80=81: Chang, Abner (HPS SW/FW Technologist) >> >; 'Michael D Kinney' >>> >; >> 'Zhiguang >>> Liu' >; 'Leif >>> Lindholm' > >>> =E4=B8=BB=E9=A2=98: Re: =E5=9B=9E=E5=A4=8D: [edk2-devel] [PATCH v1 1/1= ] Add MemoryFence >> implementation >>> for RiscV64 >>> >>> >>> >>> Great! >>> >>> >>> >>> It is verified I can boot Linux from a virtio ESP using this patch on = QEMU >>> virt machine. >>> >>> See: >>> >> https://github.com/riscv/riscv-edk2-platforms/runs/2618819010?check_sui= te >> _fo >>> cus=3Dtrue >>> >>> >>> >>> Thanks, >>> >>> Daniel >>> >>> _____ >>> >>> From: devel@edk2.groups.io >>> > on behalf of >> gaoliming >>> > >>> Sent: Friday, May 21, 2021 13:14 >>> To: devel@edk2.groups.io >>> >; Schaefer, Danie= l >>> > >>> Cc: Chang, Abner (HPS SW/FW Technologist) >> >; 'Michael D Kinney' >>> >; >> 'Zhiguang >>> Liu' >; 'Leif >>> Lindholm' > >>> Subject: =E5=9B=9E=E5=A4=8D: =E5=9B=9E=E5=A4=8D: [edk2-devel] [PATCH v= 1 1/1] Add MemoryFence >>> implementation for RiscV64 >>> >>> >>> >>> Daniel: >>> Now, it is clear to me. So, I suggest to merge this change when it = is >>> verified on generic RISC-V QEMU virt machine. Is it OK? >>> >>> Thanks >>> Liming >>>> -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- >>>> =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io >>> > =E4=BB=A3=E8=A1= =A8 Daniel >>>> Schaefer >>>> =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2021=E5=B9=B45=E6=9C=8818=E6=97= = =A5 10:35 >>>> =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io ; >>> gaoliming@byosoft.com.cn >>>> =E6=8A=84=E9=80=81: 'Abner Chang' > >; >>> 'Michael D Kinney' >>>> >; >>> 'Zhiguang Liu' = >; >>> 'Leif >>>> Lindholm' > >>>> =E4=B8=BB=E9=A2=98: Re: =E5=9B=9E=E5=A4=8D: [edk2-devel] [PATCH v1 1/= 1] Add MemoryFence >>>> implementation for RiscV64 >>>> >>>> On 5/18/21 9:04 AM, gaoliming wrote: >>>>> Daniel: >>>>> Seemly, this API is missing in BaseLib for RiscV64 arch. How do yo= u >>> detect >>>>> this issue? >>>> >>>> What do you mean it's missing? >>>> Yes MemoryFence() for RiscV64 is missing currently, that's why I'm ad= ding >>> it >>>> here. >>>> >>>> Maybe you mean that it's not currently used? That's also true. >>>> I'm enabling the generic QEMU virt machine (like OVMF or ArmVirtPkg) = for >>>> RISC-V. >>>> At least QemuFwCfgLib and VirtioLib need it. >>>> That's why I have the need to add this implementation now. >>>> >>>> Does that clear it up? >>>> >>>>> Thanks >>>>> Liming >>>>>> -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- >>>>>> =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io >>> > =E4=BB=A3=E8=A1= =A8 Daniel >>>>>> Schaefer >>>>>> =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2021=E5=B9=B45=E6=9C=8816=E6= =97=A5 2:13 >>>>>> =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io >>>>>> =E6=8A=84=E9=80=81: Abner Chang > >; >>> Michael D Kinney >>>>>> >; >>> Liming Gao > >; >>>>>> Zhiguang Liu > >; >>> Leif Lindholm >>> > >>>>>> =E4=B8=BB=E9=A2=98: [edk2-devel] [PATCH v1 1/1] Add MemoryFence imp= lementation >> for >>>>>> RiscV64 >>>>>> >>>>>> Cc: Abner Chang > > >>>>>> Cc: Michael D Kinney >> > >>>>>> Cc: Liming Gao > >> cn> > >>>>>> Cc: Zhiguang Liu >> > >>>>>> Cc: Leif Lindholm > >>>>>> Signed-off-by: Daniel Schaefer > >> schaefer@hpe.com> > >>>>>> --- >>>>>> MdePkg/Library/BaseLib/BaseLib.inf | 1 + >>>>>> MdePkg/Library/BaseLib/RiscV64/MemoryFence.S | 33 >>>>>> ++++++++++++++++++++ >>>>>> 2 files changed, 34 insertions(+) >>>>>> >>>>>> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf >>>>>> b/MdePkg/Library/BaseLib/BaseLib.inf >>>>>> index b76f3af380ea..b7ab5f632366 100644 >>>>>> --- a/MdePkg/Library/BaseLib/BaseLib.inf >>>>>> +++ b/MdePkg/Library/BaseLib/BaseLib.inf >>>>>> @@ -399,6 +399,7 @@ >>>>>> RiscV64/DisableInterrupts.c >>>>>> >>>>>> >>>>>> RiscV64/EnableInterrupts.c >>>>>> >>>>>> >>>>>> RiscV64/CpuPause.c >>>>>> >>>>>> >>>>>> + RiscV64/MemoryFence.S | GCC >>>>>> >>>>>> >>>>>> RiscV64/RiscVSetJumpLongJump.S | GCC >>>>>> >>>>>> >>>>>> RiscV64/RiscVCpuBreakpoint.S | GCC >>>>>> >>>>>> >>>>>> RiscV64/RiscVCpuPause.S | GCC >>>>>> >>>>>> >>>>>> diff --git a/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S >>>>>> b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S >>>>>> new file mode 100644 >>>>>> index 000000000000..283df9356a9a >>>>>> --- /dev/null >>>>>> +++ b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S >>>>>> @@ -0,0 +1,33 @@ >>>>>> >>>>> >>> +##-------------------------------------------------------------------= ------ >>>>> ----- >>>>>> >>>>>> >>>>>> +# >>>>>> >>>>>> >>>>>> +# MemoryFence() for RiscV64 >>>>>> >>>>>> >>>>>> + >>>>>> >>>>>> >>>>>> +# Copyright (c) 2021, Hewlett Packard Enterprise Development. All >>> rights >>>>>> reserved. >>>>>> >>>>>> >>>>>> +# >>>>>> >>>>>> >>>>>> +# SPDX-License-Identifier: BSD-2-Clause-Patent >>>>>> >>>>>> >>>>>> +# >>>>>> >>>>>> >>>>>> >>>>> >>> +##-------------------------------------------------------------------= ------ >>>>> ----- >>>>>> >>>>>> >>>>>> + >>>>>> >>>>>> >>>>>> +.text >>>>>> >>>>>> >>>>>> +.p2align 2 >>>>>> >>>>>> >>>>>> + >>>>>> >>>>>> >>>>>> +ASM_GLOBAL ASM_PFX(MemoryFence) >>>>>> >>>>>> >>>>>> + >>>>>> >>>>>> >>>>>> + >>>>>> >>>>>> >>>>>> +#/** >>>>>> >>>>>> >>>>>> +# Used to serialize load and store operations. >>>>>> >>>>>> >>>>>> +# >>>>>> >>>>>> >>>>>> +# All loads and stores that proceed calls to this function are >>>>> guaranteed to >>>>>> be >>>>>> >>>>>> >>>>>> +# globally visible when this function returns. >>>>>> >>>>>> >>>>>> +# >>>>>> >>>>>> >>>>>> +#**/ >>>>>> >>>>>> >>>>>> +#VOID >>>>>> >>>>>> >>>>>> +#EFIAPI >>>>>> >>>>>> >>>>>> +#MemoryFence ( >>>>>> >>>>>> >>>>>> +# VOID >>>>>> >>>>>> >>>>>> +# ); >>>>>> >>>>>> >>>>>> +# >>>>>> >>>>>> >>>>>> +ASM_PFX(MemoryFence): >>>>>> >>>>>> >>>>>> + // Fence on all memory and I/O >>>>>> >>>>>> >>>>>> + fence >>>>>> >>>>>> >>>>>> + ret >>>>>> >>>>>> >>>>>> -- >>>>>> 2.30.1 >>>>>> >>>>>> >>>>>> >>>>>> >>>>>> >>>>> >>>>> >>>>> >>>>> >>>>> >>>>> >>>>> >>>>> >>>> >>>> >>>> >>>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >> >> >> >> >> >=20 >=20 >=20 >=20 >=20 >=20 >=20 >=20