From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (NAM02-BN1-obe.outbound.protection.outlook.com [40.107.212.85]) by mx.groups.io with SMTP id smtpd.web10.23684.1683894773947156221 for ; Fri, 12 May 2023 05:32:54 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@amd.com header.s=selector1 header.b=t6krHK36; spf=permerror, err=parse error for token &{10 18 %{i}._ip.%{h}._ehlo.%{d}._spf.vali.email}: invalid domain name (domain: amd.com, ip: 40.107.212.85, mailfrom: abdullateef.attar@amd.com) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UA3MLga3twFLU0KIBNbjSz8xe+tJD/IVM1THq/mZKatOqYB0YIzdQ5V/QJMtha3P942MV4WKE3kQZyhbYwC8lepLNay2U++j0uwguMYLy3jlWamRCM/CDskg7iIMkgJuLFkmTuuq9KabWUBp7LMKXkpLKgqpEbmXkukyf71geFACAMIFYbptFssJ9crcA1wZq+salYAHjrY6poHhIMIONZxHyP+rkDop7mfHsmHgb7Yv5vswBo5MdUB2+0W73RvRqNA7PquCnY/ieor+QqC3cT2vO05Z8TcA0nUObMADPNW+edBRoXYCLEW257DuMdTJEYmI7uKsHVXpisqzWsiWdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=e9GbSvqlU9MSjdDXME3gVrdqzrJ4c+7AdxeuZx0pBCI=; b=aFwqFiQlcORJJ9G9E7zH6qPl+mdun7lobH3VdzH+QEcD0AH2PG322Y8IrBTJ2D8cbNlFjokDyQHqHQfWYS/l7XOyomDCr2GVq/O4o0oBaxefaytUPTYt1wQI2oVMqVm3gLACOiOz1iPj8eoyte8Ryrc4bN14H5CyTJ0y4skcUiUej0vN8AekWW9G7z0HtZpMXbwWxEWnSDKU5a2ElQkI0SX0Uh5rNpbgbpSTbm6lDh/3G4Ql5/+YBxdoCbx4ufUDX0v9bqduYLPyOKdahcrg4M+wHupixzOsA6mOjjDGq9voJGB+HZQO2kqBlbrXgyoFLMo3r9wp0RSkEs567ySmjw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=edk2.groups.io smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=e9GbSvqlU9MSjdDXME3gVrdqzrJ4c+7AdxeuZx0pBCI=; b=t6krHK36uG3f1GKLuceU4hQOut6f0091iEaLq2fQPtxuvwAB5BRhZyl2PEQlT3xnf96343yNOd503G6RJh0uRJtU/RbbtyQ6G/nnmm4CQITIQew5FJWK6/keGzpymI5PWtzwq+czGt/dnnQEgaRnC4WNl7HMxGZiouvnY6yT8yk= Received: from MW4PR03CA0137.namprd03.prod.outlook.com (2603:10b6:303:8c::22) by SN7PR12MB8060.namprd12.prod.outlook.com (2603:10b6:806:343::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.32; Fri, 12 May 2023 12:32:51 +0000 Received: from CO1NAM11FT104.eop-nam11.prod.protection.outlook.com (2603:10b6:303:8c:cafe::c3) by MW4PR03CA0137.outlook.office365.com (2603:10b6:303:8c::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.24 via Frontend Transport; Fri, 12 May 2023 12:32:51 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1NAM11FT104.mail.protection.outlook.com (10.13.174.220) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6387.24 via Frontend Transport; Fri, 12 May 2023 12:32:50 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Fri, 12 May 2023 07:32:45 -0500 Received: from BLR-LAB-SFW01.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Fri, 12 May 2023 07:32:42 -0500 From: "Abdul Lateef Attar" To: CC: Abdul Lateef Attar , Paul Grimes , Abner Chang , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [PATCH v13 6/8] UefiCpuPkg: Implements MmSaveStateLib for Intel Date: Fri, 12 May 2023 18:02:22 +0530 Message-ID: <2a07f4bf6991f95021550912a7afbc47e0f97fe7.1683894329.git.abdattar@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Return-Path: AbdulLateef.Attar@amd.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT104:EE_|SN7PR12MB8060:EE_ X-MS-Office365-Filtering-Correlation-Id: 643fe6dc-3a40-43fc-c3b6-08db52e50069 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wpWaF6IiMf1HgfGgrANNAj1UppgeV4Ls3YQ6XBz0CPz/qwMHv4kMxaYkXi2K+4nvlx7CKxI/1OWQ2Idfxwxij9PQbH+6crPtTUljdAETe2Fx6JiA6zH9zW6F6ff6pFJBFU2vlgw90OZBjrwJonWzYWjaTiOa7WHiuSYQZ6EbIUq/yOGk0MKXy3UqvSn/CHbsnFJyuexC0ks0kA/APWEK67l1+3ovuzD1yRjwIp9gW1+8ZHauX+Q//2Xt2/9SolsN/PbH6hKMptjrRN0zNk9KAYhvg4OhOyxCCOpL0szgzUlwWKer56zKePSA9N3JbGRq5S7R3Va+SsSmS+rZAAfWOnsvZYJmie83fYn/sDxfElImIoAVqM4UTt1QQW/L0WnZtVvBuQZQY7crViaJziYiOVP+rHDo+UNoz5SkEkSw0WX5CV84WpyRoXdQL6918GsKARqQXHqero6M+bgGHbjBf4acJJ3vN/ncSr+HiilksPOfDX+BqlX8m4h+tq3KocOq0ExX+DodqBNr3L9uKSl7VlYorfXRFlha5jFCvzxy4ud3NnYi3cpxEU43Q0oW/squJCvkWLFIG9YEQ15L37DZ37ho+SbIDfkdh4oEW3oofn/l5tYCM1upokj9sClTFPEoTwNlwu/yYNpe3p36RNgDjuP+qCwj6mJb9s6Cvry32m9F9HmREGBoVtEeY3BHCzYhqrbnbyHNiHpJxFVo+FFUbTsXu694tQOKEMfvF+Zi7Bs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(6029001)(4636009)(39860400002)(396003)(376002)(346002)(136003)(451199021)(36840700001)(46966006)(40470700004)(336012)(356005)(36756003)(70586007)(4326008)(966005)(7696005)(54906003)(19627235002)(478600001)(316002)(6916009)(70206006)(36860700001)(5660300002)(81166007)(82310400005)(2906002)(30864003)(40480700001)(41300700001)(8936002)(186003)(8676002)(82740400003)(426003)(83380400001)(26005)(47076005)(2616005)(6666004)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2023 12:32:50.9414 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 643fe6dc-3a40-43fc-c3b6-08db52e50069 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT104.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8060 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4182 Implements MmSaveStateLib library interfaces to read and write save state registers for Intel processor family. Moves Intel and AMD common functionality to common area. Cc: Paul Grimes Cc: Abner Chang Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Abdul Lateef Attar Reviewed-by: Abner Chang --- UefiCpuPkg/UefiCpuPkg.dsc | 3 + .../MmSaveStateLib/IntelMmSaveStateLib.inf | 34 ++ .../Library/MmSaveStateLib/IntelMmSaveState.c | 410 ++++++++++++++++++ 3 files changed, 447 insertions(+) create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.i= nf create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveState.c diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 6e29850bed17..eb6bdc5bef63 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -101,6 +101,7 @@ [LibraryClasses.common.DXE_SMM_DRIVER] HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuE= xceptionHandlerLib.inf MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf + MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf =20 [LibraryClasses.common.MM_STANDALONE] MmServicesTableLib|MdePkg/Library/StandaloneMmServicesTableLib/Standalon= eMmServicesTableLib.inf @@ -174,6 +175,7 @@ [Components.IA32, Components.X64] FILE_GUID =3D B7242C74-BD21-49EE-84B4-07162E8C080D SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeat= uresLib.inf + MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.i= nf } UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf @@ -191,6 +193,7 @@ [Components.IA32, Components.X64] UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultR= eportLib/UnitTestResultReportLibConOut.inf } UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf + UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf =20 [Components.X64] diff --git a/UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf b/Ue= fiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf new file mode 100644 index 000000000000..b92dfa643203 --- /dev/null +++ b/UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf @@ -0,0 +1,34 @@ +## @file +# SMM Smram save state service lib. +# +# This is SMM Smram save state service lib that provide service to read an= d +# save savestate area registers. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D IntelMmSaveStateLib + FILE_GUID =3D 37E8137B-9F74-4250-8951-7A970A3C39C0 + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MmSaveStateLib + +[Sources] + MmSaveState.h + MmSaveStateCommon.c + IntelMmSaveState.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + SmmServicesTableLib diff --git a/UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveState.c b/UefiCpu= Pkg/Library/MmSaveStateLib/IntelMmSaveState.c new file mode 100644 index 000000000000..fd321bb571d5 --- /dev/null +++ b/UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveState.c @@ -0,0 +1,410 @@ +/** @file +Provides services to access SMRAM Save State Map + +Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MmSaveState.h" +#include +#include +#include + +#define INTEL_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1 +#define INTEL_MM_SAVE_STATE_REGISTER_IOMISC_INDEX 2 +#define INTEL_MM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3 +#define INTEL_MM_SAVE_STATE_REGISTER_MAX_INDEX 4 + +/// +/// Macro used to simplify the lookup table entries of type CPU_MM_SAVE_ST= ATE_LOOKUP_ENTRY +/// +#define MM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field) + +/// +/// Lookup table used to retrieve the widths and offsets associated with e= ach +/// supported EFI_MM_SAVE_STATE_REGISTER value +/// +CONST CPU_MM_SAVE_STATE_LOOKUP_ENTRY mCpuWidthOffset[] =3D { + { 0, 0, 0, 0, = 0, FALSE }, // Reserved + + // + // Internally defined CPU Save State Registers. Not defined in PI SMM CP= U Protocol. + // + { 4, 4, MM_CPU_OFFSET (x86.SMMRevId), MM_CPU_OFFSET (x64.SMMRevId), = 0, FALSE }, // INTEL_MM_SAVE_STATE_REGI= STER_SMMREVID_INDEX =3D 1 + { 4, 4, MM_CPU_OFFSET (x86.IOMisc), MM_CPU_OFFSET (x64.IOMisc), = 0, FALSE }, // INTEL_MM_SAVE_STATE_REGI= STER_IOMISC_INDEX =3D 2 + { 4, 8, MM_CPU_OFFSET (x86.IOMemAddr), MM_CPU_OFFSET (x64.IOMemAddr), = MM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE }, // INTEL_MM_SAVE_STATE_REGI= STER_IOMEMADDR_INDEX =3D 3 + + // + // CPU Save State registers defined in PI SMM CPU Protocol. + // + { 0, 8, 0, MM_CPU_OFFSET (x64.GdtBaseLoDword= ), MM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_GDTBASE =3D 4 + { 0, 8, 0, MM_CPU_OFFSET (x64.IdtBaseLoDword= ), MM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_IDTBASE =3D 5 + { 0, 8, 0, MM_CPU_OFFSET (x64.LdtBaseLoDword= ), MM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_LDTBASE =3D 6 + { 0, 0, 0, 0, = 0, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_GDTLIMIT =3D 7 + { 0, 0, 0, 0, = 0, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_IDTLIMIT =3D 8 + { 0, 0, 0, 0, = 0, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_LDTLIMIT =3D 9 + { 0, 0, 0, 0, = 0, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_LDTINFO =3D 10 + + { 4, 4, MM_CPU_OFFSET (x86._ES), MM_CPU_OFFSET (x64._ES), = 0, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_ES =3D 20 + { 4, 4, MM_CPU_OFFSET (x86._CS), MM_CPU_OFFSET (x64._CS), = 0, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_CS =3D 21 + { 4, 4, MM_CPU_OFFSET (x86._SS), MM_CPU_OFFSET (x64._SS), = 0, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_SS =3D 22 + { 4, 4, MM_CPU_OFFSET (x86._DS), MM_CPU_OFFSET (x64._DS), = 0, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_DS =3D 23 + { 4, 4, MM_CPU_OFFSET (x86._FS), MM_CPU_OFFSET (x64._FS), = 0, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_FS =3D 24 + { 4, 4, MM_CPU_OFFSET (x86._GS), MM_CPU_OFFSET (x64._GS), = 0, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_GS =3D 25 + { 0, 4, 0, MM_CPU_OFFSET (x64._LDTR), = 0, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_LDTR_SEL =3D 26 + { 4, 4, MM_CPU_OFFSET (x86._TR), MM_CPU_OFFSET (x64._TR), = 0, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_TR_SEL =3D 27 + { 4, 8, MM_CPU_OFFSET (x86._DR7), MM_CPU_OFFSET (x64._DR7), = MM_CPU_OFFSET (x64._DR7) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_DR7 =3D 28 + { 4, 8, MM_CPU_OFFSET (x86._DR6), MM_CPU_OFFSET (x64._DR6), = MM_CPU_OFFSET (x64._DR6) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_DR6 =3D 29 + { 0, 8, 0, MM_CPU_OFFSET (x64._R8), = MM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_R8 =3D 30 + { 0, 8, 0, MM_CPU_OFFSET (x64._R9), = MM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_R9 =3D 31 + { 0, 8, 0, MM_CPU_OFFSET (x64._R10), = MM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_R10 =3D 32 + { 0, 8, 0, MM_CPU_OFFSET (x64._R11), = MM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_R11 =3D 33 + { 0, 8, 0, MM_CPU_OFFSET (x64._R12), = MM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_R12 =3D 34 + { 0, 8, 0, MM_CPU_OFFSET (x64._R13), = MM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_R13 =3D 35 + { 0, 8, 0, MM_CPU_OFFSET (x64._R14), = MM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_R14 =3D 36 + { 0, 8, 0, MM_CPU_OFFSET (x64._R15), = MM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_R15 =3D 37 + { 4, 8, MM_CPU_OFFSET (x86._EAX), MM_CPU_OFFSET (x64._RAX), = MM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_RAX =3D 38 + { 4, 8, MM_CPU_OFFSET (x86._EBX), MM_CPU_OFFSET (x64._RBX), = MM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_RBX =3D 39 + { 4, 8, MM_CPU_OFFSET (x86._ECX), MM_CPU_OFFSET (x64._RCX), = MM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_RCX =3D 40 + { 4, 8, MM_CPU_OFFSET (x86._EDX), MM_CPU_OFFSET (x64._RDX), = MM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_RDX =3D 41 + { 4, 8, MM_CPU_OFFSET (x86._ESP), MM_CPU_OFFSET (x64._RSP), = MM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_RSP =3D 42 + { 4, 8, MM_CPU_OFFSET (x86._EBP), MM_CPU_OFFSET (x64._RBP), = MM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_RBP =3D 43 + { 4, 8, MM_CPU_OFFSET (x86._ESI), MM_CPU_OFFSET (x64._RSI), = MM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_RSI =3D 44 + { 4, 8, MM_CPU_OFFSET (x86._EDI), MM_CPU_OFFSET (x64._RDI), = MM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_RDI =3D 45 + { 4, 8, MM_CPU_OFFSET (x86._EIP), MM_CPU_OFFSET (x64._RIP), = MM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_RIP =3D 46 + + { 4, 8, MM_CPU_OFFSET (x86._EFLAGS), MM_CPU_OFFSET (x64._RFLAGS), = MM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGIS= TER_RFLAGS =3D 51 + { 4, 8, MM_CPU_OFFSET (x86._CR0), MM_CPU_OFFSET (x64._CR0), = MM_CPU_OFFSET (x64._CR0) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_CR0 =3D 52 + { 4, 8, MM_CPU_OFFSET (x86._CR3), MM_CPU_OFFSET (x64._CR3), = MM_CPU_OFFSET (x64._CR3) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_CR3 =3D 53 + { 0, 4, 0, MM_CPU_OFFSET (x64._CR4), = 0, FALSE }, // EFI_MM_SAVE_STATE_REGIS= TER_CR4 =3D 54 +}; + +/// +/// Structure used to build a lookup table for the IOMisc width informatio= n +/// +typedef struct { + UINT8 Width; + EFI_MM_SAVE_STATE_IO_WIDTH IoWidth; +} CPU_MM_SAVE_STATE_IO_WIDTH; + +/// +/// Lookup table for the IOMisc width information +/// +STATIC CONST CPU_MM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] =3D { + { 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 0 + { 1, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 }, // SMM_IO_LENGTH_BYTE =3D 1 + { 2, EFI_MM_SAVE_STATE_IO_WIDTH_UINT16 }, // SMM_IO_LENGTH_WORD =3D 2 + { 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 3 + { 4, EFI_MM_SAVE_STATE_IO_WIDTH_UINT32 }, // SMM_IO_LENGTH_DWORD =3D 4 + { 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 5 + { 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 6 + { 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 } // Undefined =3D 7 +}; + +/// +/// Lookup table for the IOMisc type information +/// +STATIC CONST EFI_MM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] =3D { + EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_DX =3D 0 + EFI_MM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_IN_DX =3D 1 + EFI_MM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_OUTS =3D 2 + EFI_MM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_INS =3D 3 + (EFI_MM_SAVE_STATE_IO_TYPE)0, // Undefined =3D 4 + (EFI_MM_SAVE_STATE_IO_TYPE)0, // Undefined =3D 5 + EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_OUTS =3D 6 + EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_INS =3D 7 + EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_IMMEDIATE =3D 8 + EFI_MM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_OUT_IMMEDIATE =3D 9 + (EFI_MM_SAVE_STATE_IO_TYPE)0, // Undefined =3D 1= 0 + (EFI_MM_SAVE_STATE_IO_TYPE)0, // Undefined =3D 1= 1 + (EFI_MM_SAVE_STATE_IO_TYPE)0, // Undefined =3D 1= 2 + (EFI_MM_SAVE_STATE_IO_TYPE)0, // Undefined =3D 1= 3 + (EFI_MM_SAVE_STATE_IO_TYPE)0, // Undefined =3D 1= 4 + (EFI_MM_SAVE_STATE_IO_TYPE)0 // Undefined =3D 1= 5 +}; + +/** + Read an SMM Save State register on the target processor. If this functi= on + returns EFI_UNSUPPORTED, then the caller is responsible for reading the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to read the SMM Save State. = The + value must be between 0 and the NumberOfCpus field= in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to read. + @param[in] Width The number of bytes to read from the CPU save stat= e. + @param[out] Buffer Upon return, this holds the CPU register value rea= d + from the save state. + + @retval EFI_SUCCESS The register was read from Save State. + @retval EFI_INVALID_PARAMTER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support reading Reg= ister. + @retval EFI_NOT_FOUND If desired Register not found. +**/ +EFI_STATUS +EFIAPI +MmSaveStateReadRegister ( + IN UINTN CpuIndex, + IN EFI_MM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + OUT VOID *Buffer + ) +{ + UINT32 SmmRevId; + SMRAM_SAVE_STATE_IOMISC IoMisc; + EFI_MM_SAVE_STATE_IO_INFO *IoInfo; + + // + // Check for special EFI_MM_SAVE_STATE_REGISTER_LMA + // + if (Register =3D=3D EFI_MM_SAVE_STATE_REGISTER_LMA) { + // + // Only byte access is supported for this register + // + if (Width !=3D 1) { + return EFI_INVALID_PARAMETER; + } + + *(UINT8 *)Buffer =3D MmSaveStateGetRegisterLma (); + + return EFI_SUCCESS; + } + + // + // Check for special EFI_MM_SAVE_STATE_REGISTER_IO + // + if (Register =3D=3D EFI_MM_SAVE_STATE_REGISTER_IO) { + // + // Get SMM Revision ID + // + MmSaveStateReadRegisterByIndex (CpuIndex, INTEL_MM_SAVE_STATE_REGISTER= _SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId); + + // + // See if the CPU supports the IOMisc register in the save state + // + if (SmmRevId < SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC) { + return EFI_NOT_FOUND; + } + + // + // Get the IOMisc register value + // + MmSaveStateReadRegisterByIndex (CpuIndex, INTEL_MM_SAVE_STATE_REGISTER= _IOMISC_INDEX, sizeof (IoMisc.Uint32), &IoMisc.Uint32); + + // + // Check for the SMI_FLAG in IOMisc + // + if (IoMisc.Bits.SmiFlag =3D=3D 0) { + return EFI_NOT_FOUND; + } + + // + // Only support IN/OUT, but not INS/OUTS/REP INS/REP OUTS. + // + if ((mSmmCpuIoType[IoMisc.Bits.Type] !=3D EFI_MM_SAVE_STATE_IO_TYPE_IN= PUT) && + (mSmmCpuIoType[IoMisc.Bits.Type] !=3D EFI_MM_SAVE_STATE_IO_TYPE_OU= TPUT)) + { + return EFI_NOT_FOUND; + } + + // + // Compute index for the I/O Length and I/O Type lookup tables + // + if ((mSmmCpuIoWidth[IoMisc.Bits.Length].Width =3D=3D 0) || (mSmmCpuIoT= ype[IoMisc.Bits.Type] =3D=3D 0)) { + return EFI_NOT_FOUND; + } + + // + // Make sure the incoming buffer is large enough to hold IoInfo before= accessing + // + if (Width < sizeof (EFI_MM_SAVE_STATE_IO_INFO)) { + return EFI_INVALID_PARAMETER; + } + + // + // Zero the IoInfo structure that will be returned in Buffer + // + IoInfo =3D (EFI_MM_SAVE_STATE_IO_INFO *)Buffer; + ZeroMem (IoInfo, sizeof (EFI_MM_SAVE_STATE_IO_INFO)); + + // + // Use lookup tables to help fill in all the fields of the IoInfo stru= cture + // + IoInfo->IoPort =3D (UINT16)IoMisc.Bits.Port; + IoInfo->IoWidth =3D mSmmCpuIoWidth[IoMisc.Bits.Length].IoWidth; + IoInfo->IoType =3D mSmmCpuIoType[IoMisc.Bits.Type]; + MmSaveStateReadRegister (CpuIndex, EFI_MM_SAVE_STATE_REGISTER_RAX, mSm= mCpuIoWidth[IoMisc.Bits.Length].Width, &IoInfo->IoData); + return EFI_SUCCESS; + } + + // + // Convert Register to a register lookup table index + // + return MmSaveStateReadRegisterByIndex (CpuIndex, MmSaveStateGetRegisterI= ndex (Register, INTEL_MM_SAVE_STATE_REGISTER_MAX_INDEX), Width, Buffer); +} + +/** + Writes an SMM Save State register on the target processor. If this func= tion + returns EFI_UNSUPPORTED, then the caller is responsible for writing the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to write the SMM Save State. = The + value must be between 0 and the NumberOfCpus field = in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to write. + @param[in] Width The number of bytes to write to the CPU save state. + @param[in] Buffer Upon entry, this holds the new CPU register value. + + @retval EFI_SUCCESS The register was written to Save State. + @retval EFI_INVALID_PARAMTER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support writing Reg= ister. + @retval EFI_NOT_FOUND If desired Register not found. +**/ +EFI_STATUS +EFIAPI +MmSaveStateWriteRegister ( + IN UINTN CpuIndex, + IN EFI_MM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + IN CONST VOID *Buffer + ) +{ + UINTN RegisterIndex; + SMRAM_SAVE_STATE_MAP *CpuSaveState; + + // + // Writes to EFI_MM_SAVE_STATE_REGISTER_LMA are ignored + // + if (Register =3D=3D EFI_MM_SAVE_STATE_REGISTER_LMA) { + return EFI_SUCCESS; + } + + // + // Writes to EFI_MM_SAVE_STATE_REGISTER_IO are not supported + // + if (Register =3D=3D EFI_MM_SAVE_STATE_REGISTER_IO) { + return EFI_NOT_FOUND; + } + + // + // Convert Register to a register lookup table index + // + RegisterIndex =3D MmSaveStateGetRegisterIndex (Register, INTEL_MM_SAVE_S= TATE_REGISTER_MAX_INDEX); + if (RegisterIndex =3D=3D 0) { + return EFI_NOT_FOUND; + } + + CpuSaveState =3D gSmst->CpuSaveState[CpuIndex]; + + // + // Do not write non-writable SaveState, because it will cause exception. + // + if (!mCpuWidthOffset[RegisterIndex].Writeable) { + return EFI_UNSUPPORTED; + } + + // + // Check CPU mode + // + if (MmSaveStateGetRegisterLma () =3D=3D EFI_MM_SAVE_STATE_REGISTER_LMA_= 32BIT) { + // + // If 32-bit mode width is zero, then the specified register can not b= e accessed + // + if (mCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { + return EFI_NOT_FOUND; + } + + // + // If Width is bigger than the 32-bit mode width, then the specified r= egister can not be accessed + // + if (Width > mCpuWidthOffset[RegisterIndex].Width32) { + return EFI_INVALID_PARAMETER; + } + + // + // Write SMM State register + // + ASSERT (CpuSaveState !=3D NULL); + CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset= 32, Buffer, Width); + } else { + // + // If 64-bit mode width is zero, then the specified register can not b= e accessed + // + if (mCpuWidthOffset[RegisterIndex].Width64 =3D=3D 0) { + return EFI_NOT_FOUND; + } + + // + // If Width is bigger than the 64-bit mode width, then the specified r= egister can not be accessed + // + if (Width > mCpuWidthOffset[RegisterIndex].Width64) { + return EFI_INVALID_PARAMETER; + } + + // + // Write at most 4 of the lower bytes of SMM State register + // + CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset= 64Lo, Buffer, MIN (4, Width)); + if (Width > 4) { + // + // Write at most 4 of the upper bytes of SMM State register + // + CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offs= et64Hi, (UINT8 *)Buffer + 4, Width - 4); + } + } + + return EFI_SUCCESS; +} + +/** + Returns LMA value of the Processor. + + @retval UINT8 returns LMA bit value. +**/ +UINT8 +MmSaveStateGetRegisterLma ( + VOID + ) +{ + UINT32 RegEax; + UINT32 RegEdx; + UINTN FamilyId; + UINTN ModelId; + UINT8 SmmSaveStateRegisterLma; + + // + // Retrieve CPU Family + // + AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL); + FamilyId =3D (RegEax >> 8) & 0xf; + ModelId =3D (RegEax >> 4) & 0xf; + if ((FamilyId =3D=3D 0x06) || (FamilyId =3D=3D 0x0f)) { + ModelId =3D ModelId | ((RegEax >> 12) & 0xf0); + } + + RegEdx =3D 0; + AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); + if (RegEax >=3D CPUID_EXTENDED_CPU_SIG) { + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx); + } + + // + // Determine the mode of the CPU at the time an SMI occurs + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual + // Volume 3C, Section 34.4.1.1 + // + SmmSaveStateRegisterLma =3D EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT; + if ((RegEdx & BIT29) !=3D 0) { + SmmSaveStateRegisterLma =3D EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT; + } + + if (FamilyId =3D=3D 0x06) { + if ((ModelId =3D=3D 0x17) || (ModelId =3D=3D 0x0f) || (ModelId =3D=3D = 0x1c)) { + SmmSaveStateRegisterLma =3D EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT; + } + } + + return SmmSaveStateRegisterLma; +} --=20 2.25.1