From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DE43721199245 for ; Mon, 10 Dec 2018 00:01:11 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Dec 2018 00:01:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,337,1539673200"; d="scan'208";a="126553362" Received: from shzintpr02.sh.intel.com (HELO [10.253.24.48]) ([10.239.4.160]) by fmsmga004.fm.intel.com with ESMTP; 10 Dec 2018 00:01:08 -0800 To: "Chasel, Chiu" , edk2-devel@lists.01.org References: <20181207133008.2488-1-chasel.chiu@intel.com> Cc: star.zeng@intel.com From: "Zeng, Star" Message-ID: <2b7e36f0-011e-3360-c667-634be44023dd@intel.com> Date: Mon, 10 Dec 2018 16:00:38 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20181207133008.2488-1-chasel.chiu@intel.com> Subject: Re: [PATCH] IntelFsp2Pkg: Add FspmArchConfigPpi to support Dispatch mode X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 10 Dec 2018 08:01:12 -0000 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Hi Chasel, Two minor comments are added inline. On 2018/12/7 21:30, Chasel, Chiu wrote: > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1381 > > In Dispatch mode FSP may consume PPI directly so creating > FSPM_ARCH_CONFIG_PPI to align with FSPM_ARCH_UPD. > > Test: Verified on internal platform to boot with this PPI > installed successfully. > > Cc: Nate DeSimone > Cc: Star Zeng > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Chasel Chiu > --- > IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h | 41 +++++++++++++++++++++++++++++++++++++++++ > IntelFsp2Pkg/IntelFsp2Pkg.dec | 3 +++ > 2 files changed, 44 insertions(+) > > diff --git a/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h > new file mode 100644 > index 0000000000..5b3dac5b04 > --- /dev/null > +++ b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h > @@ -0,0 +1,41 @@ > +/** @file > + Header file for FSP-M Arch Config PPI > + > + @copyright > + Copyright (c) 2018, Intel Corporation. All rights reserved.
> + > + This program and the accompanying materials are licensed and made available under > + the terms and conditions of the BSD License which accompanies this distribution. > + The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > + > +#ifndef _FSPM_ARCH_CONFIG_PPI_H_ > +#define _FSPM_ARCH_CONFIG_PPI_H_ > + > +/// > +/// Global ID for the FSPM_ARCH_CONFIG_PPI. > +/// > +#define FSPM_ARCH_CONFIG_GUID \ > + { \ > + 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \ > + } > + > +/// > +/// This PPI provides FSP-M Arch Config PPI. How about adding more description about this PPI is used for dispatch mode? > +/// > +typedef struct { > + UINT8 Revision; > + UINT8 Reserved[3]; > + VOID *NvsBufferPtr; > + UINT32 BootLoaderTolumSize; > + UINT8 Reserved1[8]; > +} FSPM_ARCH_CONFIG_PPI; Could the definition be aligned with FSPM_ARCH_UPD in IntelFsp2Pkg\Include\FspEas\FspApi.h? Then we can use typedef to define it like below. typedef FSPM_ARCH_UPD FSPM_ARCH_CONFIG_PPI; Otherwise, please add description for the fields like FSPM_ARCH_UPD did. Thanks, Star > + > +extern EFI_GUID gFspmArchConfigPpiGuid; > + > +#endif // _FSPM_ARCH_CONFIG_PPI_H_ > diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec > index 50496241da..de1bece562 100644 > --- a/IntelFsp2Pkg/IntelFsp2Pkg.dec > +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec > @@ -70,6 +70,9 @@ > gFspPerformanceDataGuid = { 0x56ed21b6, 0xba23, 0x429e, { 0x89, 0x32, 0x37, 0x6d, 0x8e, 0x18, 0x2e, 0xe3 } } > gFspEventEndOfFirmwareGuid = { 0xbd44f629, 0xeae7, 0x4198, { 0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } } > > +[Ppis] > + gFspmArchConfigPpiGuid = { 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } } > + > [PcdsFixedAtBuild] > gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32|0x00000001 > gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase |0xFEF00000|UINT32|0x10001001 >