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charset="us-ascii" Content-Transfer-Encoding: quoted-printable From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a CPUID instruction requires the current value of the XCR0 register. In order to retrieve that value, the XGETBV instruction needs to be executed. Provide the necessary support to execute the XGETBV instruction. Cc: Michael D Kinney Cc: Liming Gao Reviewed-by: Liming Gao Signed-off-by: Tom Lendacky --- MdePkg/Library/BaseLib/BaseLib.inf | 2 ++ MdePkg/Include/Library/BaseLib.h | 17 +++++++++++++ MdePkg/Library/BaseLib/Ia32/XGetBv.nasm | 31 ++++++++++++++++++++++ MdePkg/Library/BaseLib/X64/XGetBv.nasm | 34 +++++++++++++++++++++++++ 4 files changed, 84 insertions(+) create mode 100644 MdePkg/Library/BaseLib/Ia32/XGetBv.nasm create mode 100644 MdePkg/Library/BaseLib/X64/XGetBv.nasm diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index c740a819cacf..3b93b5db8d24 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -183,6 +183,7 @@ [Sources.Ia32] Ia32/EnableCache.nasm| GCC Ia32/DisableCache.nasm| GCC Ia32/RdRand.nasm + Ia32/XGetBv.nasm =20 Ia32/DivS64x64Remainder.c Ia32/InternalSwitchStack.c | MSFT @@ -315,6 +316,7 @@ [Sources.X64] X64/EnableDisableInterrupts.nasm X64/DisablePaging64.nasm X64/RdRand.nasm + X64/XGetBv.nasm ChkStkGcc.c | GCC =20 [Sources.EBC] diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index 8e7b87cbda4e..7edf0051a0a0 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -7831,6 +7831,23 @@ AsmLfence ( VOID ); =20 +/** + Executes a XGETBV instruction + + Executes a XGETBV instruction. This function is only available on IA-32 = and + x64. + + @param[in] Index Extended control register index + + @return The current value of the extended control regist= er +**/ +UINT64 +EFIAPI +AsmXGetBv ( + IN UINT32 Index + ); + + /** Patch the immediate operand of an IA32 or X64 instruction such that the = byte, word, dword or qword operand is encoded at the end of the instruction's diff --git a/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm b/MdePkg/Library/BaseL= ib/Ia32/XGetBv.nasm new file mode 100644 index 000000000000..9f7b03bbff35 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm @@ -0,0 +1,31 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; XGetBv.Asm +; +; Abstract: +; +; AsmXgetBv function +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + + SECTION .text + +;-------------------------------------------------------------------------= ----- +; UINT64 +; EFIAPI +; AsmXGetBv ( +; IN UINT32 Index +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(AsmXGetBv) +ASM_PFX(AsmXGetBv): + mov ecx, [esp + 4] + xgetbv + ret diff --git a/MdePkg/Library/BaseLib/X64/XGetBv.nasm b/MdePkg/Library/BaseLi= b/X64/XGetBv.nasm new file mode 100644 index 000000000000..09f3be8ae0a8 --- /dev/null +++ b/MdePkg/Library/BaseLib/X64/XGetBv.nasm @@ -0,0 +1,34 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; XGetBv.Asm +; +; Abstract: +; +; AsmXgetBv function +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + + DEFAULT REL + SECTION .text + +;-------------------------------------------------------------------------= ----- +; UINT64 +; EFIAPI +; AsmXGetBv ( +; IN UINT32 Index +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(AsmXGetBv) +ASM_PFX(AsmXGetBv): + xgetbv + shl rdx, 32 + or rax, rdx + ret + --=20 2.27.0