From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CFDF782005 for ; Thu, 15 Dec 2016 17:48:27 -0800 (PST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP; 15 Dec 2016 17:48:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,355,1477983600"; d="scan'208";a="912741017" Received: from shwdeftian.ccr.corp.intel.com ([10.239.158.36]) by orsmga003.jf.intel.com with ESMTP; 15 Dec 2016 17:48:26 -0800 From: Feng Tian To: edk2-devel@lists.01.org Cc: Michael Kinney , Jiewen Yao , Jeff Fan Date: Fri, 16 Dec 2016 09:48:12 +0800 Message-Id: <2d3392fa654faaf80a5e177e0c07aa48418a9015.1481851932.git.feng.tian@intel.com> X-Mailer: git-send-email 2.7.1.windows.2 In-Reply-To: References: In-Reply-To: References: Subject: [patch 1/4] UefiCpuPkg/Include: Update MSEG structure comments X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Dec 2016 01:48:27 -0000 From: Michael Kinney Add comments to describe fields of MSEG_HEADER and add define values for the MonitorFeatures field. Cc: Jiewen Yao Cc: Jeff Fan Cc: Feng Tian Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney --- UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h index a7a221d..a74ea51 100644 --- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h +++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h @@ -484,7 +484,19 @@ typedef union { field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER. **/ typedef struct { + /// + /// Different processors may use different MSEG revision identifiers. These + /// identifiers enable software to avoid using an MSEG header formatted for + /// one processor on a processor that uses a different format. Software can + /// discover the MSEG revision identifier that a processor uses by reading + /// the VMX capability MSR IA32_VMX_MISC. + // UINT32 MsegHeaderRevision; + /// + /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field + /// is the IA-32e mode SMM feature bit. It indicates whether the logical + /// processor will be in IA-32e mode after the STM is activated. + /// UINT32 MonitorFeatures; UINT32 GdtrLimit; UINT32 GdtrBaseOffset; @@ -492,12 +504,19 @@ typedef struct { UINT32 EipOffset; UINT32 EspOffset; UINT32 Cr3Offset; - // - // Pad header so total size is 2KB - // + /// + /// Pad header so total size is 2KB + /// UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)]; } MSEG_HEADER; +/// +/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER +/// +#define STM_FEATURES_IA32E 0x1 +/// +/// @} +/// /** Base address of the logical processor's SMRAM image (RO, SMM only). If -- 2.7.1.windows.2