From: "Sami Mujawar" <sami.mujawar@arm.com>
To: devel@edk2.groups.io, khasim.mohammed@arm.com
Cc: nd@arm.com, Deepak Pandey <Deepak.Pandey@arm.com>
Subject: Re: [edk2-devel] [PATCH v5 4/4] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead
Date: Wed, 19 Jan 2022 15:02:28 +0000 [thread overview]
Message-ID: <2e4c69f0-9775-f32a-e9ce-83dbec1295f0@arm.com> (raw)
In-Reply-To: <20211222011440.3687-5-khasim.mohammed@arm.com>
Hi Khasim,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Regards,
Sami Mujawar
On 22/12/2021 01:14 AM, Khasim Mohammed via groups.io wrote:
> The patch removes PciExpressLib implementation for N1Sdp as:
>
> a) The PciSegmentLib implementation for N1Sdp makes MmioRead() calls
> instead of PciRead() which makes the PciExpressLib redundant.
>
> b) Since N1Sdp requires multiple segments to be supported, PciExpressLib
> and PciLib cannot be used, PciSegmentLib should be used instead as it
> supports multiple segments.
>
> Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
> ---
> Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 4 +-
> .../PciExpressLib.c | 1589 -----------------
> .../PciExpressLib.inf | 56 -
> 3 files changed, 1 insertion(+), 1648 deletions(-)
> delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
> delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
>
> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> index cb2049966c..8dac1bc54c 100644
> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> @@ -75,9 +75,7 @@
> [LibraryClasses.common.DXE_DRIVER]
> FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
> PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> - PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
> - PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
> - PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
> + PciSegmentLib|Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
>
> [LibraryClasses.common.DXE_RUNTIME_DRIVER]
> BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
> deleted file mode 100644
> index bb0246b4a9..0000000000
> --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
> +++ /dev/null
> @@ -1,1589 +0,0 @@
> -/** @file
> - Functions in this library instance make use of MMIO functions in IoLib to
> - access memory mapped PCI configuration space.
> -
> - All assertions for I/O operations are handled in MMIO functions in the IoLib
> - Library.
> -
> - Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> -
> - On the NeoverseN1Soc, a slave error is generated when host accesses the
> - configuration space of non-available device or unimplemented function on a
> - given bus. So this library introduces a workaround using IsBdfValid(),
> - to return 0xFFFFFFFF for all such access.
> -
> - In addition to this, the hardware has two other limitations which affect
> - access to the PCIe root port:
> - 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
> - from rest of the downstream hierarchy ECAM space.
> - 2. Root port ECAM space is not capable of 8bit/16bit writes.
> - The description of the workarounds included for these limitations can
> - be found in the comments below.
> -
> - Copyright (c) 2020, ARM Limited. All rights reserved.
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -
> -#include <Base.h>
> -
> -#include <Library/BaseLib.h>
> -#include <Library/PciExpressLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/PcdLib.h>
> -#include <NeoverseN1Soc.h>
> -
> -/**
> - Assert the validity of a PCI address. A valid PCI address should contain 1's
> - only in the low 28 bits.
> -
> - @param A The address to validate.
> -
> -**/
> -#define ASSERT_INVALID_PCI_ADDRESS(A) \
> - ASSERT (((A) & ~0xfffffff) == 0)
> -
> -/* Root port Entry, BDF Entries Count */
> -#define BDF_TABLE_ENTRY_SIZE 4
> -#define BDF_TABLE_HEADER_COUNT 2
> -#define BDF_TABLE_HEADER_SIZE 8
> -
> -/* BDF table offsets for PCIe */
> -#define PCIE_BDF_TABLE_OFFSET 0
> -
> -#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F)
> -#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F)
> -#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07)
> -#define GET_REG_NUM(Address) ((Address) & 0xFFF)
> -
> -/**
> - BDF Table structure : (Header + BDF Entries)
> - --------------------------------------------
> - [Offset 0x00] ROOT PORT ADDRESS
> - [Offset 0x04] BDF ENTRIES COUNT
> - [Offset 0x08] BDF ENTRY 0
> - [Offset 0x0C] BDF ENTRY 1
> - [Offset 0x10] BDF ENTRY 2
> - [Offset 0x14] BDF ENTRY 3
> - [Offset 0x18] BDF ENTRY 4
> - ...
> - [Offset 0x--] BDF ENTRY N
> - --------------------------------------------
> -**/
> -
> -/**
> - Value returned for reads on configuration space of unimplemented
> - device functions.
> -**/
> -STATIC UINTN mDummyConfigData = 0xFFFFFFFF;
> -
> -/**
> - Registers a PCI device so PCI configuration registers may be accessed after
> - SetVirtualAddressMap().
> -
> - Registers the PCI device specified by Address so all the PCI configuration
> - registers associated with that PCI device may be accessed after SetVirtualAddressMap()
> - is called.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @retval RETURN_SUCCESS The PCI device was registered for runtime access.
> - @retval RETURN_UNSUPPORTED An attempt was made to call this function
> - after ExitBootServices().
> - @retval RETURN_UNSUPPORTED The resources required to access the PCI device
> - at runtime could not be mapped.
> - @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
> - complete the registration.
> -
> -**/
> -RETURN_STATUS
> -EFIAPI
> -PciExpressRegisterForRuntimeAccess (
> - IN UINTN Address
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return RETURN_UNSUPPORTED;
> -}
> -
> -/**
> - Check if the requested PCI address can be safely accessed.
> -
> - SCP performs the initial bus scan, prepares a table of valid BDF addresses
> - and shares them through non-trusted SRAM. This function validates if the
> - requested PCI address belongs to a valid BDF by checking the table of valid
> - entries. If not, this function will return false. This is a workaround to
> - avoid bus fault that occurs when accessing unavailable PCI device due to
> - hardware bug.
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return TRUE BDF can be accessed, valid.
> - @return FALSE BDF should not be accessed, invalid.
> -
> -**/
> -STATIC
> -BOOLEAN
> -IsBdfValid (
> - IN UINTN Address
> - )
> -{
> - UINTN BdfCount;
> - UINTN BdfValue;
> - UINTN BdfEntry;
> - UINTN Count;
> - UINTN TableBase;
> - UINTN ConfigBase;
> -
> - ConfigBase = Address & ~0xFFF;
> - TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET;
> - BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE);
> - BdfEntry = TableBase + BDF_TABLE_HEADER_SIZE;
> -
> - /* Skip the header & check remaining entry */
> - for (Count = 0; Count < BdfCount; Count++, BdfEntry += BDF_TABLE_ENTRY_SIZE) {
> - BdfValue = MmioRead32 (BdfEntry);
> - if (BdfValue == ConfigBase) {
> - return TRUE;
> - }
> - }
> -
> - return FALSE;
> -}
> -
> -/**
> - Get the physical address of a configuration space register.
> -
> - Implement a workaround to avoid generation of slave errors from the bus. That
> - is, retrieve the PCI Express Base Address via a PCD entry, add the incomming
> - address with that base address and check whether this converted address
> - points to a accessible BDF. If it is not accessible, return the address
> - of a dummy location so that a read from it does not cause a slave error.
> -
> - In addition to this, implement a workaround for accessing the root port's
> - configuration space. The root port configuration space is not contiguous
> - with the rest of the downstream hierarchy configuration space. So determine
> - whether the specified address is for the root port and use a different base
> - address for it.
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return Physical address of the configuration register that corresponds to the
> - PCI configuration register specified by input parameter 'Address'.
> -
> -**/
> -STATIC
> -VOID*
> -GetPciExpressAddress (
> - IN UINTN Address
> - )
> -{
> - UINT8 Bus, Device, Function;
> - UINTN ConfigAddress;
> -
> - Bus = GET_BUS_NUM (Address);
> - Device = GET_DEV_NUM (Address);
> - Function = GET_FUNC_NUM (Address);
> -
> - if ((Bus == 0) && (Device == 0) && (Function == 0)) {
> - ConfigAddress = PcdGet32 (PcdPcieRootPortConfigBaseAddress) + Address;
> - } else {
> - ConfigAddress = PcdGet64 (PcdPciExpressBaseAddress) + Address;
> - if (!IsBdfValid(Address)) {
> - ConfigAddress = (UINTN)&mDummyConfigData;
> - }
> - }
> -
> - return (VOID *)ConfigAddress;
> -}
> -
> -/**
> - Reads an 8-bit PCI configuration register.
> -
> - Reads and returns the 8-bit PCI configuration register specified by Address.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return The read value from the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressRead8 (
> - IN UINTN Address
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioRead8 ((UINTN)GetPciExpressAddress (Address));
> -}
> -
> -/**
> - Writes an 8-bit PCI configuration register.
> -
> - Writes the 8-bit PCI configuration register specified by Address with the
> - value specified by Value. Value is returned. This function must guarantee
> - that all PCI read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param Value The value to write.
> -
> - @return The value written to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressWrite8 (
> - IN UINTN Address,
> - IN UINT8 Value
> - )
> -{
> - UINT8 Bus, Device, Function;
> - UINT8 Offset;
> - UINT32 Data;
> -
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> -
> - Bus = GET_BUS_NUM (Address);
> - Device = GET_DEV_NUM (Address);
> - Function = GET_FUNC_NUM (Address);
> -
> - //
> - // 8-bit and 16-bit writes to root port config space is not supported due to
> - // a hardware limitation. As a workaround, perform a read-update-write
> - // sequence on the whole 32-bit word of the root port config register such
> - // that only the specified 8-bits of that word are updated.
> - //
> - if ((Bus == 0) && (Device == 0) && (Function == 0)) {
> - Offset = Address & 0x3;
> - Address &= 0xFFFFFFFC;
> - Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address));
> - Data &= ~(0xFF << (8 * Offset));
> - Data |= (Value << (8 * Offset));
> - MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data);
> - return Value;
> - }
> -
> - return MmioWrite8 ((UINTN)GetPciExpressAddress (Address), Value);
> -}
> -
> -/**
> - Performs a bitwise OR of an 8-bit PCI configuration register with
> - an 8-bit value.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 8-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressOr8 (
> - IN UINTN Address,
> - IN UINT8 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioOr8 ((UINTN)GetPciExpressAddress (Address), OrData);
> -}
> -
> -/**
> - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
> - value.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 8-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressAnd8 (
> - IN UINTN Address,
> - IN UINT8 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAnd8 ((UINTN)GetPciExpressAddress (Address), AndData);
> -}
> -
> -/**
> - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
> - value, followed a bitwise OR with another 8-bit value.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData,
> - performs a bitwise OR between the result of the AND operation and
> - the value specified by OrData, and writes the result to the 8-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressAndThenOr8 (
> - IN UINTN Address,
> - IN UINT8 AndData,
> - IN UINT8 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAndThenOr8 (
> - (UINTN)GetPciExpressAddress (Address),
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field of a PCI configuration register.
> -
> - Reads the bit field in an 8-bit PCI configuration register. The bit field is
> - specified by the StartBit and the EndBit. The value of the bit field is
> - returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> -
> - @param Address The PCI configuration register to read.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> -
> - @return The value of the bit field read from the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldRead8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldRead8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit
> - );
> -}
> -
> -/**
> - Writes a bit field to a PCI configuration register.
> -
> - Writes Value to the bit field of the PCI configuration register. The bit
> - field is specified by the StartBit and the EndBit. All other bits in the
> - destination PCI configuration register are preserved. The new value of the
> - 8-bit register is returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> - @param Value The new value of the bit field.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldWrite8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT8 Value
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldWrite8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - Value
> - );
> -}
> -
> -/**
> - Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
> - writes the result back to the bit field in the 8-bit port.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 8-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized. Extra left bits in OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldOr8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT8 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldOr8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
> - AND, and writes the result back to the bit field in the 8-bit register.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 8-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized. Extra left bits in AndData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldAnd8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT8 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAnd8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData
> - );
> -}
> -
> -/**
> - Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
> - bitwise OR, and writes the result back to the bit field in the
> - 8-bit port.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise AND followed by a bitwise OR between the read result and
> - the value specified by AndData, and writes the result to the 8-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized. Extra left bits in both AndData and
> - OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldAndThenOr8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT8 AndData,
> - IN UINT8 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAndThenOr8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a 16-bit PCI configuration register.
> -
> - Reads and returns the 16-bit PCI configuration register specified by Address.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return The read value from the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressRead16 (
> - IN UINTN Address
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioRead16 ((UINTN)GetPciExpressAddress (Address));
> -}
> -
> -/**
> - Writes a 16-bit PCI configuration register.
> -
> - Writes the 16-bit PCI configuration register specified by Address with the
> - value specified by Value. Value is returned. This function must guarantee
> - that all PCI read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param Value The value to write.
> -
> - @return The value written to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressWrite16 (
> - IN UINTN Address,
> - IN UINT16 Value
> - )
> -{
> - UINT8 Bus, Device, Function;
> - UINT8 Offset;
> - UINT32 Data;
> -
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> -
> - Bus = GET_BUS_NUM (Address);
> - Device = GET_DEV_NUM (Address);
> - Function = GET_FUNC_NUM (Address);
> -
> - //
> - // 8-bit and 16-bit writes to root port config space is not supported due to
> - // a hardware limitation. As a workaround, perform a read-update-write
> - // sequence on the whole 32-bit word of the root port config register such
> - // that only the specified 16-bits of that word are updated.
> - //
> - if ((Bus == 0) && (Device == 0) && (Function == 0)) {
> - Offset = Address & 0x3;
> - Address &= 0xFFFFFFFC;
> - Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address));
> - Data &= ~(0xFFFF << (8 * Offset));
> - Data |= (Value << (8 * Offset));
> - MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data);
> - return Value;
> - }
> -
> - return MmioWrite16 ((UINTN)GetPciExpressAddress (Address), Value);
> -}
> -
> -/**
> - Performs a bitwise OR of a 16-bit PCI configuration register with
> - a 16-bit value.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 16-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressOr16 (
> - IN UINTN Address,
> - IN UINT16 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioOr16 ((UINTN)GetPciExpressAddress (Address), OrData);
> -}
> -
> -/**
> - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
> - value.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 16-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressAnd16 (
> - IN UINTN Address,
> - IN UINT16 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAnd16 ((UINTN)GetPciExpressAddress (Address), AndData);
> -}
> -
> -/**
> - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
> - value, followed a bitwise OR with another 16-bit value.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData,
> - performs a bitwise OR between the result of the AND operation and
> - the value specified by OrData, and writes the result to the 16-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressAndThenOr16 (
> - IN UINTN Address,
> - IN UINT16 AndData,
> - IN UINT16 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAndThenOr16 (
> - (UINTN)GetPciExpressAddress (Address),
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field of a PCI configuration register.
> -
> - Reads the bit field in a 16-bit PCI configuration register. The bit field is
> - specified by the StartBit and the EndBit. The value of the bit field is
> - returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> -
> - @param Address The PCI configuration register to read.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> -
> - @return The value of the bit field read from the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldRead16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldRead16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit
> - );
> -}
> -
> -/**
> - Writes a bit field to a PCI configuration register.
> -
> - Writes Value to the bit field of the PCI configuration register. The bit
> - field is specified by the StartBit and the EndBit. All other bits in the
> - destination PCI configuration register are preserved. The new value of the
> - 16-bit register is returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> - @param Value The new value of the bit field.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldWrite16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT16 Value
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldWrite16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - Value
> - );
> -}
> -
> -/**
> - Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
> - writes the result back to the bit field in the 16-bit port.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 16-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized. Extra left bits in OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldOr16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT16 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldOr16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
> - AND, and writes the result back to the bit field in the 16-bit register.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 16-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized. Extra left bits in AndData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldAnd16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT16 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAnd16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData
> - );
> -}
> -
> -/**
> - Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
> - bitwise OR, and writes the result back to the bit field in the
> - 16-bit port.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise AND followed by a bitwise OR between the read result and
> - the value specified by AndData, and writes the result to the 16-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized. Extra left bits in both AndData and
> - OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldAndThenOr16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT16 AndData,
> - IN UINT16 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAndThenOr16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a 32-bit PCI configuration register.
> -
> - Reads and returns the 32-bit PCI configuration register specified by Address.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return The read value from the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressRead32 (
> - IN UINTN Address
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioRead32 ((UINTN)GetPciExpressAddress (Address));
> -}
> -
> -/**
> - Writes a 32-bit PCI configuration register.
> -
> - Writes the 32-bit PCI configuration register specified by Address with the
> - value specified by Value. Value is returned. This function must guarantee
> - that all PCI read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param Value The value to write.
> -
> - @return The value written to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressWrite32 (
> - IN UINTN Address,
> - IN UINT32 Value
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Value);
> -}
> -
> -/**
> - Performs a bitwise OR of a 32-bit PCI configuration register with
> - a 32-bit value.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 32-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressOr32 (
> - IN UINTN Address,
> - IN UINT32 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioOr32 ((UINTN)GetPciExpressAddress (Address), OrData);
> -}
> -
> -/**
> - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
> - value.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 32-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressAnd32 (
> - IN UINTN Address,
> - IN UINT32 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAnd32 ((UINTN)GetPciExpressAddress (Address), AndData);
> -}
> -
> -/**
> - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
> - value, followed a bitwise OR with another 32-bit value.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData,
> - performs a bitwise OR between the result of the AND operation and
> - the value specified by OrData, and writes the result to the 32-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressAndThenOr32 (
> - IN UINTN Address,
> - IN UINT32 AndData,
> - IN UINT32 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAndThenOr32 (
> - (UINTN)GetPciExpressAddress (Address),
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field of a PCI configuration register.
> -
> - Reads the bit field in a 32-bit PCI configuration register. The bit field is
> - specified by the StartBit and the EndBit. The value of the bit field is
> - returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> -
> - @param Address The PCI configuration register to read.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> -
> - @return The value of the bit field read from the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldRead32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldRead32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit
> - );
> -}
> -
> -/**
> - Writes a bit field to a PCI configuration register.
> -
> - Writes Value to the bit field of the PCI configuration register. The bit
> - field is specified by the StartBit and the EndBit. All other bits in the
> - destination PCI configuration register are preserved. The new value of the
> - 32-bit register is returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> - @param Value The new value of the bit field.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldWrite32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT32 Value
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldWrite32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - Value
> - );
> -}
> -
> -/**
> - Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
> - writes the result back to the bit field in the 32-bit port.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 32-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized. Extra left bits in OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldOr32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT32 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldOr32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
> - AND, and writes the result back to the bit field in the 32-bit register.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 32-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized. Extra left bits in AndData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldAnd32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT32 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAnd32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData
> - );
> -}
> -
> -/**
> - Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
> - bitwise OR, and writes the result back to the bit field in the
> - 32-bit port.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise AND followed by a bitwise OR between the read result and
> - the value specified by AndData, and writes the result to the 32-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized. Extra left bits in both AndData and
> - OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldAndThenOr32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT32 AndData,
> - IN UINT32 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAndThenOr32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a range of PCI configuration registers into a caller supplied buffer.
> -
> - Reads the range of PCI configuration registers specified by StartAddress and
> - Size into the buffer specified by Buffer. This function only allows the PCI
> - configuration registers from a single PCI function to be read. Size is
> - returned. When possible 32-bit PCI configuration read cycles are used to read
> - from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
> - and 16-bit PCI configuration read cycles may be used at the beginning and the
> - end of the range.
> -
> - If StartAddress > 0x0FFFFFFF, then ASSERT().
> - If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> - If Size > 0 and Buffer is NULL, then ASSERT().
> -
> - @param StartAddress The starting address that encodes the PCI Bus, Device,
> - Function and Register.
> - @param Size The size in bytes of the transfer.
> - @param Buffer The pointer to a buffer receiving the data read.
> -
> - @return Size read data from StartAddress.
> -
> -**/
> -UINTN
> -EFIAPI
> -PciExpressReadBuffer (
> - IN UINTN StartAddress,
> - IN UINTN Size,
> - OUT VOID *Buffer
> - )
> -{
> - UINTN ReturnValue;
> -
> - ASSERT_INVALID_PCI_ADDRESS (StartAddress);
> - ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
> -
> - if (Size == 0) {
> - return Size;
> - }
> -
> - ASSERT (Buffer != NULL);
> -
> - //
> - // Save Size for return
> - //
> - ReturnValue = Size;
> -
> - if ((StartAddress & 1) != 0) {
> - //
> - // Read a byte if StartAddress is byte aligned
> - //
> - *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
> - StartAddress += sizeof (UINT8);
> - Size -= sizeof (UINT8);
> - Buffer = (UINT8*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
> - //
> - // Read a word if StartAddress is word aligned
> - //
> - WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
> -
> - StartAddress += sizeof (UINT16);
> - Size -= sizeof (UINT16);
> - Buffer = (UINT16*)Buffer + 1;
> - }
> -
> - while (Size >= sizeof (UINT32)) {
> - //
> - // Read as many double words as possible
> - //
> - WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));
> -
> - StartAddress += sizeof (UINT32);
> - Size -= sizeof (UINT32);
> - Buffer = (UINT32*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT16)) {
> - //
> - // Read the last remaining word if exist
> - //
> - WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
> - StartAddress += sizeof (UINT16);
> - Size -= sizeof (UINT16);
> - Buffer = (UINT16*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT8)) {
> - //
> - // Read the last remaining byte if exist
> - //
> - *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
> - }
> -
> - return ReturnValue;
> -}
> -
> -/**
> - Copies the data in a caller supplied buffer to a specified range of PCI
> - configuration space.
> -
> - Writes the range of PCI configuration registers specified by StartAddress and
> - Size from the buffer specified by Buffer. This function only allows the PCI
> - configuration registers from a single PCI function to be written. Size is
> - returned. When possible 32-bit PCI configuration write cycles are used to
> - write from StartAdress to StartAddress + Size. Due to alignment restrictions,
> - 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
> - and the end of the range.
> -
> - If StartAddress > 0x0FFFFFFF, then ASSERT().
> - If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> - If Size > 0 and Buffer is NULL, then ASSERT().
> -
> - @param StartAddress The starting address that encodes the PCI Bus, Device,
> - Function and Register.
> - @param Size The size in bytes of the transfer.
> - @param Buffer The pointer to a buffer containing the data to write.
> -
> - @return Size written to StartAddress.
> -
> -**/
> -UINTN
> -EFIAPI
> -PciExpressWriteBuffer (
> - IN UINTN StartAddress,
> - IN UINTN Size,
> - IN VOID *Buffer
> - )
> -{
> - UINTN ReturnValue;
> -
> - ASSERT_INVALID_PCI_ADDRESS (StartAddress);
> - ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
> -
> - if (Size == 0) {
> - return 0;
> - }
> -
> - ASSERT (Buffer != NULL);
> -
> - //
> - // Save Size for return
> - //
> - ReturnValue = Size;
> -
> - if ((StartAddress & 1) != 0) {
> - //
> - // Write a byte if StartAddress is byte aligned
> - //
> - PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
> - StartAddress += sizeof (UINT8);
> - Size -= sizeof (UINT8);
> - Buffer = (UINT8*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
> - //
> - // Write a word if StartAddress is word aligned
> - //
> - PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
> - StartAddress += sizeof (UINT16);
> - Size -= sizeof (UINT16);
> - Buffer = (UINT16*)Buffer + 1;
> - }
> -
> - while (Size >= sizeof (UINT32)) {
> - //
> - // Write as many double words as possible
> - //
> - PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));
> - StartAddress += sizeof (UINT32);
> - Size -= sizeof (UINT32);
> - Buffer = (UINT32*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT16)) {
> - //
> - // Write the last remaining word if exist
> - //
> - PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
> - StartAddress += sizeof (UINT16);
> - Size -= sizeof (UINT16);
> - Buffer = (UINT16*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT8)) {
> - //
> - // Write the last remaining byte if exist
> - //
> - PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
> - }
> -
> - return ReturnValue;
> -}
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
> deleted file mode 100644
> index acb6fb6219..0000000000
> --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -## @file
> -# Instance of PCI Express Library using the 256 MB PCI Express MMIO window.
> -#
> -# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform
> -# PCI Configuration cycles. Layers on top of an I/O Library instance.
> -#
> -# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
> -#
> -# This library is inherited from MdePkg/Library/BasePciExpressLib. On
> -# NeoverseN1 SoC, with the unmodified version of this library, a slave error is
> -# generated when host accesses the config space of a non-available device or
> -# unimplemented function on a given bus. In order to resolve this for
> -# NeoverseN1 SoC, a modified version of the MdePkg/Library/BasePciExpressLib
> -# library is used. The modification includes a check to determine whether the
> -# incoming PCI address can be safely accessed.
> -#
> -# In addition to this, the NeoverseN1 SoC has two other limitations which
> -# affect the access to the PCIe root port:
> -# 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
> -# from rest of the downstream hierarchy ECAM space.
> -# 2. Root port ECAM space is not capable of 8bit/16bit writes.
> -# This library includes workaround for these limitations as well.
> -#
> -# Copyright (c) 2020, ARM Limited. All rights reserved.
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[Defines]
> - INF_VERSION = 0x0001001A
> - BASE_NAME = BasePciExpressLib
> - FILE_GUID = b378dd06-de7f-4e8c-8fb0-5126adfb34bf
> - MODULE_TYPE = BASE
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = PciExpressLib
> -
> -[Sources]
> - PciExpressLib.c
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> -
> -[FixedPcd]
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
> -
> -[LibraryClasses]
> - BaseLib
> - DebugLib
> - IoLib
> - PcdLib
> -
> -[Pcd]
> - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
prev parent reply other threads:[~2022-01-19 15:02 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-22 1:14 [PATCH v5 0/4] Enable CCIX port as PCIe root host on N1SDP Khasim Mohammed
2021-12-22 1:14 ` [PATCH v5 1/4] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library Khasim Mohammed
2021-12-22 8:52 ` [edk2-devel] " PierreGondois
2022-01-19 15:01 ` Sami Mujawar
2021-12-22 1:14 ` [PATCH v5 2/4] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports Khasim Mohammed
2021-12-22 8:52 ` [edk2-devel] " PierreGondois
2022-01-19 15:01 ` Sami Mujawar
2021-12-22 1:14 ` [PATCH v5 3/4] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support Khasim Mohammed
2021-12-22 8:52 ` [edk2-devel] " PierreGondois
2022-01-19 15:02 ` Sami Mujawar
2021-12-22 1:14 ` [PATCH v5 4/4] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead Khasim Mohammed
2021-12-22 8:51 ` [edk2-devel] " PierreGondois
2022-01-19 15:02 ` Sami Mujawar [this message]
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