From: "PierreGondois" <pierre.gondois@arm.com>
To: devel@edk2.groups.io, khasim.mohammed@arm.com
Cc: nd@arm.com, Sami Mujawar <Sami.mujawar@arm.com>
Subject: Re: [edk2-devel] [PATCH v5 3/4] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support
Date: Wed, 22 Dec 2021 09:52:06 +0100 [thread overview]
Message-ID: <2ea2bedc-0d59-74e5-f3fe-b78264e94a49@arm.com> (raw)
In-Reply-To: <20211222011440.3687-4-khasim.mohammed@arm.com>
Hi Khasim,
Everything looks good to me:
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Regards,
Pierre
On 12/22/21 2:14 AM, Khasim Mohammed via groups.io wrote:
> This patch enables CCIX root complex support by updating
> the root complex node info in PciHostBridge library.
>
> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
> ---
> .../PciHostBridgeLib/PciHostBridgeLib.c | 71 +++++++++++++++++--
> .../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++-
> 2 files changed, 76 insertions(+), 6 deletions(-)
>
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> index 9332939f63..c3a14a6c17 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> @@ -1,7 +1,7 @@
> /** @file
> * PCI Host Bridge Library instance for ARM Neoverse N1 platform
> *
> -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
> +* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
> *
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> @@ -16,6 +16,8 @@
> #include <Protocol/PciHostBridgeResourceAllocation.h>
> #include <Protocol/PciRootBridgeIo.h>
>
> +#define ROOT_COMPLEX_NUM 2
> +
> GLOBAL_REMOVE_IF_UNREFERENCED
> STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
> L"Mem", L"I/O", L"Bus"
> @@ -28,7 +30,7 @@ typedef struct {
> } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
> #pragma pack ()
>
> -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = {
> // PCIe
> {
> {
> @@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> 0
> }
> }
> - }
> + },
> + //CCIX
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID(0x0A09), // CCIX
> + 0
> + },
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> };
>
> -STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
> +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = {
> {
> 0, // Segment
> 0, // Supports
> @@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
> 0
> },
> (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
> - }
> + },
> + {
> + 1, // Segment
> + 0, // Supports
> + 0, // Attributes
> + TRUE, // DmaAbove4G
> + FALSE, // NoExtendedConfigSpace
> + FALSE, // ResourceAssigned
> + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
> + {
> + // Bus
> + FixedPcdGet32 (PcdCcixBusMin),
> + FixedPcdGet32 (PcdCcixBusMax)
> + }, {
> + // Io
> + FixedPcdGet64 (PcdCcixIoBase),
> + FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1
> + }, {
> + // Mem
> + FixedPcdGet32 (PcdCcixMmio32Base),
> + FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) - 1
> + }, {
> + // MemAbove4G
> + FixedPcdGet64 (PcdCcixMmio64Base),
> + FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) - 1
> + }, {
> + // PMem
> + MAX_UINT64,
> + 0
> + }, {
> + // PMemAbove4G
> + MAX_UINT64,
> + 0
> + },
> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
> + },
> };
>
> /**
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> index 3ff1c592f2..3356c3ad35 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> @@ -1,7 +1,7 @@
> ## @file
> # PCI Host Bridge Library instance for ARM Neoverse N1 platform.
> #
> -# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
> +# Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -42,6 +42,15 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size
>
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size
> +
> [Protocols]
> gEfiCpuIo2ProtocolGuid
>
next prev parent reply other threads:[~2021-12-22 8:52 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-22 1:14 [PATCH v5 0/4] Enable CCIX port as PCIe root host on N1SDP Khasim Mohammed
2021-12-22 1:14 ` [PATCH v5 1/4] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library Khasim Mohammed
2021-12-22 8:52 ` [edk2-devel] " PierreGondois
2022-01-19 15:01 ` Sami Mujawar
2021-12-22 1:14 ` [PATCH v5 2/4] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports Khasim Mohammed
2021-12-22 8:52 ` [edk2-devel] " PierreGondois
2022-01-19 15:01 ` Sami Mujawar
2021-12-22 1:14 ` [PATCH v5 3/4] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support Khasim Mohammed
2021-12-22 8:52 ` PierreGondois [this message]
2022-01-19 15:02 ` [edk2-devel] " Sami Mujawar
2021-12-22 1:14 ` [PATCH v5 4/4] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead Khasim Mohammed
2021-12-22 8:51 ` [edk2-devel] " PierreGondois
2022-01-19 15:02 ` Sami Mujawar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=2ea2bedc-0d59-74e5-f3fe-b78264e94a49@arm.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox