From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.17180.1640163121447862872 for ; Wed, 22 Dec 2021 00:52:02 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pierre.gondois@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 29FFCD6E; Wed, 22 Dec 2021 00:52:01 -0800 (PST) Received: from [192.168.1.16] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3184B3F718; Wed, 22 Dec 2021 00:51:59 -0800 (PST) Subject: Re: [edk2-devel] [PATCH v5 3/4] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support To: devel@edk2.groups.io, khasim.mohammed@arm.com Cc: nd@arm.com, Sami Mujawar References: <20211222011440.3687-1-khasim.mohammed@arm.com> <20211222011440.3687-4-khasim.mohammed@arm.com> From: "PierreGondois" Message-ID: <2ea2bedc-0d59-74e5-f3fe-b78264e94a49@arm.com> Date: Wed, 22 Dec 2021 09:52:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20211222011440.3687-4-khasim.mohammed@arm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Content-Language: en-US Hi Khasim, Everything looks good to me: Reviewed-by: Pierre Gondois Regards, Pierre On 12/22/21 2:14 AM, Khasim Mohammed via groups.io wrote: > This patch enables CCIX root complex support by updating > the root complex node info in PciHostBridge library. > > Signed-off-by: Khasim Syed Mohammed > --- > .../PciHostBridgeLib/PciHostBridgeLib.c | 71 +++++++++++++++++-- > .../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++- > 2 files changed, 76 insertions(+), 6 deletions(-) > > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c > index 9332939f63..c3a14a6c17 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c > @@ -1,7 +1,7 @@ > /** @file > * PCI Host Bridge Library instance for ARM Neoverse N1 platform > * > -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. > +* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.
> * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -16,6 +16,8 @@ > #include > #include > > +#define ROOT_COMPLEX_NUM 2 > + > GLOBAL_REMOVE_IF_UNREFERENCED > STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { > L"Mem", L"I/O", L"Bus" > @@ -28,7 +30,7 @@ typedef struct { > } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; > #pragma pack () > > -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { > +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = { > // PCIe > { > { > @@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { > 0 > } > } > - } > + }, > + //CCIX > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) > + } > + }, > + EISA_PNP_ID(0x0A09), // CCIX > + 0 > + }, > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > }; > > -STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = { > +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = { > { > 0, // Segment > 0, // Supports > @@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = { > 0 > }, > (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] > - } > + }, > + { > + 1, // Segment > + 0, // Supports > + 0, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { > + // Bus > + FixedPcdGet32 (PcdCcixBusMin), > + FixedPcdGet32 (PcdCcixBusMax) > + }, { > + // Io > + FixedPcdGet64 (PcdCcixIoBase), > + FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1 > + }, { > + // Mem > + FixedPcdGet32 (PcdCcixMmio32Base), > + FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) - 1 > + }, { > + // MemAbove4G > + FixedPcdGet64 (PcdCcixMmio64Base), > + FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) - 1 > + }, { > + // PMem > + MAX_UINT64, > + 0 > + }, { > + // PMemAbove4G > + MAX_UINT64, > + 0 > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] > + }, > }; > > /** > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf > index 3ff1c592f2..3356c3ad35 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf > @@ -1,7 +1,7 @@ > ## @file > # PCI Host Bridge Library instance for ARM Neoverse N1 platform. > # > -# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. > +# Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -42,6 +42,15 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size > > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size > + > [Protocols] > gEfiCpuIo2ProtocolGuid >