* [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity
@ 2021-07-02 12:25 Ashraf Ali S
2021-07-19 3:14 ` Ni, Ray
0 siblings, 1 reply; 8+ messages in thread
From: Ashraf Ali S @ 2021-07-02 12:25 UTC (permalink / raw)
To: devel
Cc: Ashraf Ali S, Ray Ni, Rahul Kumar, Debkumar De, Harry Han,
Catharine West, Sangeetha V
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473
X64 Reset Vector Code can access the memory range till 4GB using the
Linear-Address Translation to a 2-MByte Page, when user wants to use
more than 4G using 2M Page it will leads to use more number of Page
table entries. using the 1-GByte Page table user can use more than
4G Memory by reducing the page table entries using 1-GByte Page,
this patch attached can access memory range till 512GByte.
Build Scrips for Reset Vector currently based on Python 2
which is already EOL, needs to modify the build script based on
Python 3, update the Binary accordingly.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Harry Han <harry.han@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Cc: Sangeetha V <sangeetha.v@intel.com>
Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
---
.../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 516 -> 484 bytes
.../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes
.../Vtf0/Bin/ResetVector.ia32.serial.raw | Bin 884 -> 868 bytes
.../Vtf0/Bin/ResetVector.x64.port80.raw | Bin 28676 -> 12292 bytes
.../ResetVector/Vtf0/Bin/ResetVector.x64.raw | Bin 28676 -> 12292 bytes
.../Vtf0/Bin/ResetVector.x64.serial.raw | Bin 28676 -> 12292 bytes
UefiCpuPkg/ResetVector/Vtf0/Build.py | 11 +--
.../ResetVector/Vtf0/Ia32/PageTables64.asm | 2 +-
UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 2 +-
.../Vtf0/Tools/FixupForRawSection.py | 4 +-
UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 4 +-
.../ResetVector/Vtf0/X64/1GPageTables.asm | 64 ++++++++++++++++++
.../X64/{PageTables.asm => 2MPageTables.asm} | 0
13 files changed, 77 insertions(+), 10 deletions(-)
create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => 2MPageTables.asm} (100%)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
index 2c6ff655ded2a5855ca8f4428d559a7727eb6983..79b23c047bdc6e552d77d5c9e9aeae21ff04d91d 100644
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diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.serial.raw b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.serial.raw
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diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py b/UefiCpuPkg/ResetVector/Vtf0/Build.py
index 343c53b5ff..29f29ff0c2 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Build.py
+++ b/UefiCpuPkg/ResetVector/Vtf0/Build.py
@@ -1,7 +1,7 @@
## @file
# Automate the process of building the various reset vector types
#
-# Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -32,16 +32,19 @@ for arch in ('ia32', 'x64'):
'-o', output,
'Vtf0.nasmb',
)
+ print(f"Command : {' '.join(commandLine)}")
ret = RunCommand(commandLine)
- print '\tASM\t' + output
- if ret != 0: sys.exit(ret)
+ if ret != 0:
+ print(f"something went wrong while executing the {commandLine[-1]}")
+ sys.exit()
+ print('\tASM\t' + output)
commandLine = (
'python',
'Tools/FixupForRawSection.py',
output,
)
- print '\tFIXUP\t' + output
+ print('\tFIXUP\t' + output)
ret = RunCommand(commandLine)
if ret != 0: sys.exit(ret)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
index 87a4125d4b..9cc6f56c17 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
@@ -15,7 +15,7 @@ BITS 32
SetCr3ForPageTables64:
;
- ; These pages are built into the ROM image in X64/PageTables.asm
+ ; These pages are built into the ROM image in X64/1GPageTables.asm
;
mov eax, ADDR_OF(TopLevelPageDirectory)
mov cr3, eax
diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
index e6e5b54243..eb9dd24ee2 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
+++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
@@ -29,7 +29,7 @@ EBP/RBP - Pointer to the start of the Boot Firmware Volume
=== HOW TO BUILD VTF0 ===
Dependencies:
-* Python 2.5~2.7
+* Python 3.0 or newer
* Nasm 2.03 or newer
To rebuild the VTF0 binaries:
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py
index c77438a0ce..de771eba22 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py
+++ b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py
@@ -1,7 +1,7 @@
## @file
# Apply fixup to VTF binary image for FFS Raw section
#
-# Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2008 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -15,6 +15,6 @@ c = ((len(d) + 4 + 7) & ~7) - 4
if c > len(d):
c -= len(d)
f = open(sys.argv[1], 'wb')
- f.write('\x90' * c)
+ f.write(b'\x90' * c)
f.write(d)
f.close()
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
index 493738c79c..0625efc456 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
+++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
@@ -2,7 +2,7 @@
; @file
; This file includes all other code files to assemble the reset vector code
;
-; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2008 - 2021, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
@@ -36,7 +36,7 @@
%include "PostCodes.inc"
%ifdef ARCH_X64
-%include "X64/PageTables.asm"
+%include "X64/1GPageTables.asm"
%endif
%ifdef DEBUG_PORT80
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
new file mode 100644
index 0000000000..8ae6c4c98c
--- /dev/null
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
@@ -0,0 +1,64 @@
+;------------------------------------------------------------------------------
+; @file
+; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB)
+;
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+; Linear-Address Translation to a 1-GByte Page
+;
+;------------------------------------------------------------------------------
+
+BITS 64
+
+%define ALIGN_TOP_TO_4K_FOR_PAGING
+
+%define PAGE_PRESENT 0x01
+%define PAGE_READ_WRITE 0x02
+%define PAGE_USER_SUPERVISOR 0x04
+%define PAGE_WRITE_THROUGH 0x08
+%define PAGE_CACHE_DISABLE 0x010
+%define PAGE_ACCESSED 0x020
+%define PAGE_DIRTY 0x040
+%define PAGE_PAT 0x080
+%define PAGE_GLOBAL 0x0100
+%define PAGE_1G 0x80
+
+%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
+ PAGE_READ_WRITE + \
+ PAGE_PRESENT)
+
+%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \
+ PAGE_READ_WRITE + \
+ PAGE_PRESENT + \
+ PAGE_1G)
+
+%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
+%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
+
+%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
+ PAGE_PDP_ATTR)
+
+%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR)
+
+ALIGN 16
+
+TopLevelPageDirectory:
+
+ ;
+ ; Top level Page Directory Pointers (1 * 512GB entry)
+ ;
+ DQ PDP(0x1000)
+
+
+ TIMES 0x1000-PGTBLS_OFFSET($) DB 0
+ ;
+ ; Next level Page Directory Pointers (512 * 1GB entries => 512GB)
+ ;
+%assign i 0
+%rep 512
+ DQ PDP_1G(i)
+ %assign i i+1
+%endrep
+
+
+EndOfPageTables:
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm
similarity index 100%
rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
rename to UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm
--
2.32.0.windows.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity 2021-07-02 12:25 [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity Ashraf Ali S @ 2021-07-19 3:14 ` Ni, Ray 2021-07-19 7:09 ` Ard Biesheuvel 0 siblings, 1 reply; 8+ messages in thread From: Ni, Ray @ 2021-07-19 3:14 UTC (permalink / raw) To: S, Ashraf Ali, devel@edk2.groups.io, Ard Biesheuvel, Justen, Jordan L, Agyeman, Prince Cc: Kumar, Rahul1, De, Debkumar, Han, Harry, West, Catharine, V, Sangeetha This change generates the reset vector binary which only contains 1G page table. If a platform doesn't support 1G page table, this will cause system hang. To Ard and Jordan, Can you evaluate whether this change impacts OVMF? To Prince, Can you evaluate whether this change impacts SimicsOpenBoardPkg? Thanks, Ray -----Original Message----- From: S, Ashraf Ali <ashraf.ali.s@intel.com> Sent: Friday, July 2, 2021 8:25 PM To: devel@edk2.groups.io Cc: S, Ashraf Ali <ashraf.ali.s@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; West, Catharine <catharine.west@intel.com>; V, Sangeetha <sangeetha.v@intel.com> Subject: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473 X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when user wants to use more than 4G using 2M Page it will leads to use more number of Page table entries. using the 1-GByte Page table user can use more than 4G Memory by reducing the page table entries using 1-GByte Page, this patch attached can access memory range till 512GByte. Build Scrips for Reset Vector currently based on Python 2 which is already EOL, needs to modify the build script based on Python 3, update the Binary accordingly. Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Cc: Sangeetha V <sangeetha.v@intel.com> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com> --- .../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 516 -> 484 bytes .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes .../Vtf0/Bin/ResetVector.ia32.serial.raw | Bin 884 -> 868 bytes .../Vtf0/Bin/ResetVector.x64.port80.raw | Bin 28676 -> 12292 bytes .../ResetVector/Vtf0/Bin/ResetVector.x64.raw | Bin 28676 -> 12292 bytes .../Vtf0/Bin/ResetVector.x64.serial.raw | Bin 28676 -> 12292 bytes UefiCpuPkg/ResetVector/Vtf0/Build.py | 11 +-- .../ResetVector/Vtf0/Ia32/PageTables64.asm | 2 +- UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 2 +- .../Vtf0/Tools/FixupForRawSection.py | 4 +- UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 4 +- .../ResetVector/Vtf0/X64/1GPageTables.asm | 64 ++++++++++++++++++ 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z9R9?~+uwiX$~`exuAIK*{?j+l>3biz{`4*LZ57d{pMBVR-05eXzPS$%o_hM0e#iO4 z-Zx!yl|1K~Y5VAFw*NPu>jxZ8+LiY1s~6g>m;cwT=R9KT36I!%{N<l{UHrsdZ+qPr zUiqjqr>}eRnR`C$a6KFj?aVu#beNVK<DPuX;Vf^NM}9E3U2{y&zGnLu9^;vN9v64r ze^=i%cRg^|TTWhbn5#=qjXJ!?&o3@lC-CZc=zrnA?0X*e>weB}jn}{MWe<MP>p$^j z58iO*;u}u#y@!kU<R`D3Jo?JXOW%9t%E>M7JAA3bjNX3F;bkBC7rNV@_NLpP_Qu<v j_J-Rp&Xu=6c;CbCb@e@7{+Tb1OP3z}mY;w3OP78Y>oK+# diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py b/UefiCpuPkg/ResetVector/Vtf0/Build.py index 343c53b5ff..29f29ff0c2 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Build.py +++ b/UefiCpuPkg/ResetVector/Vtf0/Build.py @@ -1,7 +1,7 @@ ## @file # Automate the process of building the various reset vector types # -# Copyright (c) 2009, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2009 - 2021, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -32,16 +32,19 @@ for arch in ('ia32', 'x64'): '-o', output, 'Vtf0.nasmb', ) + print(f"Command : {' '.join(commandLine)}") ret = RunCommand(commandLine) - print '\tASM\t' + output - if ret != 0: sys.exit(ret) + if ret != 0: + print(f"something went wrong while executing the {commandLine[-1]}") + sys.exit() + print('\tASM\t' + output) commandLine = ( 'python', 'Tools/FixupForRawSection.py', output, ) - print '\tFIXUP\t' + output + print('\tFIXUP\t' + output) ret = RunCommand(commandLine) if ret != 0: sys.exit(ret) diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm index 87a4125d4b..9cc6f56c17 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm @@ -15,7 +15,7 @@ BITS 32 SetCr3ForPageTables64: ; - ; These pages are built into the ROM image in X64/PageTables.asm + ; These pages are built into the ROM image in X64/1GPageTables.asm ; mov eax, ADDR_OF(TopLevelPageDirectory) mov cr3, eax diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt index e6e5b54243..eb9dd24ee2 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt +++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt @@ -29,7 +29,7 @@ EBP/RBP - Pointer to the start of the Boot Firmware Volume === HOW TO BUILD VTF0 === Dependencies: -* Python 2.5~2.7 +* Python 3.0 or newer * Nasm 2.03 or newer To rebuild the VTF0 binaries: diff --git a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py index c77438a0ce..de771eba22 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py +++ b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py @@ -1,7 +1,7 @@ ## @file # Apply fixup to VTF binary image for FFS Raw section # -# Copyright (c) 2008, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2008 - 2021, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -15,6 +15,6 @@ c = ((len(d) + 4 + 7) & ~7) - 4 if c > len(d): c -= len(d) f = open(sys.argv[1], 'wb') - f.write('\x90' * c) + f.write(b'\x90' * c) f.write(d) f.close() diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb index 493738c79c..0625efc456 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb @@ -2,7 +2,7 @@ ; @file ; This file includes all other code files to assemble the reset vector code ; -; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2008 - 2021, Intel Corporation. All rights +reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------ @@ -36,7 +36,7 @@ %include "PostCodes.inc" %ifdef ARCH_X64 -%include "X64/PageTables.asm" +%include "X64/1GPageTables.asm" %endif %ifdef DEBUG_PORT80 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm new file mode 100644 index 0000000000..8ae6c4c98c --- /dev/null +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm @@ -0,0 +1,64 @@ +;---------------------------------------------------------------------- +-------- +; @file +; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 +(512GB) ; ; Copyright (c) 2021, Intel Corporation. All rights +reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; +Linear-Address Translation to a 1-GByte Page ; +;---------------------------------------------------------------------- +-------- + +BITS 64 + +%define ALIGN_TOP_TO_4K_FOR_PAGING + +%define PAGE_PRESENT 0x01 +%define PAGE_READ_WRITE 0x02 +%define PAGE_USER_SUPERVISOR 0x04 +%define PAGE_WRITE_THROUGH 0x08 +%define PAGE_CACHE_DISABLE 0x010 +%define PAGE_ACCESSED 0x020 +%define PAGE_DIRTY 0x040 +%define PAGE_PAT 0x080 +%define PAGE_GLOBAL 0x0100 +%define PAGE_1G 0x80 + +%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT) + +%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT + \ + PAGE_1G) + +%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define +PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) + +%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ + PAGE_PDP_ATTR) + +%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR) + +ALIGN 16 + +TopLevelPageDirectory: + + ; + ; Top level Page Directory Pointers (1 * 512GB entry) + ; + DQ PDP(0x1000) + + + TIMES 0x1000-PGTBLS_OFFSET($) DB 0 + ; + ; Next level Page Directory Pointers (512 * 1GB entries => 512GB) + ; +%assign i 0 +%rep 512 + DQ PDP_1G(i) + %assign i i+1 +%endrep + + +EndOfPageTables: diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm similarity index 100% rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm rename to UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm -- 2.32.0.windows.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity 2021-07-19 3:14 ` Ni, Ray @ 2021-07-19 7:09 ` Ard Biesheuvel 2021-07-19 20:01 ` [edk2-devel] " Lendacky, Thomas 2021-07-19 20:02 ` Dov Murik 0 siblings, 2 replies; 8+ messages in thread From: Ard Biesheuvel @ 2021-07-19 7:09 UTC (permalink / raw) To: Ni, Ray, Brijesh Singh, Dov Murik, James Bottomley, Erdem Aktas Cc: S, Ashraf Ali, devel@edk2.groups.io, Ard Biesheuvel, Justen, Jordan L, Agyeman, Prince, Kumar, Rahul1, De, Debkumar, Han, Harry, West, Catharine, V, Sangeetha On Mon, 19 Jul 2021 at 05:14, Ni, Ray <ray.ni@intel.com> wrote: > > This change generates the reset vector binary which only contains 1G page table. If a platform doesn't support 1G page table, this will cause system hang. > > To Ard and Jordan, > Can you evaluate whether this change impacts OVMF? > I don't have a clue, sorry, and I wouldn't know where to begin looking. Brijesh, Dov, James, Erdem: after Laszlo's sudden departure, I will be needing help reviewing OVMF patches that are highly specific to SEV/SNP or x86 in general. Please take a look. > To Prince, > Can you evaluate whether this change impacts SimicsOpenBoardPkg? > > Thanks, > Ray > > -----Original Message----- > From: S, Ashraf Ali <ashraf.ali.s@intel.com> > Sent: Friday, July 2, 2021 8:25 PM > To: devel@edk2.groups.io > Cc: S, Ashraf Ali <ashraf.ali.s@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; West, Catharine <catharine.west@intel.com>; V, Sangeetha <sangeetha.v@intel.com> > Subject: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473 > > X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when user wants to use more than 4G using 2M Page it will leads to use more number of Page table entries. using the 1-GByte Page table user can use more than 4G Memory by reducing the page table entries using 1-GByte Page, this patch attached can access memory range till 512GByte. > Build Scrips for Reset Vector currently based on Python 2 which is already EOL, needs to modify the build script based on Python 3, update the Binary accordingly. > > Cc: Ray Ni <ray.ni@intel.com> > Cc: Rahul Kumar <rahul1.kumar@intel.com> > Cc: Debkumar De <debkumar.de@intel.com> > Cc: Harry Han <harry.han@intel.com> > Cc: Catharine West <catharine.west@intel.com> > Cc: Sangeetha V <sangeetha.v@intel.com> > Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com> > --- > .../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 516 -> 484 bytes > .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes > .../Vtf0/Bin/ResetVector.ia32.serial.raw | Bin 884 -> 868 bytes > .../Vtf0/Bin/ResetVector.x64.port80.raw | Bin 28676 -> 12292 bytes > .../ResetVector/Vtf0/Bin/ResetVector.x64.raw | Bin 28676 -> 12292 bytes > .../Vtf0/Bin/ResetVector.x64.serial.raw | Bin 28676 -> 12292 bytes > UefiCpuPkg/ResetVector/Vtf0/Build.py | 11 +-- > .../ResetVector/Vtf0/Ia32/PageTables64.asm | 2 +- > UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 2 +- > .../Vtf0/Tools/FixupForRawSection.py | 4 +- > UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 4 +- > .../ResetVector/Vtf0/X64/1GPageTables.asm | 64 ++++++++++++++++++ > .../X64/{PageTables.asm => 2MPageTables.asm} | 0 > 13 files changed, 77 insertions(+), 10 deletions(-) create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm > rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => 2MPageTables.asm} (100%) > > diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw > index 2c6ff655ded2a5855ca8f4428d559a7727eb6983..79b23c047bdc6e552d77d5c9e9aeae21ff04d91d 100644 GIT binary patch delta 410 > zcmZo+dBQ9-0SF8a=rRZ}FxWCMF#Invo+zYJ-&~=>P<pEKFmr@L>EYMB8#X*^*s&i7 > zI*-2o*Lifq#%B#L{TUe;3~zVd>wJ;c9c#dNqsaO-vqO<t>wyxZ<^$|Sx+*`qBE-KP > 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j_J-Rp&Xu=6c;CbCb@e@7{+Tb1OP3z}mY;w3OP78Y>oK+# > > diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py b/UefiCpuPkg/ResetVector/Vtf0/Build.py > index 343c53b5ff..29f29ff0c2 100644 > --- a/UefiCpuPkg/ResetVector/Vtf0/Build.py > +++ b/UefiCpuPkg/ResetVector/Vtf0/Build.py > @@ -1,7 +1,7 @@ > ## @file > # Automate the process of building the various reset vector types # -# Copyright (c) 2009, Intel Corporation. All rights reserved.<BR> > +# Copyright (c) 2009 - 2021, Intel Corporation. All rights > +reserved.<BR> > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -32,16 +32,19 @@ for arch in ('ia32', 'x64'): > '-o', output, > 'Vtf0.nasmb', > ) > + print(f"Command : {' '.join(commandLine)}") > ret = RunCommand(commandLine) > - print '\tASM\t' + output > - if ret != 0: sys.exit(ret) > + if ret != 0: > + print(f"something went wrong while executing the {commandLine[-1]}") > + sys.exit() > + print('\tASM\t' + output) > > commandLine = ( > 'python', > 'Tools/FixupForRawSection.py', > output, > ) > - print '\tFIXUP\t' + output > + print('\tFIXUP\t' + output) > ret = RunCommand(commandLine) > if ret != 0: sys.exit(ret) > > diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > index 87a4125d4b..9cc6f56c17 100644 > --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > @@ -15,7 +15,7 @@ BITS 32 > SetCr3ForPageTables64: > > ; > - ; These pages are built into the ROM image in X64/PageTables.asm > + ; These pages are built into the ROM image in X64/1GPageTables.asm > ; > mov eax, ADDR_OF(TopLevelPageDirectory) > mov cr3, eax > diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt > index e6e5b54243..eb9dd24ee2 100644 > --- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt > +++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt > @@ -29,7 +29,7 @@ EBP/RBP - Pointer to the start of the Boot Firmware Volume === HOW TO BUILD VTF0 === > > Dependencies: > -* Python 2.5~2.7 > +* Python 3.0 or newer > * Nasm 2.03 or newer > > To rebuild the VTF0 binaries: > diff --git a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py > index c77438a0ce..de771eba22 100644 > --- a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py > +++ b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py > @@ -1,7 +1,7 @@ > ## @file > # Apply fixup to VTF binary image for FFS Raw section # -# Copyright (c) 2008, Intel Corporation. All rights reserved.<BR> > +# Copyright (c) 2008 - 2021, Intel Corporation. All rights > +reserved.<BR> > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -15,6 +15,6 @@ c = ((len(d) + 4 + 7) & ~7) - 4 if c > len(d): > c -= len(d) > f = open(sys.argv[1], 'wb') > - f.write('\x90' * c) > + f.write(b'\x90' * c) > f.write(d) > f.close() > diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > index 493738c79c..0625efc456 100644 > --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > @@ -2,7 +2,7 @@ > ; @file > ; This file includes all other code files to assemble the reset vector code ; -; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR> > +; Copyright (c) 2008 - 2021, Intel Corporation. All rights > +reserved.<BR> > ; SPDX-License-Identifier: BSD-2-Clause-Patent ; > ;------------------------------------------------------------------------------ > @@ -36,7 +36,7 @@ > %include "PostCodes.inc" > > %ifdef ARCH_X64 > -%include "X64/PageTables.asm" > +%include "X64/1GPageTables.asm" > %endif > > %ifdef DEBUG_PORT80 > diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm > new file mode 100644 > index 0000000000..8ae6c4c98c > --- /dev/null > +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm > @@ -0,0 +1,64 @@ > +;---------------------------------------------------------------------- > +-------- > +; @file > +; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 > +(512GB) ; ; Copyright (c) 2021, Intel Corporation. All rights > +reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; > +Linear-Address Translation to a 1-GByte Page ; > +;---------------------------------------------------------------------- > +-------- > + > +BITS 64 > + > +%define ALIGN_TOP_TO_4K_FOR_PAGING > + > +%define PAGE_PRESENT 0x01 > +%define PAGE_READ_WRITE 0x02 > +%define PAGE_USER_SUPERVISOR 0x04 > +%define PAGE_WRITE_THROUGH 0x08 > +%define PAGE_CACHE_DISABLE 0x010 > +%define PAGE_ACCESSED 0x020 > +%define PAGE_DIRTY 0x040 > +%define PAGE_PAT 0x080 > +%define PAGE_GLOBAL 0x0100 > +%define PAGE_1G 0x80 > + > +%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ > + PAGE_READ_WRITE + \ > + PAGE_PRESENT) > + > +%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \ > + PAGE_READ_WRITE + \ > + PAGE_PRESENT + \ > + PAGE_1G) > + > +%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define > +PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) > + > +%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ > + PAGE_PDP_ATTR) > + > +%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR) > + > +ALIGN 16 > + > +TopLevelPageDirectory: > + > + ; > + ; Top level Page Directory Pointers (1 * 512GB entry) > + ; > + DQ PDP(0x1000) > + > + > + TIMES 0x1000-PGTBLS_OFFSET($) DB 0 > + ; > + ; Next level Page Directory Pointers (512 * 1GB entries => 512GB) > + ; > +%assign i 0 > +%rep 512 > + DQ PDP_1G(i) > + %assign i i+1 > +%endrep > + > + > +EndOfPageTables: > diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm > similarity index 100% > rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm > rename to UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm > -- > 2.32.0.windows.1 > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [edk2-devel] [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity 2021-07-19 7:09 ` Ard Biesheuvel @ 2021-07-19 20:01 ` Lendacky, Thomas 2021-07-19 20:02 ` Dov Murik 1 sibling, 0 replies; 8+ messages in thread From: Lendacky, Thomas @ 2021-07-19 20:01 UTC (permalink / raw) To: devel, ardb, Ni, Ray, Brijesh Singh, Dov Murik, James Bottomley, Erdem Aktas Cc: S, Ashraf Ali, Ard Biesheuvel, Justen, Jordan L, Agyeman, Prince, Kumar, Rahul1, De, Debkumar, Han, Harry, West, Catharine, V, Sangeetha On 7/19/21 2:09 AM, Ard Biesheuvel via groups.io wrote: > On Mon, 19 Jul 2021 at 05:14, Ni, Ray <ray.ni@intel.com> wrote: >> >> This change generates the reset vector binary which only contains 1G page table. If a platform doesn't support 1G page table, this will cause system hang. >> >> To Ard and Jordan, >> Can you evaluate whether this change impacts OVMF? >> > > I don't have a clue, sorry, and I wouldn't know where to begin looking. > > Brijesh, Dov, James, Erdem: after Laszlo's sudden departure, I will be > needing help reviewing OVMF patches that are highly specific to > SEV/SNP or x86 in general. > > Please take a look. I think this is OK for Ovmf (others on the email, please double check me). Ovmf includes its own version of ResetVector.nasmb (in place of Vtf0.nasmb) which includes its own version of Ia32/PageTables64.asm and never does an include for X64/PageTables.asm. Thanks, Tom > > >> To Prince, >> Can you evaluate whether this change impacts SimicsOpenBoardPkg? >> >> Thanks, >> Ray >> >> -----Original Message----- >> From: S, Ashraf Ali <ashraf.ali.s@intel.com> >> Sent: Friday, July 2, 2021 8:25 PM >> To: devel@edk2.groups.io >> Cc: S, Ashraf Ali <ashraf.ali.s@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; West, Catharine <catharine.west@intel.com>; V, Sangeetha <sangeetha.v@intel.com> >> Subject: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity >> >> REF:https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3473&data=04%7C01%7Cthomas.lendacky%40amd.com%7Ccf73602f1b224340970a08d94a84399d%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637622754052197154%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=8gFLRyPEvbfwNN6BDimRe0spZfrNkMFdl6J9fYIe4RE%3D&reserved=0 >> >> X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when user wants to use more than 4G using 2M Page it will leads to use more number of Page table entries. using the 1-GByte Page table user can use more than 4G Memory by reducing the page table entries using 1-GByte Page, this patch attached can access memory range till 512GByte. >> Build Scrips for Reset Vector currently based on Python 2 which is already EOL, needs to modify the build script based on Python 3, update the Binary accordingly. >> >> Cc: Ray Ni <ray.ni@intel.com> >> Cc: Rahul Kumar <rahul1.kumar@intel.com> >> Cc: Debkumar De <debkumar.de@intel.com> >> Cc: Harry Han <harry.han@intel.com> >> Cc: Catharine West <catharine.west@intel.com> >> Cc: Sangeetha V <sangeetha.v@intel.com> >> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com> >> --- >> .../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 516 -> 484 bytes >> .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes >> .../Vtf0/Bin/ResetVector.ia32.serial.raw | Bin 884 -> 868 bytes >> .../Vtf0/Bin/ResetVector.x64.port80.raw | Bin 28676 -> 12292 bytes >> .../ResetVector/Vtf0/Bin/ResetVector.x64.raw | Bin 28676 -> 12292 bytes >> .../Vtf0/Bin/ResetVector.x64.serial.raw | Bin 28676 -> 12292 bytes >> UefiCpuPkg/ResetVector/Vtf0/Build.py | 11 +-- >> .../ResetVector/Vtf0/Ia32/PageTables64.asm | 2 +- >> UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 2 +- >> .../Vtf0/Tools/FixupForRawSection.py | 4 +- >> UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 4 +- >> .../ResetVector/Vtf0/X64/1GPageTables.asm | 64 ++++++++++++++++++ >> .../X64/{PageTables.asm => 2MPageTables.asm} | 0 >> 13 files changed, 77 insertions(+), 10 deletions(-) create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm >> rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => 2MPageTables.asm} (100%) >> >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw >> index 2c6ff655ded2a5855ca8f4428d559a7727eb6983..79b23c047bdc6e552d77d5c9e9aeae21ff04d91d 100644 GIT binary patch delta 410 >> zcmZo+dBQ9-0SF8a=rRZ}FxWCMF#Invo+zYJ-&~=>P<pEKFmr@L>EYMB8#X*^*s&i7 >> zI*-2o*Lifq#%B#L{TUe;3~zVd>wJ;c9c#dNqsaO-vqO<t>wyxZ<^$|Sx+*`qBE-KP >> zRw#MZ?IF_m@c;k+44fxR?lK-MVJf=bP$9%z%Jy2m^*||G=ZV*+3=ec3YyDQrw&BCG >> zhLV39>OTT4_yTke(6spG0}_@eiX$2-m<39tfuvB0QMW|nV~~MBTOFDYFc(>?{CR!5 >> z`2b5=qlIr&sV@Ka2ph)3jn)CK3=F06%+4CG<$;o&htnFZ!=g(0n4LMA4`}djk7m=n >> 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zAOGf?&;HbztFQmLmmj(PtZTNPaLxAPFW>X}!?^gyllNS?a^>P1A6Z}fYPVif|H4;0 >> zdF!JhZhhOuAG-L!nOA@Iv#z`Uju)StIvi!*@d<bK*^j^ev4_WZ-1hW$zv>lFe%F0B >> zpMBufw?FB^4<Ft+ZuqXVZ@cc>&pzsoAE@(BJaz7dldnDOd1s%y;o_T5zT>dNt$p!L >> zcfRY~3m<uaXRbM*|NH5legFUY75*Pi@jcgFJ+iZRTz}Ky5TE<zFZzNyf9l4wHy^$} >> z@$B<oeba>>y?Q=}Gyjb1ub%lGFM0ZVPk!+5)b)=(Y@NCAaW8%4xsN^l+E+aPy8A9X >> z?`5BK_&A?=>P62u`G~_`KD5Wh`_5c=-pgNk?n6$!=yBIS<M8b1*M8Pxo_YVt^@oS| >> z9R9?~+uwiX$~`exuAIK*{?j+l>3biz{`4*LZ57d{pMBVR-05eXzPS$%o_hM0e#iO4 >> z-Zx!yl|1K~Y5VAFw*NPu>jxZ8+LiY1s~6g>m;cwT=R9KT36I!%{N<l{UHrsdZ+qPr >> zUiqjqr>}eRnR`C$a6KFj?aVu#beNVK<DPuX;Vf^NM}9E3U2{y&zGnLu9^;vN9v64r >> ze^=i%cRg^|TTWhbn5#=qjXJ!?&o3@lC-CZc=zrnA?0X*e>weB}jn}{MWe<MP>p$^j >> z58iO*;u}u#y@!kU<R`D3Jo?JXOW%9t%E>M7JAA3bjNX3F;bkBC7rNV@_NLpP_Qu<v >> j_J-Rp&Xu=6c;CbCb@e@7{+Tb1OP3z}mY;w3OP78Y>oK+# >> >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py b/UefiCpuPkg/ResetVector/Vtf0/Build.py >> index 343c53b5ff..29f29ff0c2 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Build.py >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Build.py >> @@ -1,7 +1,7 @@ >> ## @file >> # Automate the process of building the various reset vector types # -# Copyright (c) 2009, Intel Corporation. All rights reserved.<BR> >> +# Copyright (c) 2009 - 2021, Intel Corporation. All rights >> +reserved.<BR> >> # >> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -32,16 +32,19 @@ for arch in ('ia32', 'x64'): >> '-o', output, >> 'Vtf0.nasmb', >> ) >> + print(f"Command : {' '.join(commandLine)}") >> ret = RunCommand(commandLine) >> - print '\tASM\t' + output >> - if ret != 0: sys.exit(ret) >> + if ret != 0: >> + print(f"something went wrong while executing the {commandLine[-1]}") >> + sys.exit() >> + print('\tASM\t' + output) >> >> commandLine = ( >> 'python', >> 'Tools/FixupForRawSection.py', >> output, >> ) >> - print '\tFIXUP\t' + output >> + print('\tFIXUP\t' + output) >> ret = RunCommand(commandLine) >> if ret != 0: sys.exit(ret) >> >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm >> index 87a4125d4b..9cc6f56c17 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm >> @@ -15,7 +15,7 @@ BITS 32 >> SetCr3ForPageTables64: >> >> ; >> - ; These pages are built into the ROM image in X64/PageTables.asm >> + ; These pages are built into the ROM image in X64/1GPageTables.asm >> ; >> mov eax, ADDR_OF(TopLevelPageDirectory) >> mov cr3, eax >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt >> index e6e5b54243..eb9dd24ee2 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt >> +++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt >> @@ -29,7 +29,7 @@ EBP/RBP - Pointer to the start of the Boot Firmware Volume === HOW TO BUILD VTF0 === >> >> Dependencies: >> -* Python 2.5~2.7 >> +* Python 3.0 or newer >> * Nasm 2.03 or newer >> >> To rebuild the VTF0 binaries: >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py >> index c77438a0ce..de771eba22 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py >> @@ -1,7 +1,7 @@ >> ## @file >> # Apply fixup to VTF binary image for FFS Raw section # -# Copyright (c) 2008, Intel Corporation. All rights reserved.<BR> >> +# Copyright (c) 2008 - 2021, Intel Corporation. All rights >> +reserved.<BR> >> # >> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -15,6 +15,6 @@ c = ((len(d) + 4 + 7) & ~7) - 4 if c > len(d): >> c -= len(d) >> f = open(sys.argv[1], 'wb') >> - f.write('\x90' * c) >> + f.write(b'\x90' * c) >> f.write(d) >> f.close() >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb >> index 493738c79c..0625efc456 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb >> @@ -2,7 +2,7 @@ >> ; @file >> ; This file includes all other code files to assemble the reset vector code ; -; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR> >> +; Copyright (c) 2008 - 2021, Intel Corporation. All rights >> +reserved.<BR> >> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; >> ;------------------------------------------------------------------------------ >> @@ -36,7 +36,7 @@ >> %include "PostCodes.inc" >> >> %ifdef ARCH_X64 >> -%include "X64/PageTables.asm" >> +%include "X64/1GPageTables.asm" >> %endif >> >> %ifdef DEBUG_PORT80 >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm >> new file mode 100644 >> index 0000000000..8ae6c4c98c >> --- /dev/null >> +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm >> @@ -0,0 +1,64 @@ >> +;---------------------------------------------------------------------- >> +-------- >> +; @file >> +; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 >> +(512GB) ; ; Copyright (c) 2021, Intel Corporation. All rights >> +reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; >> +Linear-Address Translation to a 1-GByte Page ; >> +;---------------------------------------------------------------------- >> +-------- >> + >> +BITS 64 >> + >> +%define ALIGN_TOP_TO_4K_FOR_PAGING >> + >> +%define PAGE_PRESENT 0x01 >> +%define PAGE_READ_WRITE 0x02 >> +%define PAGE_USER_SUPERVISOR 0x04 >> +%define PAGE_WRITE_THROUGH 0x08 >> +%define PAGE_CACHE_DISABLE 0x010 >> +%define PAGE_ACCESSED 0x020 >> +%define PAGE_DIRTY 0x040 >> +%define PAGE_PAT 0x080 >> +%define PAGE_GLOBAL 0x0100 >> +%define PAGE_1G 0x80 >> + >> +%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ >> + PAGE_READ_WRITE + \ >> + PAGE_PRESENT) >> + >> +%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \ >> + PAGE_READ_WRITE + \ >> + PAGE_PRESENT + \ >> + PAGE_1G) >> + >> +%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define >> +PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) >> + >> +%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ >> + PAGE_PDP_ATTR) >> + >> +%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR) >> + >> +ALIGN 16 >> + >> +TopLevelPageDirectory: >> + >> + ; >> + ; Top level Page Directory Pointers (1 * 512GB entry) >> + ; >> + DQ PDP(0x1000) >> + >> + >> + TIMES 0x1000-PGTBLS_OFFSET($) DB 0 >> + ; >> + ; Next level Page Directory Pointers (512 * 1GB entries => 512GB) >> + ; >> +%assign i 0 >> +%rep 512 >> + DQ PDP_1G(i) >> + %assign i i+1 >> +%endrep >> + >> + >> +EndOfPageTables: >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm >> similarity index 100% >> rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm >> rename to UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm >> -- >> 2.32.0.windows.1 >> > > > > > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity 2021-07-19 7:09 ` Ard Biesheuvel 2021-07-19 20:01 ` [edk2-devel] " Lendacky, Thomas @ 2021-07-19 20:02 ` Dov Murik 2021-07-21 9:30 ` Ni, Ray 1 sibling, 1 reply; 8+ messages in thread From: Dov Murik @ 2021-07-19 20:02 UTC (permalink / raw) To: Ard Biesheuvel, Ni, Ray, Brijesh Singh, James Bottomley, Erdem Aktas, Tom Lendacky Cc: S, Ashraf Ali, devel@edk2.groups.io, Ard Biesheuvel, Justen, Jordan L, Agyeman, Prince, Kumar, Rahul1, De, Debkumar, Han, Harry, West, Catharine, V, Sangeetha On 19/07/2021 10:09, Ard Biesheuvel wrote: > On Mon, 19 Jul 2021 at 05:14, Ni, Ray <ray.ni@intel.com> wrote: >> >> This change generates the reset vector binary which only contains 1G page table. If a platform doesn't support 1G page table, this will cause system hang. >> >> To Ard and Jordan, >> Can you evaluate whether this change impacts OVMF? >> > > I don't have a clue, sorry, and I wouldn't know where to begin looking. > > Brijesh, Dov, James, Erdem: after Laszlo's sudden departure, I will be > needing help reviewing OVMF patches that are highly specific to > SEV/SNP or x86 in general. Adding Tom too - I think he modified the OVMF reset vector lately and might know. > > Please take a look. I'm not an expert, but I think that OVMF has its own reset vector in OvmfPkg/ResetVector, and therefore the changes in uefiCpuPkg will not affect OVMF. Regarding the patch itself: (1) I suggest separating the python tooling changes to one patch, verifying that the new python scripts generate the same binary files as the original python scripts. Then add another patch which introduces the reset vector changes. (2) Do all x64 CPUs support 1 GB pages? Is it always enabled? Do we need to check this capability somewhere? -Dov > > >> To Prince, >> Can you evaluate whether this change impacts SimicsOpenBoardPkg? >> >> Thanks, >> Ray >> >> -----Original Message----- >> From: S, Ashraf Ali <ashraf.ali.s@intel.com> >> Sent: Friday, July 2, 2021 8:25 PM >> To: devel@edk2.groups.io >> Cc: S, Ashraf Ali <ashraf.ali.s@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; West, Catharine <catharine.west@intel.com>; V, Sangeetha <sangeetha.v@intel.com> >> Subject: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity >> >> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473 >> >> X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when user wants to use more than 4G using 2M Page it will leads to use more number of Page table entries. using the 1-GByte Page table user can use more than 4G Memory by reducing the page table entries using 1-GByte Page, this patch attached can access memory range till 512GByte. >> Build Scrips for Reset Vector currently based on Python 2 which is already EOL, needs to modify the build script based on Python 3, update the Binary accordingly. >> >> Cc: Ray Ni <ray.ni@intel.com> >> Cc: Rahul Kumar <rahul1.kumar@intel.com> >> Cc: Debkumar De <debkumar.de@intel.com> >> Cc: Harry Han <harry.han@intel.com> >> Cc: Catharine West <catharine.west@intel.com> >> Cc: Sangeetha V <sangeetha.v@intel.com> >> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com> >> --- >> .../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 516 -> 484 bytes >> .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes >> .../Vtf0/Bin/ResetVector.ia32.serial.raw | Bin 884 -> 868 bytes >> .../Vtf0/Bin/ResetVector.x64.port80.raw | Bin 28676 -> 12292 bytes >> .../ResetVector/Vtf0/Bin/ResetVector.x64.raw | Bin 28676 -> 12292 bytes >> .../Vtf0/Bin/ResetVector.x64.serial.raw | Bin 28676 -> 12292 bytes >> UefiCpuPkg/ResetVector/Vtf0/Build.py | 11 +-- >> .../ResetVector/Vtf0/Ia32/PageTables64.asm | 2 +- >> UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 2 +- >> .../Vtf0/Tools/FixupForRawSection.py | 4 +- >> UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 4 +- >> .../ResetVector/Vtf0/X64/1GPageTables.asm | 64 ++++++++++++++++++ >> .../X64/{PageTables.asm => 2MPageTables.asm} | 0 >> 13 files changed, 77 insertions(+), 10 deletions(-) create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm >> rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => 2MPageTables.asm} (100%) >> >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw >> index 2c6ff655ded2a5855ca8f4428d559a7727eb6983..79b23c047bdc6e552d77d5c9e9aeae21ff04d91d 100644 GIT binary patch delta 410 >> zcmZo+dBQ9-0SF8a=rRZ}FxWCMF#Invo+zYJ-&~=>P<pEKFmr@L>EYMB8#X*^*s&i7 >> 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ze^=i%cRg^|TTWhbn5#=qjXJ!?&o3@lC-CZc=zrnA?0X*e>weB}jn}{MWe<MP>p$^j >> z58iO*;u}u#y@!kU<R`D3Jo?JXOW%9t%E>M7JAA3bjNX3F;bkBC7rNV@_NLpP_Qu<v >> j_J-Rp&Xu=6c;CbCb@e@7{+Tb1OP3z}mY;w3OP78Y>oK+# >> >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py b/UefiCpuPkg/ResetVector/Vtf0/Build.py >> index 343c53b5ff..29f29ff0c2 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Build.py >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Build.py >> @@ -1,7 +1,7 @@ >> ## @file >> # Automate the process of building the various reset vector types # -# Copyright (c) 2009, Intel Corporation. All rights reserved.<BR> >> +# Copyright (c) 2009 - 2021, Intel Corporation. All rights >> +reserved.<BR> >> # >> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -32,16 +32,19 @@ for arch in ('ia32', 'x64'): >> '-o', output, >> 'Vtf0.nasmb', >> ) >> + print(f"Command : {' '.join(commandLine)}") >> ret = RunCommand(commandLine) >> - print '\tASM\t' + output >> - if ret != 0: sys.exit(ret) >> + if ret != 0: >> + print(f"something went wrong while executing the {commandLine[-1]}") >> + sys.exit() >> + print('\tASM\t' + output) >> >> commandLine = ( >> 'python', >> 'Tools/FixupForRawSection.py', >> output, >> ) >> - print '\tFIXUP\t' + output >> + print('\tFIXUP\t' + output) >> ret = RunCommand(commandLine) >> if ret != 0: sys.exit(ret) >> >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm >> index 87a4125d4b..9cc6f56c17 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm >> @@ -15,7 +15,7 @@ BITS 32 >> SetCr3ForPageTables64: >> >> ; >> - ; These pages are built into the ROM image in X64/PageTables.asm >> + ; These pages are built into the ROM image in X64/1GPageTables.asm >> ; >> mov eax, ADDR_OF(TopLevelPageDirectory) >> mov cr3, eax >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt >> index e6e5b54243..eb9dd24ee2 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt >> +++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt >> @@ -29,7 +29,7 @@ EBP/RBP - Pointer to the start of the Boot Firmware Volume === HOW TO BUILD VTF0 === >> >> Dependencies: >> -* Python 2.5~2.7 >> +* Python 3.0 or newer >> * Nasm 2.03 or newer >> >> To rebuild the VTF0 binaries: >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py >> index c77438a0ce..de771eba22 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py >> @@ -1,7 +1,7 @@ >> ## @file >> # Apply fixup to VTF binary image for FFS Raw section # -# Copyright (c) 2008, Intel Corporation. All rights reserved.<BR> >> +# Copyright (c) 2008 - 2021, Intel Corporation. All rights >> +reserved.<BR> >> # >> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -15,6 +15,6 @@ c = ((len(d) + 4 + 7) & ~7) - 4 if c > len(d): >> c -= len(d) >> f = open(sys.argv[1], 'wb') >> - f.write('\x90' * c) >> + f.write(b'\x90' * c) >> f.write(d) >> f.close() >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb >> index 493738c79c..0625efc456 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb >> @@ -2,7 +2,7 @@ >> ; @file >> ; This file includes all other code files to assemble the reset vector code ; -; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR> >> +; Copyright (c) 2008 - 2021, Intel Corporation. All rights >> +reserved.<BR> >> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; >> ;------------------------------------------------------------------------------ >> @@ -36,7 +36,7 @@ >> %include "PostCodes.inc" >> >> %ifdef ARCH_X64 >> -%include "X64/PageTables.asm" >> +%include "X64/1GPageTables.asm" >> %endif >> >> %ifdef DEBUG_PORT80 >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm >> new file mode 100644 >> index 0000000000..8ae6c4c98c >> --- /dev/null >> +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm >> @@ -0,0 +1,64 @@ >> +;---------------------------------------------------------------------- >> +-------- >> +; @file >> +; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 >> +(512GB) ; ; Copyright (c) 2021, Intel Corporation. All rights >> +reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; >> +Linear-Address Translation to a 1-GByte Page ; >> +;---------------------------------------------------------------------- >> +-------- >> + >> +BITS 64 >> + >> +%define ALIGN_TOP_TO_4K_FOR_PAGING >> + >> +%define PAGE_PRESENT 0x01 >> +%define PAGE_READ_WRITE 0x02 >> +%define PAGE_USER_SUPERVISOR 0x04 >> +%define PAGE_WRITE_THROUGH 0x08 >> +%define PAGE_CACHE_DISABLE 0x010 >> +%define PAGE_ACCESSED 0x020 >> +%define PAGE_DIRTY 0x040 >> +%define PAGE_PAT 0x080 >> +%define PAGE_GLOBAL 0x0100 >> +%define PAGE_1G 0x80 >> + >> +%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ >> + PAGE_READ_WRITE + \ >> + PAGE_PRESENT) >> + >> +%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \ >> + PAGE_READ_WRITE + \ >> + PAGE_PRESENT + \ >> + PAGE_1G) >> + >> +%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define >> +PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) >> + >> +%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ >> + PAGE_PDP_ATTR) >> + >> +%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR) >> + >> +ALIGN 16 >> + >> +TopLevelPageDirectory: >> + >> + ; >> + ; Top level Page Directory Pointers (1 * 512GB entry) >> + ; >> + DQ PDP(0x1000) >> + >> + >> + TIMES 0x1000-PGTBLS_OFFSET($) DB 0 >> + ; >> + ; Next level Page Directory Pointers (512 * 1GB entries => 512GB) >> + ; >> +%assign i 0 >> +%rep 512 >> + DQ PDP_1G(i) >> + %assign i i+1 >> +%endrep >> + >> + >> +EndOfPageTables: >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm >> similarity index 100% >> rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm >> rename to UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm >> -- >> 2.32.0.windows.1 >> ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity 2021-07-19 20:02 ` Dov Murik @ 2021-07-21 9:30 ` Ni, Ray 2021-07-22 16:57 ` Ashraf Ali S 0 siblings, 1 reply; 8+ messages in thread From: Ni, Ray @ 2021-07-21 9:30 UTC (permalink / raw) To: Dov Murik, Ard Biesheuvel, Brijesh Singh, James Bottomley, Erdem Aktas, Tom Lendacky, Xu, Min M Cc: S, Ashraf Ali, devel@edk2.groups.io, Ard Biesheuvel, Justen, Jordan L, Agyeman, Prince, Kumar, Rahul1, De, Debkumar, Han, Harry, West, Catharine, V, Sangeetha OVMF's ResetVector is including the UefiCpuPkg's ResetVector. So, OVMF owners please do evaluate the impact. I think this change assumes platform owner knows which format of page table should be chosen in build time. -----Original Message----- From: Dov Murik <dovmurik@linux.ibm.com> Sent: Tuesday, July 20, 2021 4:02 AM To: Ard Biesheuvel <ardb@kernel.org>; Ni, Ray <ray.ni@intel.com>; Brijesh Singh <brijesh.singh@amd.com>; James Bottomley <jejb@linux.ibm.com>; Erdem Aktas <erdemaktas@google.com>; Tom Lendacky <thomas.lendacky@amd.com> Cc: S, Ashraf Ali <ashraf.ali.s@intel.com>; devel@edk2.groups.io; Ard Biesheuvel <ardb+tianocore@kernel.org>; Justen, Jordan L <jordan.l.justen@intel.com>; Agyeman, Prince <prince.agyeman@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; West, Catharine <catharine.west@intel.com>; V, Sangeetha <sangeetha.v@intel.com> Subject: Re: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity On 19/07/2021 10:09, Ard Biesheuvel wrote: > On Mon, 19 Jul 2021 at 05:14, Ni, Ray <ray.ni@intel.com> wrote: >> >> This change generates the reset vector binary which only contains 1G page table. If a platform doesn't support 1G page table, this will cause system hang. >> >> To Ard and Jordan, >> Can you evaluate whether this change impacts OVMF? >> > > I don't have a clue, sorry, and I wouldn't know where to begin looking. > > Brijesh, Dov, James, Erdem: after Laszlo's sudden departure, I will be > needing help reviewing OVMF patches that are highly specific to > SEV/SNP or x86 in general. Adding Tom too - I think he modified the OVMF reset vector lately and might know. > > Please take a look. I'm not an expert, but I think that OVMF has its own reset vector in OvmfPkg/ResetVector, and therefore the changes in uefiCpuPkg will not affect OVMF. Regarding the patch itself: (1) I suggest separating the python tooling changes to one patch, verifying that the new python scripts generate the same binary files as the original python scripts. Then add another patch which introduces the reset vector changes. (2) Do all x64 CPUs support 1 GB pages? Is it always enabled? Do we need to check this capability somewhere? -Dov > > >> To Prince, >> Can you evaluate whether this change impacts SimicsOpenBoardPkg? >> >> Thanks, >> Ray >> >> -----Original Message----- >> From: S, Ashraf Ali <ashraf.ali.s@intel.com> >> Sent: Friday, July 2, 2021 8:25 PM >> To: devel@edk2.groups.io >> Cc: S, Ashraf Ali <ashraf.ali.s@intel.com>; Ni, Ray >> <ray.ni@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, >> Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; >> West, Catharine <catharine.west@intel.com>; V, Sangeetha >> <sangeetha.v@intel.com> >> Subject: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte >> Page Granularity >> >> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473 >> >> X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when user wants to use more than 4G using 2M Page it will leads to use more number of Page table entries. using the 1-GByte Page table user can use more than 4G Memory by reducing the page table entries using 1-GByte Page, this patch attached can access memory range till 512GByte. >> Build Scrips for Reset Vector currently based on Python 2 which is already EOL, needs to modify the build script based on Python 3, update the Binary accordingly. >> >> Cc: Ray Ni <ray.ni@intel.com> >> Cc: Rahul Kumar <rahul1.kumar@intel.com> >> Cc: Debkumar De <debkumar.de@intel.com> >> Cc: Harry Han <harry.han@intel.com> >> Cc: Catharine West <catharine.west@intel.com> >> Cc: Sangeetha V <sangeetha.v@intel.com> >> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com> >> --- >> .../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 516 -> 484 bytes >> .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes >> .../Vtf0/Bin/ResetVector.ia32.serial.raw | Bin 884 -> 868 bytes >> .../Vtf0/Bin/ResetVector.x64.port80.raw | Bin 28676 -> 12292 bytes >> .../ResetVector/Vtf0/Bin/ResetVector.x64.raw | Bin 28676 -> 12292 bytes >> .../Vtf0/Bin/ResetVector.x64.serial.raw | Bin 28676 -> 12292 bytes >> UefiCpuPkg/ResetVector/Vtf0/Build.py | 11 +-- >> .../ResetVector/Vtf0/Ia32/PageTables64.asm | 2 +- >> UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 2 +- >> .../Vtf0/Tools/FixupForRawSection.py | 4 +- >> UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 4 +- >> .../ResetVector/Vtf0/X64/1GPageTables.asm | 64 ++++++++++++++++++ >> .../X64/{PageTables.asm => 2MPageTables.asm} | 0 >> 13 files changed, 77 insertions(+), 10 deletions(-) create mode >> 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm >> rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => >> 2MPageTables.asm} (100%) >> >> diff --git >> a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw >> b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw >> index >> 2c6ff655ded2a5855ca8f4428d559a7727eb6983..79b23c047bdc6e552d77d5c9e9a >> eae21ff04d91d 100644 GIT binary patch delta 410 >> zcmZo+dBQ9-0SF8a=rRZ}FxWCMF#Invo+zYJ-&~=>P<pEKFmr@L>EYMB8#X*^*s&i7 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z-Zx!yl|1K~Y5VAFw*NPu>jxZ8+LiY1s~6g>m;cwT=R9KT36I!%{N<l{UHrsdZ+qPr >> zUiqjqr>}eRnR`C$a6KFj?aVu#beNVK<DPuX;Vf^NM}9E3U2{y&zGnLu9^;vN9v64r >> ze^=i%cRg^|TTWhbn5#=qjXJ!?&o3@lC-CZc=zrnA?0X*e>weB}jn}{MWe<MP>p$^j >> z58iO*;u}u#y@!kU<R`D3Jo?JXOW%9t%E>M7JAA3bjNX3F;bkBC7rNV@_NLpP_Qu<v >> j_J-Rp&Xu=6c;CbCb@e@7{+Tb1OP3z}mY;w3OP78Y>oK+# >> >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py >> b/UefiCpuPkg/ResetVector/Vtf0/Build.py >> index 343c53b5ff..29f29ff0c2 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Build.py >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Build.py >> @@ -1,7 +1,7 @@ >> ## @file >> # Automate the process of building the various reset vector types >> # -# Copyright (c) 2009, Intel Corporation. All rights reserved.<BR> >> +# Copyright (c) 2009 - 2021, Intel Corporation. All rights >> +reserved.<BR> >> # >> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -32,16 +32,19 @@ for arch in ('ia32', 'x64'): >> '-o', output, >> 'Vtf0.nasmb', >> ) >> + print(f"Command : {' '.join(commandLine)}") >> ret = RunCommand(commandLine) >> - print '\tASM\t' + output >> - if ret != 0: sys.exit(ret) >> + if ret != 0: >> + print(f"something went wrong while executing the {commandLine[-1]}") >> + sys.exit() >> + print('\tASM\t' + output) >> >> commandLine = ( >> 'python', >> 'Tools/FixupForRawSection.py', >> output, >> ) >> - print '\tFIXUP\t' + output >> + print('\tFIXUP\t' + output) >> ret = RunCommand(commandLine) >> if ret != 0: sys.exit(ret) >> >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm >> b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm >> index 87a4125d4b..9cc6f56c17 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm >> @@ -15,7 +15,7 @@ BITS 32 >> SetCr3ForPageTables64: >> >> ; >> - ; These pages are built into the ROM image in X64/PageTables.asm >> + ; These pages are built into the ROM image in >> + X64/1GPageTables.asm >> ; >> mov eax, ADDR_OF(TopLevelPageDirectory) >> mov cr3, eax >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt >> b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt >> index e6e5b54243..eb9dd24ee2 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt >> +++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt >> @@ -29,7 +29,7 @@ EBP/RBP - Pointer to the start of the Boot Firmware >> Volume === HOW TO BUILD VTF0 === >> >> Dependencies: >> -* Python 2.5~2.7 >> +* Python 3.0 or newer >> * Nasm 2.03 or newer >> >> To rebuild the VTF0 binaries: >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py >> b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py >> index c77438a0ce..de771eba22 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py >> @@ -1,7 +1,7 @@ >> ## @file >> # Apply fixup to VTF binary image for FFS Raw section # -# >> Copyright (c) 2008, Intel Corporation. All rights reserved.<BR> >> +# Copyright (c) 2008 - 2021, Intel Corporation. All rights >> +reserved.<BR> >> # >> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -15,6 +15,6 @@ c = ((len(d) + 4 + 7) & ~7) - 4 if c > len(d): >> c -= len(d) >> f = open(sys.argv[1], 'wb') >> - f.write('\x90' * c) >> + f.write(b'\x90' * c) >> f.write(d) >> f.close() >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb >> b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb >> index 493738c79c..0625efc456 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb >> @@ -2,7 +2,7 @@ >> ; @file >> ; This file includes all other code files to assemble the reset >> vector code ; -; Copyright (c) 2008 - 2013, Intel Corporation. All >> rights reserved.<BR> >> +; Copyright (c) 2008 - 2021, Intel Corporation. All rights >> +reserved.<BR> >> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; >> >> ;-------------------------------------------------------------------- >> ---------- >> @@ -36,7 +36,7 @@ >> %include "PostCodes.inc" >> >> %ifdef ARCH_X64 >> -%include "X64/PageTables.asm" >> +%include "X64/1GPageTables.asm" >> %endif >> >> %ifdef DEBUG_PORT80 >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm >> b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm >> new file mode 100644 >> index 0000000000..8ae6c4c98c >> --- /dev/null >> +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm >> @@ -0,0 +1,64 @@ >> +;------------------------------------------------------------------- >> +--- >> +-------- >> +; @file >> +; Emits Page Tables for 1:1 mapping of the addresses 0 - >> +0x8000000000 >> +(512GB) ; ; Copyright (c) 2021, Intel Corporation. All rights >> +reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; >> +Linear-Address Translation to a 1-GByte Page ; >> +;------------------------------------------------------------------- >> +--- >> +-------- >> + >> +BITS 64 >> + >> +%define ALIGN_TOP_TO_4K_FOR_PAGING >> + >> +%define PAGE_PRESENT 0x01 >> +%define PAGE_READ_WRITE 0x02 >> +%define PAGE_USER_SUPERVISOR 0x04 >> +%define PAGE_WRITE_THROUGH 0x08 >> +%define PAGE_CACHE_DISABLE 0x010 >> +%define PAGE_ACCESSED 0x020 >> +%define PAGE_DIRTY 0x040 >> +%define PAGE_PAT 0x080 >> +%define PAGE_GLOBAL 0x0100 >> +%define PAGE_1G 0x80 >> + >> +%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ >> + PAGE_READ_WRITE + \ >> + PAGE_PRESENT) >> + >> +%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \ >> + PAGE_READ_WRITE + \ >> + PAGE_PRESENT + \ >> + PAGE_1G) >> + >> +%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define >> +PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) >> + >> +%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ >> + PAGE_PDP_ATTR) >> + >> +%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR) >> + >> +ALIGN 16 >> + >> +TopLevelPageDirectory: >> + >> + ; >> + ; Top level Page Directory Pointers (1 * 512GB entry) >> + ; >> + DQ PDP(0x1000) >> + >> + >> + TIMES 0x1000-PGTBLS_OFFSET($) DB 0 >> + ; >> + ; Next level Page Directory Pointers (512 * 1GB entries => 512GB) >> + ; >> +%assign i 0 >> +%rep 512 >> + DQ PDP_1G(i) >> + %assign i i+1 >> +%endrep >> + >> + >> +EndOfPageTables: >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm >> b/UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm >> similarity index 100% >> rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm >> rename to UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm >> -- >> 2.32.0.windows.1 >> ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity 2021-07-21 9:30 ` Ni, Ray @ 2021-07-22 16:57 ` Ashraf Ali S 2021-07-23 2:37 ` Ni, Ray 0 siblings, 1 reply; 8+ messages in thread From: Ashraf Ali S @ 2021-07-22 16:57 UTC (permalink / raw) To: Ni, Ray, Dov Murik, Ard Biesheuvel, Brijesh Singh, James Bottomley, Erdem Aktas, Tom Lendacky, Xu, Min M Cc: devel@edk2.groups.io, Ard Biesheuvel, Justen, Jordan L, Agyeman, Prince, Kumar, Rahul1, De, Debkumar, Han, Harry, West, Catharine, V, Sangeetha Hi. Ray Based on Dov Murik <dovmurik@linux.ibm.com> Comments to take the python script changes separately, I have filed the Bugzilla for that separately. https://bugzilla.tianocore.org/show_bug.cgi?id=3506 verified the binary. More details are in Bugzilla. Regards, Ashraf Ali S Intel Technology India Pvt. Ltd. -----Original Message----- From: Ni, Ray <ray.ni@intel.com> Sent: Wednesday, July 21, 2021 3:00 PM To: Dov Murik <dovmurik@linux.ibm.com>; Ard Biesheuvel <ardb@kernel.org>; Brijesh Singh <brijesh.singh@amd.com>; James Bottomley <jejb@linux.ibm.com>; Erdem Aktas <erdemaktas@google.com>; Tom Lendacky <thomas.lendacky@amd.com>; Xu, Min M <min.m.xu@intel.com> Cc: S, Ashraf Ali <ashraf.ali.s@intel.com>; devel@edk2.groups.io; Ard Biesheuvel <ardb+tianocore@kernel.org>; Justen, Jordan L <jordan.l.justen@intel.com>; Agyeman, Prince <prince.agyeman@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; West, Catharine <catharine.west@intel.com>; V, Sangeetha <sangeetha.v@intel.com> Subject: RE: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity OVMF's ResetVector is including the UefiCpuPkg's ResetVector. So, OVMF owners please do evaluate the impact. I think this change assumes platform owner knows which format of page table should be chosen in build time. -----Original Message----- From: Dov Murik <dovmurik@linux.ibm.com> Sent: Tuesday, July 20, 2021 4:02 AM To: Ard Biesheuvel <ardb@kernel.org>; Ni, Ray <ray.ni@intel.com>; Brijesh Singh <brijesh.singh@amd.com>; James Bottomley <jejb@linux.ibm.com>; Erdem Aktas <erdemaktas@google.com>; Tom Lendacky <thomas.lendacky@amd.com> Cc: S, Ashraf Ali <ashraf.ali.s@intel.com>; devel@edk2.groups.io; Ard Biesheuvel <ardb+tianocore@kernel.org>; Justen, Jordan L <jordan.l.justen@intel.com>; Agyeman, Prince <prince.agyeman@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; West, Catharine <catharine.west@intel.com>; V, Sangeetha <sangeetha.v@intel.com> Subject: Re: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity On 19/07/2021 10:09, Ard Biesheuvel wrote: > On Mon, 19 Jul 2021 at 05:14, Ni, Ray <ray.ni@intel.com> wrote: >> >> This change generates the reset vector binary which only contains 1G page table. If a platform doesn't support 1G page table, this will cause system hang. >> >> To Ard and Jordan, >> Can you evaluate whether this change impacts OVMF? >> > > I don't have a clue, sorry, and I wouldn't know where to begin looking. > > Brijesh, Dov, James, Erdem: after Laszlo's sudden departure, I will be > needing help reviewing OVMF patches that are highly specific to > SEV/SNP or x86 in general. Adding Tom too - I think he modified the OVMF reset vector lately and might know. > > Please take a look. I'm not an expert, but I think that OVMF has its own reset vector in OvmfPkg/ResetVector, and therefore the changes in uefiCpuPkg will not affect OVMF. Regarding the patch itself: (1) I suggest separating the python tooling changes to one patch, verifying that the new python scripts generate the same binary files as the original python scripts. Then add another patch which introduces the reset vector changes. (2) Do all x64 CPUs support 1 GB pages? Is it always enabled? Do we need to check this capability somewhere? -Dov > > >> To Prince, >> Can you evaluate whether this change impacts SimicsOpenBoardPkg? >> >> Thanks, >> Ray >> >> -----Original Message----- >> From: S, Ashraf Ali <ashraf.ali.s@intel.com> >> Sent: Friday, July 2, 2021 8:25 PM >> To: devel@edk2.groups.io >> Cc: S, Ashraf Ali <ashraf.ali.s@intel.com>; Ni, Ray >> <ray.ni@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, >> Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; >> West, Catharine <catharine.west@intel.com>; V, Sangeetha >> <sangeetha.v@intel.com> >> Subject: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte >> Page Granularity >> >> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473 >> >> X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when user wants to use more than 4G using 2M Page it will leads to use more number of Page table entries. using the 1-GByte Page table user can use more than 4G Memory by reducing the page table entries using 1-GByte Page, this patch attached can access memory range till 512GByte. >> Build Scrips for Reset Vector currently based on Python 2 which is already EOL, needs to modify the build script based on Python 3, update the Binary accordingly. >> >> Cc: Ray Ni <ray.ni@intel.com> >> Cc: Rahul Kumar <rahul1.kumar@intel.com> >> Cc: Debkumar De <debkumar.de@intel.com> >> Cc: Harry Han <harry.han@intel.com> >> Cc: Catharine West <catharine.west@intel.com> >> Cc: Sangeetha V <sangeetha.v@intel.com> >> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com> >> --- >> .../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 516 -> 484 bytes >> .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes >> .../Vtf0/Bin/ResetVector.ia32.serial.raw | Bin 884 -> 868 bytes >> .../Vtf0/Bin/ResetVector.x64.port80.raw | Bin 28676 -> 12292 bytes >> .../ResetVector/Vtf0/Bin/ResetVector.x64.raw | Bin 28676 -> 12292 bytes >> .../Vtf0/Bin/ResetVector.x64.serial.raw | Bin 28676 -> 12292 bytes >> UefiCpuPkg/ResetVector/Vtf0/Build.py | 11 +-- >> .../ResetVector/Vtf0/Ia32/PageTables64.asm | 2 +- >> UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 2 +- >> .../Vtf0/Tools/FixupForRawSection.py | 4 +- >> UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 4 +- >> .../ResetVector/Vtf0/X64/1GPageTables.asm | 64 ++++++++++++++++++ >> .../X64/{PageTables.asm => 2MPageTables.asm} | 0 >> 13 files changed, 77 insertions(+), 10 deletions(-) create mode >> 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm >> rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => >> 2MPageTables.asm} (100%) >> >> diff --git >> a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw >> b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw >> index >> 2c6ff655ded2a5855ca8f4428d559a7727eb6983..79b23c047bdc6e552d77d5c9e9a >> eae21ff04d91d 100644 GIT binary patch delta 410 >> zcmZo+dBQ9-0SF8a=rRZ}FxWCMF#Invo+zYJ-&~=>P<pEKFmr@L>EYMB8#X*^*s&i7 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z<}m)6p2@}HW^)*SUC-oVakDv$zoBPxvAEeB#y9DiTr6%jhw(S{OfD8To5T29dL|c( >> zo6TW-v!2Pt;%0Lge_PMwVsW!MjK8C2a<RDC9LC?(Gr3sYY!2gF^h_=mH=D!wdwM1p >> zi<`}1{Cz!>i^a|6FuqmK<YIBNIgGpYOfD8To5T1AdL|c(o6TYTLp_s=#m(k0{*j)^ >> z#o}gj82?z$<YIBNIgEdzXL7N)*&N0{)ib$R+-wfxwR$EOi<`}1+@oi5vAEeB#<%I2 >> zTr6%jhjFi-$;IMka~QAFGr3sYY!2g}>6u(CZZ?PU&-F|$7B`#2_!oL67mJ(CVZ2_? >> z<YIBNIgHjbxmet64&&S7Fb?;BCKrpF&0&0pp2@}HW^)+#>6u(CZZ?PU20fFD#m(k0 >> z-l%7CvAEeB#+&p^E*3YN!}v};lZ(a8<}lu@XL7N)*&N1q>6u(CZZ?PU-FhY$i<`}1 >> z{7XHPi^a|6F#eUE$;IMka~S_x&*WlpvpI}^qi1rlxY-=W_vo2iEN(W3@fJOki^a|6 >> zFuqsM<YIBNIgIbqGr3sYY!2i5^-L}nH=D!ww|XWQi<`}1{D7Xx#o}gj7(b|Ia<RDC >> z9LB%XGr3sYY!2goJ(G*Y&E_!Ps%LVsxY-=Wzt=OlSlnz5<868-7mJ(CVf+U@lZ(a8 >> z<}m)Fp2@}HW^))nq-S!mxY-=Wf6_C#Slnz5WAsce7B`#2_~AH=!~LJh#o}gj7(b$C >> za<RDC9LA68nOrPxHiz+_^-L}nH=D!wF+G!u#m(k0-mYhIvAEeB#(&W>xmet64&wnm >> zlZ(a8<}gn5OfD8To5OgAp2@}HW^))1>X}?DZZ?PU<9a3+i<`}1{8v4bi^a|6FfQwv >> zTr6%jhw<O^OfD8To5T1CJ(G*Y&E_!vyPnC#;%0Lg|3lB@VsW!MJS;tjaaeztTr6%j >> zhw+noCKrpF&0+jcJ(G*Y&E_!PrDt-nxY-=WPwAOlEN(W3@oqhni^a|6Fn(Ik<YIBN >> zIgFptGr3sYY!2f+dL|c(o6TXoSI^{PakDv$_vx8jEN(W3@qRs%i^a|6Fs|sCTr6%j >> z=OJ&qbmd_;?`9vpI<L1K=i%Y&<2Vn;c{qMQ9M^;6I&fSEj_bg29XPH7$93Si4jk8k >> z<2vyF_d4(vKj$BP_;WnY!*L$2-q()T!SOmcUI)kTgX21ITnCQpz;PWot^>z);J6MP >> z*MVPT>%iex03640297guoPpyE9B1G-1IHOS&cJa7jx+F!bO!Ey&#Ak=<np~ged_MG >> zeDAwY-F@BVtIs_4^2s-yy7lmz32uyd!QrReD|bBi!ucD||JZ9@bMC<l=b!X~S3Tv^ >> z&;7`S^EZ9X$6WlJb8o$H{wa6f_mSU!?kyM2KmD+Cocqp;_nmsh&FA{$Qx98b?tR~> >> zAOGf?&;HbztFQmLmmj(PtZTNPaLxAPFW>X}!?^gyllNS?a^>P1A6Z}fYPVif|H4;0 >> zdF!JhZhhOuAG-L!nOA@Iv#z`Uju)StIvi!*@d<bK*^j^ev4_WZ-1hW$zv>lFe%F0B >> zpMBufw?FB^4<Ft+ZuqXVZ@cc>&pzsoAE@(BJaz7dldnDOd1s%y;o_T5zT>dNt$p!L >> zcfRY~3m<uaXRbM*|NH5legFUY75*Pi@jcgFJ+iZRTz}Ky5TE<zFZzNyf9l4wHy^$} >> z@$B<oeba>>y?Q=}Gyjb1ub%lGFM0ZVPk!+5)b)=(Y@NCAaW8%4xsN^l+E+aPy8A9X >> z?`5BK_&A?=>P62u`G~_`KD5Wh`_5c=-pgNk?n6$!=yBIS<M8b1*M8Pxo_YVt^@oS| >> z9R9?~+uwiX$~`exuAIK*{?j+l>3biz{`4*LZ57d{pMBVR-05eXzPS$%o_hM0e#iO4 >> z-Zx!yl|1K~Y5VAFw*NPu>jxZ8+LiY1s~6g>m;cwT=R9KT36I!%{N<l{UHrsdZ+qPr >> zUiqjqr>}eRnR`C$a6KFj?aVu#beNVK<DPuX;Vf^NM}9E3U2{y&zGnLu9^;vN9v64r >> ze^=i%cRg^|TTWhbn5#=qjXJ!?&o3@lC-CZc=zrnA?0X*e>weB}jn}{MWe<MP>p$^j >> z58iO*;u}u#y@!kU<R`D3Jo?JXOW%9t%E>M7JAA3bjNX3F;bkBC7rNV@_NLpP_Qu<v >> j_J-Rp&Xu=6c;CbCb@e@7{+Tb1OP3z}mY;w3OP78Y>oK+# >> >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py >> b/UefiCpuPkg/ResetVector/Vtf0/Build.py >> index 343c53b5ff..29f29ff0c2 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Build.py >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Build.py >> @@ -1,7 +1,7 @@ >> ## @file >> # Automate the process of building the various reset vector types >> # -# Copyright (c) 2009, Intel Corporation. All rights reserved.<BR> >> +# Copyright (c) 2009 - 2021, Intel Corporation. All rights >> +reserved.<BR> >> # >> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -32,16 +32,19 @@ for arch in ('ia32', 'x64'): >> '-o', output, >> 'Vtf0.nasmb', >> ) >> + print(f"Command : {' '.join(commandLine)}") >> ret = RunCommand(commandLine) >> - print '\tASM\t' + output >> - if ret != 0: sys.exit(ret) >> + if ret != 0: >> + print(f"something went wrong while executing the {commandLine[-1]}") >> + sys.exit() >> + print('\tASM\t' + output) >> >> commandLine = ( >> 'python', >> 'Tools/FixupForRawSection.py', >> output, >> ) >> - print '\tFIXUP\t' + output >> + print('\tFIXUP\t' + output) >> ret = RunCommand(commandLine) >> if ret != 0: sys.exit(ret) >> >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm >> b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm >> index 87a4125d4b..9cc6f56c17 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm >> @@ -15,7 +15,7 @@ BITS 32 >> SetCr3ForPageTables64: >> >> ; >> - ; These pages are built into the ROM image in X64/PageTables.asm >> + ; These pages are built into the ROM image in >> + X64/1GPageTables.asm >> ; >> mov eax, ADDR_OF(TopLevelPageDirectory) >> mov cr3, eax >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt >> b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt >> index e6e5b54243..eb9dd24ee2 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt >> +++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt >> @@ -29,7 +29,7 @@ EBP/RBP - Pointer to the start of the Boot Firmware >> Volume === HOW TO BUILD VTF0 === >> >> Dependencies: >> -* Python 2.5~2.7 >> +* Python 3.0 or newer >> * Nasm 2.03 or newer >> >> To rebuild the VTF0 binaries: >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py >> b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py >> index c77438a0ce..de771eba22 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py >> @@ -1,7 +1,7 @@ >> ## @file >> # Apply fixup to VTF binary image for FFS Raw section # -# >> Copyright (c) 2008, Intel Corporation. All rights reserved.<BR> >> +# Copyright (c) 2008 - 2021, Intel Corporation. All rights >> +reserved.<BR> >> # >> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -15,6 +15,6 @@ c = ((len(d) + 4 + 7) & ~7) - 4 if c > len(d): >> c -= len(d) >> f = open(sys.argv[1], 'wb') >> - f.write('\x90' * c) >> + f.write(b'\x90' * c) >> f.write(d) >> f.close() >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb >> b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb >> index 493738c79c..0625efc456 100644 >> --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb >> @@ -2,7 +2,7 @@ >> ; @file >> ; This file includes all other code files to assemble the reset >> vector code ; -; Copyright (c) 2008 - 2013, Intel Corporation. All >> rights reserved.<BR> >> +; Copyright (c) 2008 - 2021, Intel Corporation. All rights >> +reserved.<BR> >> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; >> >> ;-------------------------------------------------------------------- >> ---------- >> @@ -36,7 +36,7 @@ >> %include "PostCodes.inc" >> >> %ifdef ARCH_X64 >> -%include "X64/PageTables.asm" >> +%include "X64/1GPageTables.asm" >> %endif >> >> %ifdef DEBUG_PORT80 >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm >> b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm >> new file mode 100644 >> index 0000000000..8ae6c4c98c >> --- /dev/null >> +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm >> @@ -0,0 +1,64 @@ >> +;------------------------------------------------------------------- >> +--- >> +-------- >> +; @file >> +; Emits Page Tables for 1:1 mapping of the addresses 0 - >> +0x8000000000 >> +(512GB) ; ; Copyright (c) 2021, Intel Corporation. All rights >> +reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; >> +Linear-Address Translation to a 1-GByte Page ; >> +;------------------------------------------------------------------- >> +--- >> +-------- >> + >> +BITS 64 >> + >> +%define ALIGN_TOP_TO_4K_FOR_PAGING >> + >> +%define PAGE_PRESENT 0x01 >> +%define PAGE_READ_WRITE 0x02 >> +%define PAGE_USER_SUPERVISOR 0x04 >> +%define PAGE_WRITE_THROUGH 0x08 >> +%define PAGE_CACHE_DISABLE 0x010 >> +%define PAGE_ACCESSED 0x020 >> +%define PAGE_DIRTY 0x040 >> +%define PAGE_PAT 0x080 >> +%define PAGE_GLOBAL 0x0100 >> +%define PAGE_1G 0x80 >> + >> +%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ >> + PAGE_READ_WRITE + \ >> + PAGE_PRESENT) >> + >> +%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \ >> + PAGE_READ_WRITE + \ >> + PAGE_PRESENT + \ >> + PAGE_1G) >> + >> +%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define >> +PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) >> + >> +%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ >> + PAGE_PDP_ATTR) >> + >> +%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR) >> + >> +ALIGN 16 >> + >> +TopLevelPageDirectory: >> + >> + ; >> + ; Top level Page Directory Pointers (1 * 512GB entry) >> + ; >> + DQ PDP(0x1000) >> + >> + >> + TIMES 0x1000-PGTBLS_OFFSET($) DB 0 >> + ; >> + ; Next level Page Directory Pointers (512 * 1GB entries => 512GB) >> + ; >> +%assign i 0 >> +%rep 512 >> + DQ PDP_1G(i) >> + %assign i i+1 >> +%endrep >> + >> + >> +EndOfPageTables: >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm >> b/UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm >> similarity index 100% >> rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm >> rename to UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm >> -- >> 2.32.0.windows.1 >> ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity 2021-07-22 16:57 ` Ashraf Ali S @ 2021-07-23 2:37 ` Ni, Ray 0 siblings, 0 replies; 8+ messages in thread From: Ni, Ray @ 2021-07-23 2:37 UTC (permalink / raw) To: S, Ashraf Ali, Dov Murik, Ard Biesheuvel, Brijesh Singh, James Bottomley, Erdem Aktas, Tom Lendacky, Xu, Min M Cc: devel@edk2.groups.io, Ard Biesheuvel, Justen, Jordan L, Agyeman, Prince, Kumar, Rahul1, De, Debkumar, Han, Harry, West, Catharine, V, Sangeetha Ashraf, Thanks for the summary. Can you send a V2 patch which only take cares the 1G page table assembly logic? Thanks, Ray > -----Original Message----- > From: S, Ashraf Ali <ashraf.ali.s@intel.com> > Sent: Friday, July 23, 2021 12:58 AM > To: Ni, Ray <ray.ni@intel.com>; Dov Murik <dovmurik@linux.ibm.com>; Ard Biesheuvel <ardb@kernel.org>; Brijesh Singh > <brijesh.singh@amd.com>; James Bottomley <jejb@linux.ibm.com>; Erdem Aktas <erdemaktas@google.com>; Tom Lendacky > <thomas.lendacky@amd.com>; Xu, Min M <min.m.xu@intel.com> > Cc: devel@edk2.groups.io; Ard Biesheuvel <ardb+tianocore@kernel.org>; Justen, Jordan L <jordan.l.justen@intel.com>; > Agyeman, Prince <prince.agyeman@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, Debkumar > <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; West, Catharine <catharine.west@intel.com>; V, Sangeetha > <sangeetha.v@intel.com> > Subject: RE: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity > > Hi. Ray > Based on Dov Murik <dovmurik@linux.ibm.com> Comments to take the python script changes separately, > I have filed the Bugzilla for that separately. > https://bugzilla.tianocore.org/show_bug.cgi?id=3506 > > verified the binary. More details are in Bugzilla. > > Regards, > Ashraf Ali S > Intel Technology India Pvt. Ltd. > > -----Original Message----- > From: Ni, Ray <ray.ni@intel.com> > Sent: Wednesday, July 21, 2021 3:00 PM > To: Dov Murik <dovmurik@linux.ibm.com>; Ard Biesheuvel <ardb@kernel.org>; Brijesh Singh <brijesh.singh@amd.com>; James > Bottomley <jejb@linux.ibm.com>; Erdem Aktas <erdemaktas@google.com>; Tom Lendacky <thomas.lendacky@amd.com>; Xu, > Min M <min.m.xu@intel.com> > Cc: S, Ashraf Ali <ashraf.ali.s@intel.com>; devel@edk2.groups.io; Ard Biesheuvel <ardb+tianocore@kernel.org>; Justen, Jordan > L <jordan.l.justen@intel.com>; Agyeman, Prince <prince.agyeman@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, > Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; West, Catharine <catharine.west@intel.com>; V, > Sangeetha <sangeetha.v@intel.com> > Subject: RE: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity > > OVMF's ResetVector is including the UefiCpuPkg's ResetVector. So, OVMF owners please do evaluate the impact. > > I think this change assumes platform owner knows which format of page table should be chosen in build time. > > -----Original Message----- > From: Dov Murik <dovmurik@linux.ibm.com> > Sent: Tuesday, July 20, 2021 4:02 AM > To: Ard Biesheuvel <ardb@kernel.org>; Ni, Ray <ray.ni@intel.com>; Brijesh Singh <brijesh.singh@amd.com>; James Bottomley > <jejb@linux.ibm.com>; Erdem Aktas <erdemaktas@google.com>; Tom Lendacky <thomas.lendacky@amd.com> > Cc: S, Ashraf Ali <ashraf.ali.s@intel.com>; devel@edk2.groups.io; Ard Biesheuvel <ardb+tianocore@kernel.org>; Justen, Jordan > L <jordan.l.justen@intel.com>; Agyeman, Prince <prince.agyeman@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, > Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; West, Catharine <catharine.west@intel.com>; V, > Sangeetha <sangeetha.v@intel.com> > Subject: Re: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity > > > > On 19/07/2021 10:09, Ard Biesheuvel wrote: > > On Mon, 19 Jul 2021 at 05:14, Ni, Ray <ray.ni@intel.com> wrote: > >> > >> This change generates the reset vector binary which only contains 1G page table. If a platform doesn't support 1G page table, > this will cause system hang. > >> > >> To Ard and Jordan, > >> Can you evaluate whether this change impacts OVMF? > >> > > > > I don't have a clue, sorry, and I wouldn't know where to begin looking. > > > > Brijesh, Dov, James, Erdem: after Laszlo's sudden departure, I will be > > needing help reviewing OVMF patches that are highly specific to > > SEV/SNP or x86 in general. > > Adding Tom too - I think he modified the OVMF reset vector lately and might know. > > > > > Please take a look. > > > I'm not an expert, but I think that OVMF has its own reset vector in OvmfPkg/ResetVector, and therefore the changes in > uefiCpuPkg will not affect OVMF. > > > Regarding the patch itself: > > (1) I suggest separating the python tooling changes to one patch, verifying that the new python scripts generate the same binary > files as the original python scripts. Then add another patch which introduces the reset vector changes. > > (2) Do all x64 CPUs support 1 GB pages? Is it always enabled? Do we need to check this capability somewhere? > > > -Dov > > > > > > > >> To Prince, > >> Can you evaluate whether this change impacts SimicsOpenBoardPkg? > >> > >> Thanks, > >> Ray > >> > >> -----Original Message----- > >> From: S, Ashraf Ali <ashraf.ali.s@intel.com> > >> Sent: Friday, July 2, 2021 8:25 PM > >> To: devel@edk2.groups.io > >> Cc: S, Ashraf Ali <ashraf.ali.s@intel.com>; Ni, Ray > >> <ray.ni@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, > >> Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; > >> West, Catharine <catharine.west@intel.com>; V, Sangeetha > >> <sangeetha.v@intel.com> > >> Subject: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte > >> Page Granularity > >> > >> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473 > >> > >> X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when > user wants to use more than 4G using 2M Page it will leads to use more number of Page table entries. using the 1-GByte Page > table user can use more than 4G Memory by reducing the page table entries using 1-GByte Page, this patch attached can access > memory range till 512GByte. > >> Build Scrips for Reset Vector currently based on Python 2 which is already EOL, needs to modify the build script based on > Python 3, update the Binary accordingly. > >> > >> Cc: Ray Ni <ray.ni@intel.com> > >> Cc: Rahul Kumar <rahul1.kumar@intel.com> > >> Cc: Debkumar De <debkumar.de@intel.com> > >> Cc: Harry Han <harry.han@intel.com> > >> Cc: Catharine West <catharine.west@intel.com> > >> Cc: Sangeetha V <sangeetha.v@intel.com> > >> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com> > >> --- > >> .../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 516 -> 484 bytes > >> .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes > >> .../Vtf0/Bin/ResetVector.ia32.serial.raw | Bin 884 -> 868 bytes > >> .../Vtf0/Bin/ResetVector.x64.port80.raw | Bin 28676 -> 12292 bytes > >> .../ResetVector/Vtf0/Bin/ResetVector.x64.raw | Bin 28676 -> 12292 bytes > >> .../Vtf0/Bin/ResetVector.x64.serial.raw | Bin 28676 -> 12292 bytes > >> UefiCpuPkg/ResetVector/Vtf0/Build.py | 11 +-- > >> .../ResetVector/Vtf0/Ia32/PageTables64.asm | 2 +- > >> UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 2 +- > >> .../Vtf0/Tools/FixupForRawSection.py | 4 +- > >> UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 4 +- > >> .../ResetVector/Vtf0/X64/1GPageTables.asm | 64 ++++++++++++++++++ > >> .../X64/{PageTables.asm => 2MPageTables.asm} | 0 > >> 13 files changed, 77 insertions(+), 10 deletions(-) create mode > >> 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm > >> rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => > >> 2MPageTables.asm} (100%) > >> > >> diff --git > >> a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw > >> b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw > >> index > >> 2c6ff655ded2a5855ca8f4428d559a7727eb6983..79b23c047bdc6e552d77d5c9e9a > >> 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zpMBufw?FB^4<Ft+ZuqXVZ@cc>&pzsoAE@(BJaz7dldnDOd1s%y;o_T5zT>dNt$p!L > >> zcfRY~3m<uaXRbM*|NH5legFUY75*Pi@jcgFJ+iZRTz}Ky5TE<zFZzNyf9l4wHy^$} > >> z@$B<oeba>>y?Q=}Gyjb1ub%lGFM0ZVPk!+5)b)=(Y@NCAaW8%4xsN^l+E+aPy8A9X > >> z?`5BK_&A?=>P62u`G~_`KD5Wh`_5c=-pgNk?n6$!=yBIS<M8b1*M8Pxo_YVt^@oS| > >> z9R9?~+uwiX$~`exuAIK*{?j+l>3biz{`4*LZ57d{pMBVR-05eXzPS$%o_hM0e#iO4 > >> z-Zx!yl|1K~Y5VAFw*NPu>jxZ8+LiY1s~6g>m;cwT=R9KT36I!%{N<l{UHrsdZ+qPr > >> zUiqjqr>}eRnR`C$a6KFj?aVu#beNVK<DPuX;Vf^NM}9E3U2{y&zGnLu9^;vN9v64r > >> ze^=i%cRg^|TTWhbn5#=qjXJ!?&o3@lC-CZc=zrnA?0X*e>weB}jn}{MWe<MP>p$^j > >> z58iO*;u}u#y@!kU<R`D3Jo?JXOW%9t%E>M7JAA3bjNX3F;bkBC7rNV@_NLpP_Qu<v > >> j_J-Rp&Xu=6c;CbCb@e@7{+Tb1OP3z}mY;w3OP78Y>oK+# > >> > >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py > >> b/UefiCpuPkg/ResetVector/Vtf0/Build.py > >> index 343c53b5ff..29f29ff0c2 100644 > >> --- a/UefiCpuPkg/ResetVector/Vtf0/Build.py > >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Build.py > >> @@ -1,7 +1,7 @@ > >> ## @file > >> # Automate the process of building the various reset vector types > >> # -# Copyright (c) 2009, Intel Corporation. All rights reserved.<BR> > >> +# Copyright (c) 2009 - 2021, Intel Corporation. All rights > >> +reserved.<BR> > >> # > >> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -32,16 +32,19 @@ for arch in ('ia32', 'x64'): > >> '-o', output, > >> 'Vtf0.nasmb', > >> ) > >> + print(f"Command : {' '.join(commandLine)}") > >> ret = RunCommand(commandLine) > >> - print '\tASM\t' + output > >> - if ret != 0: sys.exit(ret) > >> + if ret != 0: > >> + print(f"something went wrong while executing the {commandLine[-1]}") > >> + sys.exit() > >> + print('\tASM\t' + output) > >> > >> commandLine = ( > >> 'python', > >> 'Tools/FixupForRawSection.py', > >> output, > >> ) > >> - print '\tFIXUP\t' + output > >> + print('\tFIXUP\t' + output) > >> ret = RunCommand(commandLine) > >> if ret != 0: sys.exit(ret) > >> > >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > >> b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > >> index 87a4125d4b..9cc6f56c17 100644 > >> --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > >> @@ -15,7 +15,7 @@ BITS 32 > >> SetCr3ForPageTables64: > >> > >> ; > >> - ; These pages are built into the ROM image in X64/PageTables.asm > >> + ; These pages are built into the ROM image in > >> + X64/1GPageTables.asm > >> ; > >> mov eax, ADDR_OF(TopLevelPageDirectory) > >> mov cr3, eax > >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt > >> b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt > >> index e6e5b54243..eb9dd24ee2 100644 > >> --- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt > >> +++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt > >> @@ -29,7 +29,7 @@ EBP/RBP - Pointer to the start of the Boot Firmware > >> Volume === HOW TO BUILD VTF0 === > >> > >> Dependencies: > >> -* Python 2.5~2.7 > >> +* Python 3.0 or newer > >> * Nasm 2.03 or newer > >> > >> To rebuild the VTF0 binaries: > >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py > >> b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py > >> index c77438a0ce..de771eba22 100644 > >> --- a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py > >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py > >> @@ -1,7 +1,7 @@ > >> ## @file > >> # Apply fixup to VTF binary image for FFS Raw section # -# > >> Copyright (c) 2008, Intel Corporation. All rights reserved.<BR> > >> +# Copyright (c) 2008 - 2021, Intel Corporation. All rights > >> +reserved.<BR> > >> # > >> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -15,6 +15,6 @@ c = ((len(d) + 4 + 7) & ~7) - 4 if c > len(d): > >> c -= len(d) > >> f = open(sys.argv[1], 'wb') > >> - f.write('\x90' * c) > >> + f.write(b'\x90' * c) > >> f.write(d) > >> f.close() > >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > >> b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > >> index 493738c79c..0625efc456 100644 > >> --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > >> +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > >> @@ -2,7 +2,7 @@ > >> ; @file > >> ; This file includes all other code files to assemble the reset > >> vector code ; -; Copyright (c) 2008 - 2013, Intel Corporation. All > >> rights reserved.<BR> > >> +; Copyright (c) 2008 - 2021, Intel Corporation. All rights > >> +reserved.<BR> > >> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; > >> > >> ;-------------------------------------------------------------------- > >> ---------- > >> @@ -36,7 +36,7 @@ > >> %include "PostCodes.inc" > >> > >> %ifdef ARCH_X64 > >> -%include "X64/PageTables.asm" > >> +%include "X64/1GPageTables.asm" > >> %endif > >> > >> %ifdef DEBUG_PORT80 > >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm > >> b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm > >> new file mode 100644 > >> index 0000000000..8ae6c4c98c > >> --- /dev/null > >> +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm > >> @@ -0,0 +1,64 @@ > >> +;------------------------------------------------------------------- > >> +--- > >> +-------- > >> +; @file > >> +; Emits Page Tables for 1:1 mapping of the addresses 0 - > >> +0x8000000000 > >> +(512GB) ; ; Copyright (c) 2021, Intel Corporation. All rights > >> +reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; > >> +Linear-Address Translation to a 1-GByte Page ; > >> +;------------------------------------------------------------------- > >> +--- > >> +-------- > >> + > >> +BITS 64 > >> + > >> +%define ALIGN_TOP_TO_4K_FOR_PAGING > >> + > >> +%define PAGE_PRESENT 0x01 > >> +%define PAGE_READ_WRITE 0x02 > >> +%define PAGE_USER_SUPERVISOR 0x04 > >> +%define PAGE_WRITE_THROUGH 0x08 > >> +%define PAGE_CACHE_DISABLE 0x010 > >> +%define PAGE_ACCESSED 0x020 > >> +%define PAGE_DIRTY 0x040 > >> +%define PAGE_PAT 0x080 > >> +%define PAGE_GLOBAL 0x0100 > >> +%define PAGE_1G 0x80 > >> + > >> +%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ > >> + PAGE_READ_WRITE + \ > >> + PAGE_PRESENT) > >> + > >> +%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \ > >> + PAGE_READ_WRITE + \ > >> + PAGE_PRESENT + \ > >> + PAGE_1G) > >> + > >> +%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define > >> +PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) > >> + > >> +%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ > >> + PAGE_PDP_ATTR) > >> + > >> +%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR) > >> + > >> +ALIGN 16 > >> + > >> +TopLevelPageDirectory: > >> + > >> + ; > >> + ; Top level Page Directory Pointers (1 * 512GB entry) > >> + ; > >> + DQ PDP(0x1000) > >> + > >> + > >> + TIMES 0x1000-PGTBLS_OFFSET($) DB 0 > >> + ; > >> + ; Next level Page Directory Pointers (512 * 1GB entries => 512GB) > >> + ; > >> +%assign i 0 > >> +%rep 512 > >> + DQ PDP_1G(i) > >> + %assign i i+1 > >> +%endrep > >> + > >> + > >> +EndOfPageTables: > >> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm > >> b/UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm > >> similarity index 100% > >> rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm > >> rename to UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm > >> -- > >> 2.32.0.windows.1 > >> ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-07-23 2:37 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-07-02 12:25 [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity Ashraf Ali S 2021-07-19 3:14 ` Ni, Ray 2021-07-19 7:09 ` Ard Biesheuvel 2021-07-19 20:01 ` [edk2-devel] " Lendacky, Thomas 2021-07-19 20:02 ` Dov Murik 2021-07-21 9:30 ` Ni, Ray 2021-07-22 16:57 ` Ashraf Ali S 2021-07-23 2:37 ` Ni, Ray
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