From: "Gerd Hoffmann" <kraxel@redhat.com>
To: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: devel@edk2.groups.io, Eric Dong <eric.dong@intel.com>,
Ray Ni <ray.ni@intel.com>, Rahul Kumar <rahul1.kumar@intel.com>,
Debkumar De <debkumar.de@intel.com>,
Catharine West <catharine.west@intel.com>
Subject: Re: [PATCH 2/2] UefiCpuPkg: Support 5 level page table in ResetVector
Date: Mon, 3 Apr 2023 13:55:44 +0200 [thread overview]
Message-ID: <2oe66me7kd474drxptj6rcjxh7bf25cnq7sunvrvtizgkfetyo@vmiqncl6r32b> (raw)
In-Reply-To: <20230403092814.1709-1-zhiguang.liu@intel.com>
On Mon, Apr 03, 2023 at 05:28:14PM +0800, Zhiguang Liu wrote:
> Use a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create
> 5 level page table. Whether creating it or not, the highest level
> page table address is fixed.
Can we create the 5level page table unconditionally?
We should have the PML5 table @ fixed at 4G - 12k and the PML4 table
fixed at 4G - 16k then. Then ideally check processor capabilities and
decide at runtime whenever to use 4level or 5level paging.
thanks,
Gerd
next prev parent reply other threads:[~2023-04-03 11:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-03 9:28 [PATCH 2/2] UefiCpuPkg: Support 5 level page table in ResetVector Zhiguang Liu
2023-04-03 11:55 ` Gerd Hoffmann [this message]
2023-04-14 7:09 ` [edk2-devel] " Zhiguang Liu
2023-04-14 10:04 ` Gerd Hoffmann
2023-04-15 5:02 ` Ni, Ray
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