From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124])
 by mx.groups.io with SMTP id smtpd.web10.67990.1680522974881614531
 for <devel@edk2.groups.io>;
 Mon, 03 Apr 2023 04:56:15 -0700
Authentication-Results: mx.groups.io;
 dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=J8GG4dDJ;
 spf=pass (domain: redhat.com, ip: 170.10.133.124, mailfrom: kraxel@redhat.com)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;
	s=mimecast20190719; t=1680522974;
	h=from:from:reply-to:subject:subject:date:date:message-id:message-id:
	 to:to:cc:cc:mime-version:mime-version:content-type:content-type:
	 in-reply-to:in-reply-to:references:references;
	bh=EzvbNeGBURo6xcMCo0e2e8+LsBPZvHNGylJyNALvTfY=;
	b=J8GG4dDJzZqCuvqgMGv+Lwyy85H9dyEkluT9/HRWCHU+L0cRbv0lPl9NJmtFQsyh8TDqgx
	ucXyqctGQiBOU9x4YukmuZ9QbEwJnrTFOzG2W0nRsfBkq7mWSi11FYFoOdnH07298e/aQ2
	w341COpNH4zM4elEhqshrgHCpAwWixg=
Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com
 [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS
 (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id
 us-mta-64-bZC2GPQbMZ6J-qaahe1lDw-1; Mon, 03 Apr 2023 07:56:11 -0400
X-MC-Unique: bZC2GPQbMZ6J-qaahe1lDw-1
Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10])
	(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))
	(No client certificate requested)
	by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 919CB811E7C;
	Mon,  3 Apr 2023 11:56:10 +0000 (UTC)
Received: from sirius.home.kraxel.org (unknown [10.39.193.241])
	by smtp.corp.redhat.com (Postfix) with ESMTPS id 586CA483EC1;
	Mon,  3 Apr 2023 11:56:09 +0000 (UTC)
Received: by sirius.home.kraxel.org (Postfix, from userid 1000)
	id AC9DF1800393; Mon,  3 Apr 2023 13:55:44 +0200 (CEST)
Date: Mon, 3 Apr 2023 13:55:44 +0200
From: "Gerd Hoffmann" <kraxel@redhat.com>
To: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: devel@edk2.groups.io, Eric Dong <eric.dong@intel.com>, 
	Ray Ni <ray.ni@intel.com>, Rahul Kumar <rahul1.kumar@intel.com>, 
	Debkumar De <debkumar.de@intel.com>, Catharine West <catharine.west@intel.com>
Subject: Re: [PATCH 2/2] UefiCpuPkg: Support 5 level page table in ResetVector
Message-ID: <2oe66me7kd474drxptj6rcjxh7bf25cnq7sunvrvtizgkfetyo@vmiqncl6r32b>
References: <20230403092814.1709-1-zhiguang.liu@intel.com>
MIME-Version: 1.0
In-Reply-To: <20230403092814.1709-1-zhiguang.liu@intel.com>
X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10
X-Mimecast-Spam-Score: 0
X-Mimecast-Originator: redhat.com
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline

On Mon, Apr 03, 2023 at 05:28:14PM +0800, Zhiguang Liu wrote:
> Use a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create
> 5 level page table. Whether creating it or not, the highest level
> page table address is fixed.

Can we create the 5level page table unconditionally?

We should have the PML5 table @ fixed at 4G - 12k and the PML4 table
fixed at 4G - 16k then.  Then ideally check processor capabilities and
decide at runtime whenever to use 4level or 5level paging.

thanks,
  Gerd