From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web11.16777.1663566840953220069 for ; Sun, 18 Sep 2022 22:54:01 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=Cgd8tFXQ; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: ashraf.ali.s@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663566841; x=1695102841; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=8F6iLF2nQ5jJyR1W6NP78326d+3l9X7f44JLjwyZYY4=; b=Cgd8tFXQyS5//elGcYUuk7/BxFwGnfWC/1XodxlNBcfA+OrTh4yvoRMf srEgUFOwrcBgs45hPFNBIniprZdryWZLPpkPEjO3lXl3/AXSW6aFQDJDf mi57fr0Aiho3cm8TWMVm7CHD7/Eg3RfyjVbG2lEoHPqJnCh2LsgQUWx/3 LIohthlyIi3cL7felPu5eVxyrf5PCkZB51hmQAOQrJn2rkjeC/H/52IO6 leEyqBsblxuO9kojNL/HeiNIwQ6N5KyB2m+VgKcjLKg1dmhfZw7kej3Ef 0mQUkRb1mxtTXRfIWHZUUCByQo7umLaM9QXfxtEBJrv5LqTkoP2bDF2GI g==; X-IronPort-AV: E=McAfee;i="6500,9779,10474"; a="325598324" X-IronPort-AV: E=Sophos;i="5.93,327,1654585200"; d="scan'208";a="325598324" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2022 22:54:00 -0700 X-IronPort-AV: E=Sophos;i="5.93,327,1654585200"; d="scan'208";a="595945993" Received: from basfe004.gar.corp.intel.com ([10.66.129.57]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2022 22:53:57 -0700 From: "Ashraf Ali S" To: devel@edk2.groups.io Cc: Ashraf Ali S , Ray Ni , Rangasai V Chaganty , Isaac Oram , Chasel Chiu , Nate DeSimone , Liming Gao , Eric Dong Subject: [PATCH] FIX MinPlatformPkg PCIE Base Addess avoid thunking operation. Date: Mon, 19 Sep 2022 11:23:01 +0530 Message-Id: <30041569f0c8cb2639d4526b0464d80a91fb3b0b.1663566735.git.ashraf.ali.s@intel.com> X-Mailer: git-send-email 2.30.2.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit thunking the PCIE base address will cause the distruption in the execution flow when the PCIE base address is 64bit bit. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4068 Signed-off-by: Ashraf Ali S Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Isaac Oram Cc: Chasel Chiu Cc: Nate DeSimone Cc: Isaac Oram Cc: Liming Gao Cc: Eric Dong --- .../Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c index 0e3fee28b5..e38975eee5 100644 --- a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c +++ b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c @@ -90,7 +90,7 @@ PciHostBridgeGetRootBridges ( if (PcdGet32(PcdPciReservedMemLimit) != 0) { mRootBridgeTemplate.Mem.Limit = PcdGet32 (PcdPciReservedMemLimit); } else { - mRootBridgeTemplate.Mem.Limit = (UINT32) PcdGet64 (PcdPciExpressBaseAddress) - 1; + mRootBridgeTemplate.Mem.Limit = PcdGet64 (PcdPciExpressBaseAddress) - 1; } mRootBridgeTemplate.MemAbove4G.Base = PcdGet64 (PcdPciReservedMemAbove4GBBase); -- 2.30.2.windows.1