From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.8480.1648454962517853012 for ; Mon, 28 Mar 2022 01:09:40 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=SCbfWU9a; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: min.m.xu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648454980; x=1679990980; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rh8Pg+L93ZumSgHtZ8cuyKtw9jHKgLMDGbZoMOCkaGg=; b=SCbfWU9aC3K1x/b3ttaDlec1u8fFWEmSf49QFi/JhBxLp4RGeotaGjuv S0m5O6uaedZeD9KLk2HcmYwMb3XB/6oEynNshobazvy1By98HAlb3U/EK Bt2LQtj+Wzvfn+rBJK7CfJn2M2DHaB5sIn6XHr5PwD6hE5GmmeJOkbcpo S6rGTWpi4uRtYj9YOjTWpwPc2Z66Cmfe/Xp1Bt9pUB7dy8JAXr0IpIdrW aYxsKKCv4GSXIDum1rTeZVnqhfw95BHudP1JHpvqGrhXMI7RficFnUL1f NWKEVmFcONdjTKs6DV4/1C8GGpp9hFXvOjXtW7vOIjsEWstuy75H5tzog A==; X-IronPort-AV: E=McAfee;i="6200,9189,10299"; a="257770878" X-IronPort-AV: E=Sophos;i="5.90,216,1643702400"; d="scan'208";a="257770878" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Mar 2022 01:09:35 -0700 X-IronPort-AV: E=Sophos;i="5.90,216,1643702400"; d="scan'208";a="563427227" Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.167]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Mar 2022 01:09:32 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [PATCH V11 17/47] OvmfPkg: Create initial version of PlatformInitLib Date: Mon, 28 Mar 2022 16:07:56 +0800 Message-Id: <31487f723f3e9dcf4fc9569f1e5a9ec01d95578f.1648454441.git.min.m.xu@intel.com> X-Mailer: git-send-email 2.29.2.windows.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 There are 3 variants of PlatformPei in OvmfPkg: - OvmfPkg/PlatformPei - OvmfPkg/XenPlatformPei - OvmfPkg/Bhyve/PlatformPei/PlatformPei.inf These PlatformPeis can share many common codes, such as Cmos / Hob / Memory / Platform related functions. This commit (and its following several patches) are to create a PlatformInitLib which wraps the common code called in above PlatformPeis. In this initial version of PlatformInitLib, below Cmos related functions are introduced: - PlatformCmosRead8 - PlatformCmosWrite8 - PlatformDebugDumpCmos They correspond to the functions in OvmfPkg/PlatformPei: - CmosRead8 - CmosWrite8 - DebugDumpCmos Considering this PlatformInitLib will be used in SEC phase, global variables and dynamic PCDs are avoided. We use PlatformInfoHob to exchange information between functions. EFI_HOB_PLATFORM_INFO is the data struct which contains the platform information, such as HostBridgeDevId, BootMode, S3Supported, SmmSmramRequire, etc. After PlatformInitLib is created, OvmfPkg/PlatformPei is refactored with this library. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/AmdSev/AmdSevX64.dsc | 1 + OvmfPkg/CloudHv/CloudHvX64.dsc | 1 + OvmfPkg/Include/Library/PlatformInitLib.h | 99 +++++++++++++++++++ .../PlatformInitLib}/Cmos.c | 32 +++++- .../PlatformInitLib/PlatformInitLib.inf | 36 +++++++ OvmfPkg/Microvm/MicrovmX64.dsc | 1 + OvmfPkg/OvmfPkg.dec | 4 + OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 1 + OvmfPkg/PlatformPei/Cmos.h | 48 --------- OvmfPkg/PlatformPei/MemDetect.c | 8 +- OvmfPkg/PlatformPei/Platform.c | 29 +----- OvmfPkg/PlatformPei/PlatformPei.inf | 3 +- 14 files changed, 183 insertions(+), 82 deletions(-) create mode 100644 OvmfPkg/Include/Library/PlatformInitLib.h rename OvmfPkg/{PlatformPei => Library/PlatformInitLib}/Cmos.c (61%) create mode 100644 OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf delete mode 100644 OvmfPkg/PlatformPei/Cmos.h diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc index fd56176796d5..785049c88962 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.dsc +++ b/OvmfPkg/AmdSev/AmdSevX64.dsc @@ -280,6 +280,7 @@ !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf [LibraryClasses.common.DXE_CORE] HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index b4d855d80f56..b8a82380202c 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -307,6 +307,7 @@ !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf [LibraryClasses.common.DXE_CORE] HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Library/PlatformInitLib.h new file mode 100644 index 000000000000..2ebac5ccb013 --- /dev/null +++ b/OvmfPkg/Include/Library/PlatformInitLib.h @@ -0,0 +1,99 @@ +/** @file + PlatformInitLib header file. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PLATFORM_INIT_LIB_H_ +#define PLATFORM_INIT_LIB_H_ + +#include + +#pragma pack(1) +typedef struct { + EFI_HOB_GUID_TYPE GuidHeader; + UINT16 HostBridgeDevId; + + UINT64 PcdConfidentialComputingGuestAttr; + BOOLEAN SevEsIsEnabled; + + UINT32 BootMode; + BOOLEAN S3Supported; + + BOOLEAN SmmSmramRequire; + BOOLEAN Q35SmramAtDefaultSmbase; + UINT16 Q35TsegMbytes; + + UINT64 FirstNonAddress; + UINT8 PhysMemAddressWidth; + UINT32 Uc32Base; + UINT32 Uc32Size; + + BOOLEAN PcdSetNxForStack; + UINT64 PcdTdxSharedBitMask; + + UINT64 PcdPciMmio64Base; + UINT64 PcdPciMmio64Size; + UINT32 PcdPciMmio32Base; + UINT32 PcdPciMmio32Size; + UINT64 PcdPciIoBase; + UINT64 PcdPciIoSize; + + UINT64 PcdEmuVariableNvStoreReserved; + UINT32 PcdCpuBootLogicalProcessorNumber; + UINT32 PcdCpuMaxLogicalProcessorNumber; + UINT32 DefaultMaxCpuNumber; + + UINT32 S3AcpiReservedMemoryBase; + UINT32 S3AcpiReservedMemorySize; +} EFI_HOB_PLATFORM_INFO; +#pragma pack() + +/** + Reads 8-bits of CMOS data. + + Reads the 8-bits of CMOS data at the location specified by Index. + The 8-bit read value is returned. + + @param Index The CMOS location to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +PlatformCmosRead8 ( + IN UINTN Index + ); + +/** + Writes 8-bits of CMOS data. + + Writes 8-bits of CMOS data to the location specified by Index + with the value specified by Value and returns Value. + + @param Index The CMOS location to write. + @param Value The value to write to CMOS. + + @return The value written to CMOS. + +**/ +UINT8 +EFIAPI +PlatformCmosWrite8 ( + IN UINTN Index, + IN UINT8 Value + ); + +/** + Dump the CMOS content + */ +VOID +EFIAPI +PlatformDebugDumpCmos ( + VOID + ); + +#endif // PLATFORM_INIT_LIB_H_ diff --git a/OvmfPkg/PlatformPei/Cmos.c b/OvmfPkg/Library/PlatformInitLib/Cmos.c similarity index 61% rename from OvmfPkg/PlatformPei/Cmos.c rename to OvmfPkg/Library/PlatformInitLib/Cmos.c index a01b3866bee4..977aa97aea8c 100644 --- a/OvmfPkg/PlatformPei/Cmos.c +++ b/OvmfPkg/Library/PlatformInitLib/Cmos.c @@ -6,7 +6,8 @@ **/ -#include "Cmos.h" +#include +#include #include "Library/IoLib.h" /** @@ -22,7 +23,7 @@ **/ UINT8 EFIAPI -CmosRead8 ( +PlatformCmosRead8 ( IN UINTN Index ) { @@ -44,7 +45,7 @@ CmosRead8 ( **/ UINT8 EFIAPI -CmosWrite8 ( +PlatformCmosWrite8 ( IN UINTN Index, IN UINT8 Value ) @@ -53,3 +54,28 @@ CmosWrite8 ( IoWrite8 (0x71, Value); return Value; } + +/** + Dump the CMOS content + */ +VOID +EFIAPI +PlatformDebugDumpCmos ( + VOID + ) +{ + UINT32 Loop; + + DEBUG ((DEBUG_INFO, "CMOS:\n")); + + for (Loop = 0; Loop < 0x80; Loop++) { + if ((Loop % 0x10) == 0) { + DEBUG ((DEBUG_INFO, "%02x:", Loop)); + } + + DEBUG ((DEBUG_INFO, " %02x", PlatformCmosRead8 (Loop))); + if ((Loop % 0x10) == 0xf) { + DEBUG ((DEBUG_INFO, "\n")); + } + } +} diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf new file mode 100644 index 000000000000..4ea2da86274f --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf @@ -0,0 +1,36 @@ +## @file +# Platform Initialization Lib +# +# This module provides platform specific function to detect boot mode. +# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformInitLib + FILE_GUID = 89f886b0-7109-46e1-9d28-503ad4ab6ee0 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformInitLib|PEIM + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 EBC +# + +[Sources] + Cmos.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc index 1ea43443ae97..27005eec89f2 100644 --- a/OvmfPkg/Microvm/MicrovmX64.dsc +++ b/OvmfPkg/Microvm/MicrovmX64.dsc @@ -300,6 +300,7 @@ QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf [LibraryClasses.common.DXE_CORE] HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index d373b5d6042e..61635c73c761 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -113,6 +113,10 @@ # TdxMailboxLib|Include/Library/TdxMailboxLib.h + ## @libraryclass PlatformInitLib + # + PlatformInitLib|Include/Library/PlatformInitLib.h + [Guids] gUefiOvmfPkgTokenSpaceGuid = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}} gEfiXenInfoGuid = {0xd3b46f3b, 0xd441, 0x1244, {0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}} diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 85abed24c1a7..8f02dca63869 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -300,6 +300,7 @@ QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index a9c1daecc1a8..c58ef8494470 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -304,6 +304,7 @@ QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 718399299f57..227b9845619f 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -305,6 +305,7 @@ QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc diff --git a/OvmfPkg/PlatformPei/Cmos.h b/OvmfPkg/PlatformPei/Cmos.h deleted file mode 100644 index 2b3124d7ba36..000000000000 --- a/OvmfPkg/PlatformPei/Cmos.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - PC/AT CMOS access routines - - Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef __CMOS_H__ -#define __CMOS_H__ - -/** - Reads 8-bits of CMOS data. - - Reads the 8-bits of CMOS data at the location specified by Index. - The 8-bit read value is returned. - - @param Index The CMOS location to read. - - @return The value read. - -**/ -UINT8 -EFIAPI -CmosRead8 ( - IN UINTN Index - ); - -/** - Writes 8-bits of CMOS data. - - Writes 8-bits of CMOS data to the location specified by Index - with the value specified by Value and returns Value. - - @param Index The CMOS location to write. - @param Value The value to write to CMOS. - - @return The value written to CMOS. - -**/ -UINT8 -EFIAPI -CmosWrite8 ( - IN UINTN Index, - IN UINT8 Value - ); - -#endif diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c index 8ecc8257f9b9..9c5bf240e3ba 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -37,9 +37,9 @@ Module Name: #include #include #include +#include #include "Platform.h" -#include "Cmos.h" UINT8 mPhysMemAddressWidth; @@ -412,8 +412,8 @@ GetSystemMemorySizeBelow4gb ( // into the calculation to get the total memory size. // - Cmos0x34 = (UINT8)CmosRead8 (0x34); - Cmos0x35 = (UINT8)CmosRead8 (0x35); + Cmos0x34 = (UINT8)PlatformCmosRead8 (0x34); + Cmos0x35 = (UINT8)PlatformCmosRead8 (0x35); return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB); } @@ -436,7 +436,7 @@ GetSystemMemorySizeAbove4gb ( Size = 0; for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) { - Size = (UINT32)(Size << 8) + (UINT32)CmosRead8 (CmosIndex); + Size = (UINT32)(Size << 8) + (UINT32)PlatformCmosRead8 (CmosIndex); } return LShiftU64 (Size, 16); diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index d0323c645162..594891786440 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -36,10 +36,10 @@ #include #include #include +#include #include #include "Platform.h" -#include "Cmos.h" EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = { { @@ -505,11 +505,11 @@ BootModeInitialization ( { EFI_STATUS Status; - if (CmosRead8 (0xF) == 0xFE) { + if (PlatformCmosRead8 (0xF) == 0xFE) { mBootMode = BOOT_ON_S3_RESUME; } - CmosWrite8 (0xF, 0x00); + PlatformCmosWrite8 (0xF, 0x00); Status = PeiServicesSetBootMode (mBootMode); ASSERT_EFI_ERROR (Status); @@ -546,27 +546,6 @@ ReserveEmuVariableNvStore ( ASSERT_RETURN_ERROR (PcdStatus); } -VOID -DebugDumpCmos ( - VOID - ) -{ - UINT32 Loop; - - DEBUG ((DEBUG_INFO, "CMOS:\n")); - - for (Loop = 0; Loop < 0x80; Loop++) { - if ((Loop % 0x10) == 0) { - DEBUG ((DEBUG_INFO, "%02x:", Loop)); - } - - DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop))); - if ((Loop % 0x10) == 0xf) { - DEBUG ((DEBUG_INFO, "\n")); - } - } -} - VOID S3Verification ( VOID @@ -810,7 +789,7 @@ InitializePlatform ( DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n")); - DebugDumpCmos (); + PlatformDebugDumpCmos (); if (QemuFwCfgS3Enabled ()) { DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n")); diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf index 212aa7b04751..f6bfc09c2dd5 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -25,8 +25,6 @@ [Sources] AmdSev.c ClearCache.c - Cmos.c - Cmos.h FeatureControl.c Fv.c MemDetect.c @@ -64,6 +62,7 @@ MemEncryptSevLib PcdLib VmgExitLib + PlatformInitLib [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase -- 2.29.2.windows.2