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dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=arm.com; Received: from AS8PR08MB6806.eurprd08.prod.outlook.com (2603:10a6:20b:39b::12) by AM5PR0801MB1779.eurprd08.prod.outlook.com (2603:10a6:203:2f::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.25; Mon, 10 May 2021 08:43:17 +0000 Received: from AS8PR08MB6806.eurprd08.prod.outlook.com ([fe80::80cb:878d:c8f1:2688]) by AS8PR08MB6806.eurprd08.prod.outlook.com ([fe80::80cb:878d:c8f1:2688%7]) with mapi id 15.20.4108.031; Mon, 10 May 2021 08:43:17 +0000 Subject: Re: [edk2-platforms][PATCH V2 1/8] Platform/Sgi: Helper macros for PPTT Table To: Pranav Madhu , devel@edk2.groups.io Cc: Ard Biesheuvel , Pierre Gondois References: <20210428121229.32674-1-pranav.madhu@arm.com> <20210428121229.32674-2-pranav.madhu@arm.com> From: "Sami Mujawar" Message-ID: <31c0b4fd-04ba-f202-5d84-2cd60881eebf@arm.com> Date: Mon, 10 May 2021 09:43:15 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2021 08:43:32.5256 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 944b3b94-2b00-45b5-1c7b-08d9138fb154 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT022.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6475 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Content-Language: en-GB Hi Pranav, Please find my response inline marked [SAMI]. Regards, Sami Mujawar On 28/04/2021 01:12 PM, Pranav Madhu wrote: > Add helper macros for the creation for PPTT table. These macros help > with initializing processor hierarchy node structure, cache type > structure and ID structure. > > Signed-off-by: Pranav Madhu > --- > Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 160 ++++++++++++++++++++ > 1 file changed, 160 insertions(+) > > diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/S= giPkg/Include/SgiAcpiHeader.h > index dcb4e6c77a74..7bb8b6dec6a3 100644 > --- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h > +++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h > @@ -20,6 +20,131 @@ > #define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ') > #define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099 > > +#define CORE_COUNT FixedPcdGet32 (PcdCoreCount) > +#define CLUSTER_COUNT FixedPcdGet32 (PcdClusterCount) > + > +#pragma pack(1) > +// PPTT processor core structure > +typedef struct { > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core; > + UINT32 ResourceOffset[2]; > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache; > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache; > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache; > +} RD_PPTT_CORE; > + > +// PPTT processor cluster structure > +typedef struct { > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; > + UINT32 ResourceOffset; > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache; > + RD_PPTT_CORE Core[CORE_COUNT]; > +} RD_PPTT_CLUSTER; > + > +// PPTT processor cluster structure without cache > +typedef struct { > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; > + RD_PPTT_CORE Core[CORE_COUNT]; > +} RD_PPTT_MINIMAL_CLUSTER; > + > +// PPTT processor package structure > +typedef struct { > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; > + UINT32 ResourceOffset; > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; > + RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT]; > +} RD_PPTT_SLC_PACKAGE; > +#pragma pack () > + > +// > +// PPTT processor structure flags for different SoC components as define= d in > +// ACPI 6.3 specification > +// > + > +// Processor structure flags for SoC package > +#define PPTT_PROCESSOR_PACKAGE_FLAGS = \ > + { = \ > + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, = \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, = \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ > + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, = \ > + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL = \ > + } > + > +// Processor structure flags for cluster > +#define PPTT_PROCESSOR_CLUSTER_FLAGS = \ > + { = \ > + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, = \ [SAMI] Is there a reason for setting the ID as invalid? In the next CPPC patch series 'Platform/Sgi: Add CPU container for xxx' the processor containers "ACPI0010" are described with valid UIDs. According to the ACPI 6.4 sepcification, Table 5.138: Processor Hierarchy Node Structure, Field description for 'ACPI Processor ID' states the following: "If the processor structure represents a group of associated processors, the structure might match a processor container in the name space. In that case this entry will match the value of the _UID method of the associated processor container. Where there is a match it must be represented." So, either this patch series or the next patch series 'Platform/Sgi: Add CPU container for xxx' will need to address this. [/SAMI] > + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ > + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, = \ > + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL = \ > + } > + > +// Processor structure flags for single-thread core > +#define PPTT_PROCESSOR_CORE_FLAGS = \ > + { = \ > + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, = \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ > + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF = \ > + } > + > +// Processor structure flags for multi-thread core > +#define PPTT_PROCESSOR_CORE_THREADED_FLAGS = \ > + { = \ > + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, = \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ > + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, = \ > + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL = \ > + } > + > +// Processor structure flags for CPU thread > +#define PPTT_PROCESSOR_THREAD_FLAGS = \ > + { = \ > + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, = \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD, = \ > + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF = \ > + } > + > +// PPTT cache structure flags as defined in ACPI 6.3 Specification > +#define PPTT_CACHE_STRUCTURE_FLAGS = \ > + { = \ > + EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID, = \ > + EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID, = \ > + EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID, = \ > + EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID, = \ > + EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID, = \ > + EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID, = \ > + EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID = \ > + } > + > +// PPTT cache attributes for data cache > +#define PPTT_DATA_CACHE_ATTR = \ > + { = \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ > + } > + > +// PPTT cache attributes for instruction cache > +#define PPTT_INST_CACHE_ATTR = \ > + { = \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, = \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ > + } > + > +// PPTT cache attributes for unified cache > +#define PPTT_UNIFIED_CACHE_ATTR = \ > + { = \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ > + } > + > // A macro to initialise the common header part of EFI ACPI tables as d= efined by > // EFI_ACPI_DESCRIPTION_HEADER structure. > #define ARM_ACPI_HEADER(Signature, Type, Revision) { \ > @@ -246,4 +371,39 @@ > TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheL= ineSize \ > } > > +// EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR > +#define EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag, Parent,= \ > + ACPIProcessorID, NumberOfPrivateResource) = \ > + { = \ > + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type 0 */ = \ > + Length, /* Length */ = \ > + { = \ > + EFI_ACPI_RESERVED_BYTE, = \ > + EFI_ACPI_RESERVED_BYTE, = \ > + }, = \ > + Flag, /* Processor flags= */ \ > + Parent, /* Ref to parent n= ode */ \ > + ACPIProcessorID, /* UID, as per MAD= T */ \ > + NumberOfPrivateResource /* Resource count = */ \ > + } > + > +// EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE > +#define EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT(Flag, NextLevelCache, Siz= e, \ > + NoOfSets, Associativity, Attributes, LineSize) = \ > + { = \ > + EFI_ACPI_6_3_PPTT_TYPE_CACHE, /* Type 1 */ = \ > + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), /* Length */ = \ > + { = \ > + EFI_ACPI_RESERVED_BYTE, = \ > + EFI_ACPI_RESERVED_BYTE, = \ > + }, = \ > + Flag, /* Cache flags */ = \ > + NextLevelCache, /* Ref to next lev= el */ \ > + Size, /* Size in bytes *= / \ > + NoOfSets, /* Num of sets */ = \ > + Associativity, /* Num of ways */ = \ > + Attributes, /* Cache attribute= s */ \ > + LineSize /* Line size in by= tes */ \ > + } > + > #endif /* __SGI_ACPI_HEADER__ */ IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. 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