From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::241; helo=mail-it0-x241.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x241.google.com (mail-it0-x241.google.com [IPv6:2607:f8b0:4001:c0b::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E616D202E53F4 for ; Fri, 29 Jun 2018 00:27:04 -0700 (PDT) Received: by mail-it0-x241.google.com with SMTP id 76-v6so1546083itx.4 for ; Fri, 29 Jun 2018 00:27:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-transfer-encoding; bh=qR9WoIRN4FZsRz8ymdYTbvOFTiCkzmQFwvxe8Cc2fho=; b=GThlaWfp7HxUHv0MEXltu01JwvJ0JCb06ViA0SKsTHzN0Myk0pnlNlQU9/rXJ0rQWU hH6W1U0uRKvjoI/S8dvIP6qlA4XgY27ng9GshdGT3/jIlgO9qJKu2xIuAZayRpBwQAjx f2lQV9iNVdsjtMIdHhv9+SRqj4stx/nodg5nY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-transfer-encoding; bh=qR9WoIRN4FZsRz8ymdYTbvOFTiCkzmQFwvxe8Cc2fho=; b=LR1dBoJ+eDzTDRhn63f43HoBW2EFarOHBlDC1M/LdKgxors5/LWgFF77WW2/cFWYfo MLZ3jAACQ0Mza84gF0ULPoLCk+hVFPM1KgReal+KQTbaGiUjCHSSA+2mdu+UbsBYWdn0 PhIo1nE6ciN3XVCDikuajWXIBdeM+B/Mv0ShbDKt94r+yD1C17Met6L+f038jbzy/I5T aEt39M5F+79YMnKD5y1hdWr3frpGn26zrRGmDNwkfCqW9v66OQ4VQD8uPF81vYOOtQCP oLcnAWc52+L0nC81is9zU89JjsaS68evrNZRdk9S7O1MNw4Utl6JLntOhvjW0ZnBn7RU vjDQ== X-Gm-Message-State: APt69E3GAZUZ4Z13qiR95eJoVepEstDxBzN5zEIGeAcW3L7jYQkvNQ93 rGoaYWIYOKaOoMwnu4cK34n+3Q== X-Google-Smtp-Source: AAOMgpcDwABiOyj8IwW8xJjw9mBva39884YLth97SR981/knq3iCvzylxNFNn6v9xcwAVAUdIkZTRQ== X-Received: by 2002:a24:9c46:: with SMTP id b67-v6mr900892ite.78.1530257223720; Fri, 29 Jun 2018 00:27:03 -0700 (PDT) Received: from [10.139.3.66] ([64.64.108.39]) by smtp.gmail.com with ESMTPSA id y6-v6sm396979itc.38.2018.06.29.00.26.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 29 Jun 2018 00:27:03 -0700 (PDT) To: Ard Biesheuvel Cc: Leif Lindholm , linaro-uefi , "edk2-devel@lists.01.org" , Graeme Gregory , guoheyi@huawei.com, wanghuiqiang , huangming , Jason Zhang , huangdaode@hisilicon.com, John Garry , Heyi Guo References: <20180627070443.42886-1-ming.huang@linaro.org> <20180627070443.42886-5-ming.huang@linaro.org> From: Ming Message-ID: <31c190df-9659-a6d4-cf6f-6dd62daa734f@linaro.org> Date: Fri, 29 Jun 2018 15:26:42 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: Subject: Re: [PATCH edk2-platforms v1 4/6] Hisilicon/D05: Add PlatformMiscDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jun 2018 07:27:05 -0000 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit 在 2018/6/28 18:54, Ard Biesheuvel 写道: > On 28 June 2018 at 04:26, Ming wrote: >> >> >> 在 2018/6/27 15:33, Ard Biesheuvel 写道: >>> On 27 June 2018 at 09:04, Ming Huang wrote: >>>> Fix the issue of onboard Nic not work kerenl with AMD GPU and >>>> NVME SSD in board. The GPU don't support 64 MSI, so need to >>>> allocate INTx, but the default interrupt number 255 is invalid, >>>> so Change all the PCI Device interrupt number to 0. >>>> >>> >>> Could you please try to explain in more detail what the problem is you >>> are solving, and why you think it should be solved in the firmware? >>> What does '64 MSI' mean? And where does the default of 255 come from? >>> >>> >> >> With AMD GPU and NVMe in board, the onboard Nic(hns-nic) can not work in ubuntu os. >> The AMD GPU has two devices: >> PCI device amdgpu 000d:33:00.0, snd_hda_intel 000d:33:00.1 >> The MSI is 64bit address in D05, and snd_hda_intel don't support 64bit MSI address, > > Legacy PCIe endpoints are permitted to only implement support for > 32-bit addressing of the MSI doorbell register, which is why it is > generally a good idea to put that below 4 GB in the physical address > space. > > So how is this implemented on D05? How are the PCIe host bridge > inbound windows configured? Any chance you could fix this by remapping > inbound transactions so the MSI doorbell appears at a 32-bit > addressable offset? > Inbound windows is not configured on D05. Maybe There are some risks if we configure inbound windows considering D05 has been running stably for a long time. Thanks. > >> so snd_hda_intel use the 255 irq. The onboard Nic register 255 irq failed. >> The 255 is the default value of PCI_INTERRUPT_LINE reg (0x3C). >> There is not a proper solution in kernel.This patch is a workaround in firmware. >> >> error log in kernel: >> Mar 1 00:27:07 ubuntu kernel: [ 25.581265] snd_hda_intel 000d:33:00.1: Device has broken 64-bit MSI but arch tried to assign one above 4Gl >> >> Mar 1 00:36:39 ubuntu kernel: [ 600.751276] genirq: Flags mismatch irq 255. 00000001 (enahisic2i0-tx1) vs. 00000081 (snd_hda_intel:card0) >> >> Mar 1 00:36:39 ubuntu kernel: [ 600.761137] hns-nic HISI00C2:00 enahisic2i0: request irq(255) fail >> >> Thanks. >> >>> >>>> Contributed-under: TianoCore Contribution Agreement 1.1 >>>> Signed-off-by: Ming Huang >>>> Signed-off-by: Heyi Guo >>>> --- >>>> Platform/Hisilicon/D05/D05.dsc | 1 + >>>> Platform/Hisilicon/D05/D05.fdf | 1 + >>>> Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c | 99 ++++++++++++++++++++ >>>> Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf | 47 ++++++++++ >>>> 4 files changed, 148 insertions(+) >>>> >>>> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc >>>> index b6e1a9d98a..0e6d5912a0 100644 >>>> --- a/Platform/Hisilicon/D05/D05.dsc >>>> +++ b/Platform/Hisilicon/D05/D05.dsc >>>> @@ -629,6 +629,7 @@ >>>> >>>> >>>> Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf >>>> + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf >>>> >>>> # >>>> # Memory test >>>> diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf >>>> index 37d9cc0c18..32374e245e 100644 >>>> --- a/Platform/Hisilicon/D05/D05.fdf >>>> +++ b/Platform/Hisilicon/D05/D05.fdf >>>> @@ -358,6 +358,7 @@ READ_LOCK_STATUS = TRUE >>>> INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf >>>> INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf >>>> INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf >>>> + INF Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf >>>> >>>> INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf >>>> >>>> diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c >>>> new file mode 100644 >>>> index 0000000000..8519b7139d >>>> --- /dev/null >>>> +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c >>>> @@ -0,0 +1,99 @@ >>>> +/** @file >>>> +* >>>> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. >>>> +* Copyright (c) 2016, Linaro Limited. All rights reserved. >>>> +* >>>> +* This program and the accompanying materials >>>> +* are licensed and made available under the terms and conditions of the BSD License >>>> +* which accompanies this distribution. The full text of the license may be found at >>>> +* http://opensource.org/licenses/bsd-license.php >>>> +* >>>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >>>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. >>>> +* >>>> +**/ >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> +VOID >>>> +SetIntLine ( >>>> + ) >>>> +{ >>>> + EFI_STATUS Status; >>>> + UINTN HandleIndex; >>>> + EFI_HANDLE *HandleBuffer; >>>> + UINTN HandleCount; >>>> + EFI_PCI_IO_PROTOCOL *PciIo; >>>> + UINT8 INTLine; >>>> + UINTN Segment; >>>> + UINTN Bus; >>>> + UINTN Device; >>>> + UINTN Fun; >>>> + >>>> + Status = gBS->LocateHandleBuffer ( >>>> + ByProtocol, >>>> + &gEfiPciIoProtocolGuid, >>>> + NULL, >>>> + &HandleCount, >>>> + &HandleBuffer >>>> + ); >>>> + if (EFI_ERROR (Status)) { >>>> + DEBUG ((DEBUG_ERROR, " Locate gEfiPciIoProtocol Failed.\n")); >>>> + gBS->FreePool ((VOID *)HandleBuffer); >>>> + return; >>>> + } >>>> + >>>> + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { >>>> + Status = gBS->HandleProtocol ( >>>> + HandleBuffer[HandleIndex], >>>> + &gEfiPciIoProtocolGuid, >>>> + (VOID **)&PciIo >>>> + ); >>>> + if (EFI_ERROR (Status)) { >>>> + continue; >>>> + } >>>> + >>>> + INTLine = 0; >>>> + (VOID)PciIo->Pci.Write ( >>>> + PciIo, >>>> + EfiPciIoWidthUint8, >>>> + PCI_INT_LINE_OFFSET, >>>> + 1, >>>> + &INTLine); >>>> + (VOID)PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Fun); >>>> + DEBUG ((DEBUG_INFO, "Set BDF(%x-%x-%x) IntLine to 0\n", Bus, Device, Fun)); >>>> + } >>>> + >>>> + gBS->FreePool ((VOID *)HandleBuffer); >>>> + return; >>>> +} >>>> + >>>> +EFI_STATUS >>>> +EFIAPI >>>> +PlatformMiscDxeEntry ( >>>> + IN EFI_HANDLE ImageHandle, >>>> + IN EFI_SYSTEM_TABLE *SystemTable >>>> + ) >>>> +{ >>>> + EFI_STATUS Status; >>>> + EFI_EVENT Event; >>>> + >>>> + Status = gBS->CreateEventEx ( >>>> + EVT_NOTIFY_SIGNAL, >>>> + TPL_CALLBACK, >>>> + SetIntLine, >>>> + NULL, >>>> + &gEfiEventReadyToBootGuid, >>>> + &Event >>>> + ); >>>> + if (EFI_ERROR (Status)) { >>>> + DEBUG ((DEBUG_ERROR, "Create event for SetIntLine, %r!\n", Status)); >>>> + } >>>> + >>>> + return EFI_SUCCESS; >>>> +} >>>> + >>>> diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf >>>> new file mode 100644 >>>> index 0000000000..0b365e7a53 >>>> --- /dev/null >>>> +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf >>>> @@ -0,0 +1,47 @@ >>>> +#/** @file >>>> +# >>>> +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. >>>> +# Copyright (c) 2016, Linaro Limited. All rights reserved. >>>> +# >>>> +# This program and the accompanying materials >>>> +# are licensed and made available under the terms and conditions of the BSD License >>>> +# which accompanies this distribution. The full text of the license may be found at >>>> +# http://opensource.org/licenses/bsd-license.php >>>> +# >>>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >>>> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. >>>> +# >>>> +#**/ >>>> + >>>> +[Defines] >>>> + INF_VERSION = 0x0001001A >>>> + BASE_NAME = PlatformMiscDxe >>>> + FILE_GUID = a48f7a09-253f-468b-87c6-caf78baf47bb >>>> + MODULE_TYPE = DXE_DRIVER >>>> + VERSION_STRING = 1.0 >>>> + ENTRY_POINT = PlatformMiscDxeEntry >>>> + >>>> +[Sources.common] >>>> + PlatformMiscDxe.c >>>> + >>>> +[Packages] >>>> + MdeModulePkg/MdeModulePkg.dec >>>> + MdePkg/MdePkg.dec >>>> + Silicon/Hisilicon/HisiPkg.dec >>>> + >>>> +[Guids] >>>> + gEfiEventReadyToBootGuid >>>> + >>>> +[Protocols] >>>> + gEfiPciIoProtocolGuid >>>> + >>>> +[LibraryClasses] >>>> + BaseLib >>>> + DebugLib >>>> + UefiBootServicesTableLib >>>> + UefiDriverEntryPoint >>>> + >>>> +[FixedPcd] >>>> + >>>> +[Depex] >>>> + TRUE >>>> -- >>>> 2.17.0 >>>>