From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 552DD210EE4E7 for ; Tue, 21 Aug 2018 07:39:19 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 961974021CC2; Tue, 21 Aug 2018 14:39:18 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-121-71.rdu2.redhat.com [10.10.121.71]) by smtp.corp.redhat.com (Postfix) with ESMTP id AD4E094653; Tue, 21 Aug 2018 14:39:17 +0000 (UTC) To: Jian J Wang , edk2-devel@lists.01.org Cc: Ruiyu Ni , Eric Dong References: <20180821030515.10156-1-jian.j.wang@intel.com> <20180821030515.10156-3-jian.j.wang@intel.com> From: Laszlo Ersek Message-ID: <3214cd76-aa39-6ed0-a080-be7128eadf32@redhat.com> Date: Tue, 21 Aug 2018 16:39:16 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180821030515.10156-3-jian.j.wang@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Tue, 21 Aug 2018 14:39:18 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Tue, 21 Aug 2018 14:39:18 +0000 (UTC) for IP:'10.11.54.5' DOMAIN:'int-mx05.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: Re: [PATCH v2 2/4] UefiCpuPkg/CpuExceptionHandlerLib: Setup single step in #PF handler X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 Aug 2018 14:39:19 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 08/21/18 05:05, Jian J Wang wrote: >> v2 changes: >> n/a > > Once the #PF handler has set the page to be 'present', there should > be a way to reset it to 'not-present'. 'TF' bit in EFLAGS can be used > for this purpose. 'TF' bit will be set in interrupted function context > so that it can be triggered once the cpu control returns back to the > instruction causing #PF and re-execute it. > > This is an necessary step to implement non-stop mode for Heap Guard > and NULL Pointer Detection feature. > > Cc: Eric Dong > Cc: Laszlo Ersek > Cc: Ruiyu Ni > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Jian J Wang > --- > .../Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm | 7 +++++++ > .../Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm | 4 +--- > .../Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 4 ++++ > 3 files changed, 12 insertions(+), 3 deletions(-) > > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm > index 45d6474091..6fcf5fb23f 100644 > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm > @@ -383,6 +383,13 @@ ErrorCodeAndVectorOnStack: > pop dword [ebp - 4] > mov esp, ebp > pop ebp > + > +; Enable TF bit after page fault handler runs > + cmp dword [esp], 14 ; #PF? > + jne .5 > + bts dword [esp + 16], 8 ; EFLAGS > + > +.5: > add esp, 8 > cmp dword [esp - 16], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler > jz DoReturn > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm > index 62bcedea1a..7aac29c7e7 100644 > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm > @@ -355,10 +355,8 @@ o16 mov [ecx + IA32_TSS._SS], ax > movzx ebx, word [ecx + IA32_TSS._CS] > mov [eax - 0x8], ebx ; create CS in old stack > mov ebx, dword [ecx + IA32_TSS.EFLAGS] > - bts ebx, 8 > + bts ebx, 8 ; Set TF > mov [eax - 0x4], ebx ; create eflags in old stack > - mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old TSS > - mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer > sub eax, 0xc ; minus 12 byte > mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer > > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > index 7b97810d10..f842af2336 100644 > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > @@ -336,6 +336,10 @@ HasErrorCode: > pop r15 > > mov rsp, rbp > + cmp qword [rbp + 8], 14 ; #PF? > + jne .1 > + bts qword [rsp + 40], 8 ; RFLAGS.TF > +.1: > pop rbp > add rsp, 16 > cmp qword [rsp - 32], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler > I'll defer to Ray and Eric on this. Thanks Laszlo