From: "Alexander D" <aenv067@gmail.com>
To: "Arminder Singh" <arminders208@outlook.com>, devel@edk2.groups.io
Subject: Re: [edk2-devel] [Question] How do you set PCIe host bridge address space granularity for a PCI host bridge defined with PciHostBridgeLib?
Date: Wed, 24 Jul 2024 13:28:10 -0700 [thread overview]
Message-ID: <32224.1721852890188999603@groups.io> (raw)
In-Reply-To: <SJ0PR12MB6926A2164541379115C26D7A9FAA2@SJ0PR12MB6926.namprd12.prod.outlook.com>
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That's expected. All PCIe endpoints in your case have *non-prefetchable* 64-bit BARs. These can only reside below 4 GB, so EDK2 downgrades them to the 32-bit non-prefetchable aperture.
If you had a device with a *prefetchable* 64-bit BAR (e.g. GPU VRAM), it would enumerate as "PMem64" and then you'd see it being allocated to the 64-bit prefetchable aperture.
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next prev parent reply other threads:[~2024-07-24 20:42 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-24 15:29 [edk2-devel] [Question] How do you set PCIe host bridge address space granularity for a PCI host bridge defined with PciHostBridgeLib? Arminder Singh
2024-07-24 20:28 ` Alexander D [this message]
2024-07-24 21:14 ` Alexander D
2024-07-30 0:19 ` Arminder Singh
2024-07-30 2:35 ` Alexander D
2024-08-05 17:58 ` Arminder Singh
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