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Thu, 22 Feb 2024 13:49:42 -0800 From: "Dat Mach via groups.io" To: CC: Dat Mach Subject: [edk2-devel] [PATCH] MdeModulePkg/Xhci: Skip another size round up for TRB address translation Date: Thu, 22 Feb 2024 13:48:58 -0800 Message-ID: <3293642dead287a039922cdabda5dc706ad5ccc4.1708638360.git.dmach@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009A:EE_|SA0PR12MB4559:EE_ X-MS-Office365-Filtering-Correlation-Id: b09d2b90-3374-4df3-7985-08dc33f0367c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: Z9sks9DI3DyX70z0Xe6akB5AF9o1op8DrX73WhZjP0gvXQq1Z4JDJ8TkL6Hd3uD+71YAgMPWKwLN4mxXi2dAQwFQ1J+bolK5eUgH1/xJ69RT/O6xKi6iE0b026xeIJuNl9ViSRS8ZMOX1OS6xGLyM+qKjIbXkoIT2Jh+GlhumRrcU3WLk2rXCctRmiqoZ9oyIN1NFvWdF9Ad41wAGt41ZS2IeaLllwPiSH7PAV/Wi66yjBy1hBdFsSn95Bq/xbt6Hvhm/SSv5NkrfFZI627UxYPYF3WhtCCG4iWNo+6oJTfVVnYEbo1QepVOnehpx10SqK22eA0Lb4LHfHO8Gwk4AvkCEhW4kStfU5jpKedRmXsYC3DSBni4lZJKQPLrAHtkwS6gKvd3Op7jaV16P8X/kfzsv3sqBVcQ3kb52LkK//B5wGioX+gEzDUqM4+BzjdRvmNSmFQmGl081IrDWrQxEPStd77lsxQAY/1k4vrY5q/0z8K43VT6PlpVFFxrYXHWRu1s/+KACXFn780l43T4bLHCIKPkOAGBiBqXx7qrhDWP1ly98G1ZxjC5QFH3LSdgP28VVEJB6ZSr+vevikou+eAjKAFKp42GpttszNlsU2gHJsfR7sWSwntoABnuOXzD3xRtpo7432d9bEx0rlRb1F8kbzf6b5fbKgj6v4R5HhLxNumtXakOBzs96u/5yU6Pn2F1qIqYdMJHjo1g2yn6Lw== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Feb 2024 21:49:57.7656 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b09d2b90-3374-4df3-7985-08dc33f0367c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4559 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dmach@nvidia.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: eaJj5HMOq5vldVgrJTDjKDeIx7686176AA= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=V8o2EIY6; dmarc=pass (policy=none) header.from=groups.io; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D4560 Commit f36e1ec1f0a5fd3be84913e09181d7813444b620 had fixed the DXE_ASSERT caused by the TRB size round up from 16 to 64 for most cases. However, there is a remaining case that the TRB size is also rounded up during setting TR dequeue pointer that would trigger DXE_ASSERT. This patch sets the alignment flag to FALSE in XhcSetTrDequeuePointer to fix this issue as well. Signed-off-by: Dat Mach --- MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 2 +- MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pc= i/XhciDxe/XhciSched.c index 05528a478b..5d735008ba 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -3539,7 +3539,7 @@ XhcSetTrDequeuePointer ( // Send stop endpoint command to transit Endpoint from running to stop s= tate // ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->= Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->= Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), FALSE); CmdSetTRDeq.PtrLo =3D XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS; CmdSetTRDeq.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdSetTRDeq.CycleBit =3D 1; diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c b/MdeModulePkg/Bus/Pc= i/XhciPei/XhciSched.c index 53272f62dd..c956e45907 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c @@ -2526,7 +2526,7 @@ XhcPeiSetTrDequeuePointer ( // Send stop endpoint command to transit Endpoint from running to stop s= tate // ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->= Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->= Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), FALSE); CmdSetTRDeq.PtrLo =3D XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS; CmdSetTRDeq.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdSetTRDeq.CycleBit =3D 1; --=20 2.44.0.rc2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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