From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.88; helo=mga01.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2544E21959CB2 for ; Thu, 24 Jan 2019 18:08:03 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jan 2019 18:08:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,519,1539673200"; d="scan'208";a="117280621" Received: from shzintpr01.sh.intel.com (HELO [10.253.24.52]) ([10.239.4.80]) by fmsmga007.fm.intel.com with ESMTP; 24 Jan 2019 18:08:01 -0800 To: "Chasel, Chiu" , edk2-devel@lists.01.org References: <20190123093311.16708-1-chasel.chiu@intel.com> Cc: star.zeng@intel.com From: "Zeng, Star" Message-ID: <32b86090-9167-8bae-638c-6ff41c55629f@intel.com> Date: Fri, 25 Jan 2019 10:07:32 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20190123093311.16708-1-chasel.chiu@intel.com> Subject: Re: [PATCH] IntelFsp2Pkg: FSP can utilize bootloader stack X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Jan 2019 02:08:04 -0000 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit On 2019/1/23 17:33, Chasel, Chiu wrote: > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1485 > > Current FSP utilizes pre-allocated temporary memory from > boot loader for both heap and stack. To reduce overall > temporary memory usage FSP may share the same stack with > boot loader and only needs a smaller memory for heap, > no separate memory required for stack. > Setting PcdFspHeapSizePercentage to 0 to enable FSP sharing > stack with boot loader, in this case boot loader stack > has to be large enough for FSP to use. Default is 50 > (half memory heap and half memory stack) for backward > compatible with original model. > > Test: Verified on internal platform and booting successfully > with both modes. > > Cc: Nate DeSimone > Cc: Star Zeng > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Chasel Chiu Minor comments below. With them addressed, Reviewed-by: Star Zeng . > --- > IntelFsp2Pkg/FspSecCore/SecMain.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------ > IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 3 ++- > IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 52 ++++++++++++++++++++++++++++++++++++++++++++++------ > IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 28 ++++++++++++++++++++++++++++ > IntelFsp2Pkg/IntelFsp2Pkg.dec | 4 ++++ > 5 files changed, 154 insertions(+), 19 deletions(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c b/IntelFsp2Pkg/FspSecCore/SecMain.c > index 70460a3c8b..b0b5dda711 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecMain.c > +++ b/IntelFsp2Pkg/FspSecCore/SecMain.c > @@ -1,6 +1,6 @@ > /** @file > > - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
> + Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the BSD License > which accompanies this distribution. The full text of the license may be found at > @@ -38,6 +38,19 @@ UINT64 mIdtEntryTemplate = 0xffff8e000008ffe4ULL; > > /** > > + Return value of esp > + > + @return value of esp > + > +**/ > +UINT32 > +EFIAPI > +AsmReadEsp ( > + VOID > + ); > + > +/** > + > Entry point to the C language phase of SEC. After the SEC assembly > code has initialized some temporary memory and set up the stack, > the control is transferred to this function. > @@ -83,7 +96,26 @@ SecStartup ( > // > InitializeFloatingPointUnits (); > > + // > + // Scenario 1 memory map when running on bootloader stack > + // > + // |-------------------|----> > + // |Idt Table | > + // |-------------------| > + // |PeiService Pointer | > + // |-------------------| > + // | | > + // | | > + // | Heap | > + // | | > + // | | > + // |-------------------|----> TempRamBase > + // |Bootloader stack | > + // |-------------------| The Bootloader stack range and TempRam range should be separated and should be not adjacent. How about drawing them separated here to remove the confusion? Another, maybe we can propose AsmReadEsp to BaseLib for long term. :) Thanks, Star > > + // > + // Scenario 2 memory map when running FSP on a separate stack > + // > // |-------------------|----> > // |Idt Table | > // |-------------------| > @@ -135,11 +167,19 @@ SecStartup ( > SecCoreData.BootFirmwareVolumeSize = (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *)BootFirmwareVolume)->FvLength; > > SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase; > - SecCoreData.TemporaryRamSize = SizeOfRam; > - SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase; > - SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100; > - SecCoreData.StackBase = (VOID*)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize); > - SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize; > + if (PcdGet8 (PcdFspHeapSizePercentage) == 0) { > + SecCoreData.TemporaryRamSize = SizeOfRam; // stack size that is going to be copied to the permanent memory > + SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase; > + SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize; > + SecCoreData.StackBase = (VOID *)GetFspEntryStack(); // Share the same boot loader stack > + SecCoreData.StackSize = 0; > + } else { > + SecCoreData.TemporaryRamSize = SizeOfRam; > + SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase; > + SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100; > + SecCoreData.StackBase = (VOID*)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize); > + SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize; > + } > > DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase)); > DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeSize - 0x%x\n", SecCoreData.BootFirmwareVolumeSize)); > @@ -194,15 +234,37 @@ SecTemporaryRamSupport ( > UINTN HeapSize; > UINTN StackSize; > > - HeapSize = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100 ; > - StackSize = CopySize - HeapSize; > + UINTN CurrentStack; > + UINTN FspStackBase; > + > + if (PcdGet8 (PcdFspHeapSizePercentage) == 0) { > > - OldHeap = (VOID*)(UINTN)TemporaryMemoryBase; > - NewHeap = (VOID*)((UINTN)PermanentMemoryBase + StackSize); > + CurrentStack = AsmReadEsp(); > + FspStackBase = (UINTN)GetFspEntryStack(); > > - OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize); > - NewStack = (VOID*)(UINTN)PermanentMemoryBase; > + StackSize = FspStackBase - CurrentStack; > + HeapSize = CopySize; > > + OldHeap = (VOID*)(UINTN)TemporaryMemoryBase; > + NewHeap = (VOID*)((UINTN)PermanentMemoryBase); > + > + OldStack = (VOID*)CurrentStack; > + // > + //The old stack is copied at the end of the stack region because stack grows down. > + // > + NewStack = (VOID*)((UINTN)PermanentMemoryBase - StackSize); > + > + } else { > + HeapSize = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100 ; > + StackSize = CopySize - HeapSize; > + > + OldHeap = (VOID*)(UINTN)TemporaryMemoryBase; > + NewHeap = (VOID*)((UINTN)PermanentMemoryBase + StackSize); > + > + OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize); > + NewStack = (VOID*)(UINTN)PermanentMemoryBase; > + > + } > // > // Migrate Heap > // > diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > index dafe6f5993..0024254e0e 100644 > --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > @@ -1,7 +1,7 @@ > ## @file > # Sec Core for FSP > # > -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
> # > # This program and the accompanying materials > # are licensed and made available under the terms and conditions of the BSD License > @@ -38,6 +38,7 @@ > Ia32/FspApiEntryM.nasm > Ia32/FspApiEntryCommon.nasm > Ia32/FspHelper.nasm > + Ia32/ReadEsp.nasm > > [Binaries.Ia32] > RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > index 9c9a84db0a..916ad4ff0d 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > @@ -1,7 +1,7 @@ > ;; @file > ; Provide FSP API entry points. > ; > -; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
> +; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
> ; This program and the accompanying materials > ; are licensed and made available under the terms and conditions of the BSD License > ; which accompanies this distribution. The full text of the license may be found at > @@ -19,6 +19,7 @@ > extern ASM_PFX(PcdGet32(PcdTemporaryRamBase)) > extern ASM_PFX(PcdGet32(PcdTemporaryRamSize)) > extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize)) > +extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage)) > > struc FSPM_UPD_COMMON > ; FSP_UPD_HEADER { > @@ -128,15 +129,55 @@ ASM_PFX(FspApiCommonContinue): > add edx, [eax + FSP_HEADER_CFGREG_OFFSET] > pop eax > > - FspStackSetup: > +FspStackSetup: > + ; > + ; StackBase = temp memory base, StackSize = temp memory size > + ; > mov edi, [edx + FSPM_UPD_COMMON.StackBase] > mov ecx, [edx + FSPM_UPD_COMMON.StackSize] > + > + ; > + ; Keep using bootloader stack if heap size % is 0 > + ; > + mov bl, BYTE [ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))] > + cmp bl, 0 > + jz SkipStackSwitch > + > + ; > + ; Set up a dedicated temp ram stack for FSP if FSP heap size % doesn't equal 0 > + ; > add edi, ecx > ; > - ; Setup new FSP stack > + ; Switch to new FSP stack > ; > - xchg edi, esp ; Exchange edi and esp, edi will be assigned to the current esp pointer and esp will be Stack base + Stack size > - mov ebx, esp ; Put Stack base + Stack size in ebx > + xchg edi, esp ; Exchange edi and esp, edi will be assigned to the current esp pointer and esp will be Stack base + Stack size > + > +SkipStackSwitch: > + ; > + ; If heap size % is 0: > + ; EDI is FSPM_UPD_COMMON.StackBase and will hold ESP later (boot loader stack pointer) > + ; ECX is FSPM_UPD_COMMON.StackSize > + ; ESP is boot loader stack pointer (no stack switch) > + ; BL is 0 to indicate no stack switch (EBX will hold FSPM_UPD_COMMON.StackBase later) > + ; > + ; If heap size % is not 0 > + ; EDI is boot loader stack pointer > + ; ECX is FSPM_UPD_COMMON.StackSize > + ; ESP is new stack (FSPM_UPD_COMMON.StackBase + FSPM_UPD_COMMON.StackSize) > + ; BL is NOT 0 to indicate stack has switched > + ; > + cmp bl, 0 > + jnz StackHasBeenSwitched > + > + mov ebx, edi ; Put FSPM_UPD_COMMON.StackBase to ebx as temp memory base > + mov edi, esp ; Put boot loader stack pointer to edi > + jmp StackSetupDone > + > +StackHasBeenSwitched: > + mov ebx, esp ; Put Stack base + Stack size in ebx > + sub ebx, ecx ; Stack base + Stack size - Stack size as temp memory base > + > +StackSetupDone: > > ; > ; Pass the API Idx to SecStartup > @@ -170,7 +211,6 @@ ASM_PFX(FspApiCommonContinue): > ; > ; Pass stack base and size into the PEI Core > ; > - sub ebx, ecx ; Stack base + Stack size - Stack size > push ebx > push ecx > > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm > new file mode 100644 > index 0000000000..ca29f0529c > --- /dev/null > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm > @@ -0,0 +1,28 @@ > +;; @file > +; Provide read ESP function > +; > +; Copyright (c) 2019, Intel Corporation. All rights reserved.
> +; This program and the accompanying materials > +; are licensed and made available under the terms and conditions of the BSD License > +; which accompanies this distribution. The full text of the license may be found at > +; http://opensource.org/licenses/bsd-license.php. > +; > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +;; > +;------------------------------------------------------------------------------ > + > + SECTION .text > + > +;------------------------------------------------------------------------------ > +; UINT32 > +; EFIAPI > +; AsmReadEsp ( > +; VOID > +; ); > +;------------------------------------------------------------------------------ > +global ASM_PFX(AsmReadEsp) > +ASM_PFX(AsmReadEsp): > + mov eax, esp > + ret > + > diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec > index 64a31b3505..d4c6d221a1 100644 > --- a/IntelFsp2Pkg/IntelFsp2Pkg.dec > +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec > @@ -86,8 +86,12 @@ > gIntelFsp2PkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase|0xFFF80000|UINT32|0x10000003 > gIntelFsp2PkgTokenSpaceGuid.PcdFspHeaderSpecVersion | 0x20| UINT8|0x00000002 > > + # > # x % of FSP temporary memory will be used for heap > # (100 - x) % of FSP temporary memory will be used for stack > + # 0 means FSP will share the stack with boot loader and FSP temporary memory is heap > + # Note: This mode assumes boot loader stack is large enough for FSP to use. > + # > gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage | 50| UINT8|0x10000004 > # > # Maximal Interrupt supported in IDT table. >