From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id E92BCAC04CF for ; Tue, 7 Nov 2023 02:02:27 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=RHPkC2kutE1PQvWbb4TSnG24EnOFOvXwJfIsVpfMogw=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1699322546; v=1; b=eTnYC6ssGEIxfJkU0wfTjafxNyYIl7u5yFAPM9Dd4TqxoixIzRsLa1yX6mluIXJYA3i8Xp2n xM4kaKMKh+nM0f9Mph5syIB6mjhUIIfSSff3nsgaZEXqhOR8r8C//es/S7Z9QiBn/wusEIXpuSk FPaciMVpRokoDtepFzUOqHC8= X-Received: by 127.0.0.2 with SMTP id jgJRYY7687511xc7kzKjLHA1; Mon, 06 Nov 2023 18:02:26 -0800 X-Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) by mx.groups.io with SMTP id smtpd.web10.1627.1699322546141458876 for ; Mon, 06 Nov 2023 18:02:26 -0800 X-Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-1cc9b626a96so26807255ad.2 for ; Mon, 06 Nov 2023 18:02:26 -0800 (PST) X-Gm-Message-State: ZNzhZmxBzNa4QJxYYgwJzYgQx7686176AA= X-Google-Smtp-Source: AGHT+IE/ZUnaFdSxnr/j+1hCXkjRAhdPXGMYV0RiTCy+zeBmPhXIchLx3r/pejd+p2fZ9jojmmIgNg== X-Received: by 2002:a17:902:d28b:b0:1c9:ea71:8032 with SMTP id t11-20020a170902d28b00b001c9ea718032mr22363016plc.31.1699322545249; Mon, 06 Nov 2023 18:02:25 -0800 (PST) X-Received: from JOE-LENO.redmond.corp.microsoft.com ([131.107.159.145]) by smtp.gmail.com with ESMTPSA id m15-20020a170902db0f00b001c7443d0890sm5093947plx.102.2023.11.06.18.02.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 18:02:24 -0800 (PST) From: "Joe L" To: devel@edk2.groups.io Cc: joelopez333 Subject: [edk2-devel] [PATCH v2] MdeModulePkg/PciHostBridgeDxe: Add readback after final Cfg-Write Date: Mon, 6 Nov 2023 18:02:21 -0800 Message-Id: <34167f0f873c01654aee0e9c8629221dad241529.1699322498.git.jlotwo@gmail.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jlotwo@gmail.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=eTnYC6ss; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=gmail.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: joelopez333 REF:https://edk2.groups.io/g/devel/topic/102310377#110456 Problem Report: On AARCH64, there is no ordering guarantee between configuration space (ECAM) writes and memory space reads (MMIO). ARM AMBA CHI only guarantees ordering for reads and writes within a single address r= egion, however, on some systems MMIO and ECAM may be split into separate address regions. A problem may arise when an ECAM write is issued a completion before a = subsequent MMIO read is issued and receives a completion. For example, a typical PCI software flow is the following: 1. ECAM write to device command register to enable memory space 2. MMIO read from device memory space for which access was enabled in step 1. There is no guarantee that step 2. will not begin before the completion= of step 1. on systems where ECAM/MMIO are specified as separate address regions, e= ven if both spaces have the memory attributes device-nGnRnE. Fix: - Add a read after the final PCI Configuration space write in RootBridgeIoPciAccess. - When configuration space is strongly ordered, this ensures that program execution cannot continue until the completion is received for the previous Cfg-Write, which may have side-effects. - Risk of reading a "write-only" register and causing a CA which leaves= the device unresponsive. The expectation based on the PCI Base Spec v6.1 section= 7.4 is that all PCI Spec-defined registers will be readable, however, there may e= xist design-specific registers that fall into this category. Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Sami Mujawar Cc: Jian J Wang Cc: Liming Gao Cc: Hao A Wu Cc: Ray Ni Cc: Pedro Falcato Cc: Michael Brown Signed-off-by: Joe Lopez --- MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeM= odulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index 157a0ada80..c2dc2018d6 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -1238,6 +1238,14 @@ RootBridgeIoPciAccess ( }=0D }=0D =0D + //=0D + // Perform readback after write to confirm completion was received for t= he last write=0D + // before subsequent memory operations can be issued.=0D + //=0D + if (!Read) {=0D + PciSegmentRead8 (Address - InStride);=0D + }=0D +=0D return EFI_SUCCESS;=0D }=0D =0D --=20 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110782): https://edk2.groups.io/g/devel/message/110782 Mute This Topic: https://groups.io/mt/102435564/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-