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([2607:f2c0:e98c:e:da1:4180:8030:1a92]) by smtp.gmail.com with ESMTPSA id bp6-20020a05620a458600b006bbda80595asm6846218qkb.5.2022.08.29.13.37.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 13:37:03 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Ankit Sinha , Isaac Oram , Liming Gao , Eric Dong Subject: [edk2-devel][edk2-platforms][PATCH v1 4/5] MinPlatformPkg: Implement working S3 resume Date: Mon, 29 Aug 2022 16:36:19 -0400 Message-Id: <3473a10f0459bc0d23bd496753ee3179e1860c50.1661799519.git.benjamin.doron00@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Consume S3 resume memory allocation on resume flow. Also, include complementary FirmwarePerformanceDataTablePei module in MinPlatform FV for S3 resume performance measurement. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Ankit Sinha Cc: Isaac Oram Cc: Liming Gao Cc: Eric Dong Signed-off-by: Benjamin Doron --- .../FspWrapperHobProcessLib.c | 70 ++++++++++++++++++- .../PeiFspWrapperHobProcessLib.inf | 2 + .../Include/Dsc/CorePeiInclude.dsc | 4 ++ .../Include/Fdf/CorePostMemoryInclude.fdf | 4 ++ 4 files changed, 79 insertions(+), 1 deletion(-) diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapper= HobProcessLib/FspWrapperHobProcessLib.c b/Platform/Intel/MinPlatformPkg/Fsp= Wrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c index 7ee4d3a31c49..992ec5d41bd8 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProc= essLib/FspWrapperHobProcessLib.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProc= essLib/FspWrapperHobProcessLib.c @@ -16,14 +16,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D #include =0D +#include =0D #include =0D #include =0D #include =0D #include =0D #include =0D #include =0D +#include =0D =0D #include =0D +#include =0D =0D //=0D // Additional pages are used by DXE memory manager.=0D @@ -130,6 +133,55 @@ GetPeiMemSize ( return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE;=0D }=0D =0D +/**=0D + Get S3 PEI memory information.=0D +=0D + @note At this point, memory is ready, and PeiServices are available to u= se.=0D + Platform can get some data from SMRAM directly.=0D +=0D + @param[out] S3PeiMemSize PEI memory size to be installed in S3 phase.=0D + @param[out] S3PeiMemBase PEI memory base to be installed in S3 phase.=0D +=0D + @return If S3 PEI memory information is got successfully.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GetS3MemoryInfo (=0D + OUT UINT64 *S3PeiMemSize,=0D + OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;=0D + UINTN DataSize;=0D + ACPI_S3_MEMORY S3MemoryInfo;=0D +=0D + *S3PeiMemBase =3D 0;=0D + *S3PeiMemSize =3D 0;=0D +=0D + Status =3D PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NU= LL, (VOID **) &VariablePpi);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + DataSize =3D sizeof (S3MemoryInfo);=0D + Status =3D VariablePpi->GetVariable (=0D + VariablePpi,=0D + ACPI_S3_MEMORY_NV_NAME,=0D + &gEfiAcpiVariableGuid,=0D + NULL,=0D + &DataSize,=0D + &S3MemoryInfo=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + *S3PeiMemBase =3D S3MemoryInfo.S3PeiMemBase;=0D + *S3PeiMemSize =3D S3MemoryInfo.S3PeiMemSize;=0D + return EFI_SUCCESS;=0D +}=0D +=0D /**=0D Post FSP-M HOB process for Memory Resource Descriptor.=0D =0D @@ -280,7 +332,7 @@ PostFspmHobProcess ( 0x1000=0D );=0D =0D -=0D + if (BootMode !=3D BOOT_ON_S3_RESUME) {=0D //=0D // Capsule mode=0D //=0D @@ -337,7 +389,23 @@ PostFspmHobProcess ( if (Capsule !=3D NULL) {=0D Status =3D Capsule->CreateState ((EFI_PEI_SERVICES **)PeiServices, C= apsuleBuffer, CapsuleBufferLength);=0D }=0D + } else {=0D + // TODO: Must BuildResourceDescriptorHob()?=0D + Status =3D GetS3MemoryInfo (&PeiMemSize, &PeiMemBase);=0D + ASSERT_EFI_ERROR (Status);=0D =0D + DEBUG ((DEBUG_INFO, "S3 resume PeiMemBase : 0x%08x\n", PeiMemBa= se));=0D + DEBUG ((DEBUG_INFO, "S3 resume PeiMemSize : 0x%08x\n", PeiMemSi= ze));=0D +=0D + //=0D + // Install efi memory=0D + //=0D + Status =3D PeiServicesInstallPeiMemory (=0D + PeiMemBase,=0D + PeiMemSize=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D + }=0D =0D //=0D // Create a memory allocation HOB at fixed location for MP Services PPI = AP wait loop.=0D diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapper= HobProcessLib/PeiFspWrapperHobProcessLib.inf b/Platform/Intel/MinPlatformPk= g/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.= inf index b846e7af1d2d..e2aac36bf018 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProc= essLib/PeiFspWrapperHobProcessLib.inf +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProc= essLib/PeiFspWrapperHobProcessLib.inf @@ -75,7 +75,9 @@ gZeroGuid=0D gEfiGraphicsInfoHobGuid=0D gEfiGraphicsDeviceInfoHobGuid=0D + gEfiAcpiVariableGuid=0D =0D [Ppis]=0D gEfiPeiCapsulePpiGuid ## CONSUMES=0D + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES=0D gEdkiiSiliconInitializedPpiGuid ## PRODUCES=0D diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc b= /Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc index 08e50cac075f..0eb0cc8306ee 100644 --- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc +++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc @@ -41,3 +41,7 @@ NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256= .inf=0D }=0D !endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE && gS3Fe= aturePkgTokenSpaceGuid.PcdS3FeatureEnable =3D=3D TRUE=0D + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerf= ormancePei.inf=0D +!endif=0D diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclud= e.fdf b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf index 3c2716d6728a..d8fb6683f7d4 100644 --- a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf +++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf @@ -6,3 +6,7 @@ # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D ##=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE && gS3Fe= aturePkgTokenSpaceGuid.PcdS3FeatureEnable =3D=3D TRUE=0D + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/Firmwar= ePerformancePei.inf=0D +!endif=0D --=20 2.37.2