* [edk2-devel] [PATCH edk2-platforms v3 0/5] SbsaQemu: Align the PPTT tables with QEMU
@ 2024-07-09 10:47 Marcin Juszkiewicz
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 1/5] SbsaQemu: get the information of CPU topology via SMC calls Marcin Juszkiewicz
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Marcin Juszkiewicz @ 2024-07-09 10:47 UTC (permalink / raw)
To: devel
Cc: Xiong Yining, Marcin Juszkiewicz, Leif Lindholm, Ard Biesheuvel,
Graeme Gregory, Chen Baozi
We want to make sure that CPU topology information given to QEMU would
be provided to the operating system. So we use SMC call to ask TF-A for
amount of sockets, clusters, cores and threads set in QEMU config.
The TF-A part is already merged:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/27189
Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
To: devel@edk2.groups.io
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Graeme Gregory <graeme@xora.org.uk>
Cc: Chen Baozi <chenbaozi@phytium.com.cn>
Cc: Xiong Yining <xiongyining1480@phytium.com.cn>
Changes in v3:
- split ACPI 6.5 changes into separate patch
- moved adding cores/threads to separate function
- fixed cache offsets
- Link to v2: https://openfw.io/edk2-devel/20240702-acpi65-v2-0-3cb18a892221@linaro.org/T/#t
Changes in v2 (Marcin Juszkiewicz):
- use ACPI 6.5 structures (instead of 6.3)
- add patch to move cache data to cores (instead of clusters)
- this is for future MPAM support
- reformatted sources using uncrustify
- changed debug output to allow singular values (s/are/:/)
---
Marcin Juszkiewicz (4):
SbsaQemu: get the information of CPU topology via SMC calls
SbsaQemu: update PPTT to ACPI 6.5
SbsaQemu: provide cache info per core in PPTT
SbsaQemu: introduce helper in PPTT generation
Xiong Yining (1):
SbsaQemu: align the PPTT tables with QEMU
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 11 +
.../Include/IndustryStandard/SbsaQemuAcpi.h | 78 +++----
.../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 1 +
.../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h | 26 +++
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 228 ++++++++++++++++----
.../SbsaQemuHardwareInfoLib.c | 36 ++++
6 files changed, 286 insertions(+), 94 deletions(-)
---
base-commit: ad553efc01125cad4ebdbe694b82cf6a59ce6a03
change-id: 20240702-acpi65-1bfdb20bde1a
Best regards,
--
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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* [edk2-devel] [PATCH edk2-platforms v3 1/5] SbsaQemu: get the information of CPU topology via SMC calls
2024-07-09 10:47 [edk2-devel] [PATCH edk2-platforms v3 0/5] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
@ 2024-07-09 10:47 ` Marcin Juszkiewicz
2024-07-09 12:40 ` Leif Lindholm
[not found] ` <17E08BE30DD079C5.26166@groups.io>
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 2/5] SbsaQemu: align the PPTT tables with QEMU Marcin Juszkiewicz
` (3 subsequent siblings)
4 siblings, 2 replies; 16+ messages in thread
From: Marcin Juszkiewicz @ 2024-07-09 10:47 UTC (permalink / raw)
To: devel
Cc: Xiong Yining, Marcin Juszkiewicz, Leif Lindholm, Ard Biesheuvel,
Graeme Gregory, Chen Baozi
Provide functions to check for CPU topology information:
- the number of sockets on sbsa-ref platform.
- the number of clusters in one socket.
- the number of cores in one cluster.
- the number of threads in one core.
As SMC calls can return up to 4 return values, the number of sockets,
clusters and cores are read from TF-A using platform specific SMC call.
Number of threads is caluculated using the cpu count and the number of
sockets, clusters and cores.
Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
.../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 1 +
.../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h | 26 ++++++++++++++
.../SbsaQemuHardwareInfoLib.c | 36 ++++++++++++++++++++
3 files changed, 63 insertions(+)
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
index af6b120561ad..b57573735ace 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
@@ -16,6 +16,7 @@
#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101)
#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200)
#define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201)
+#define SIP_SVC_GET_CPU_TOPOLOGY SMC_SIP_FUNCTION_ID(202)
#define SIP_SVC_GET_MEMORY_NODE_COUNT SMC_SIP_FUNCTION_ID(300)
#define SIP_SVC_GET_MEMORY_NODE SMC_SIP_FUNCTION_ID(301)
diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
index e5076274fa0a..cef6f6f58194 100644
--- a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
+++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
@@ -15,6 +15,19 @@ typedef struct {
UINT64 AddressSize;
} MemoryInfo;
+/**
+ Sockets: the number of sockets on sbsa-ref platform.
+ Clusters: the number of clusters in one socket.
+ Cores: the number of cores in one cluster.
+ Threads: the number of threads in one core.
+**/
+typedef struct {
+ UINT32 Sockets;
+ UINT32 Clusters;
+ UINT32 Cores;
+ UINT32 Threads;
+} CpuTopology;
+
/**
Get CPU count from information passed by Qemu.
@@ -83,4 +96,17 @@ GetNumaNodeCount (
VOID
);
+/**
+ Get cpu topology(sockets, clusters, cores, threads) from device tree passed by Qemu.
+
+ @param [out] CpuTopo A pointer to the cpu topology.
+
+
+ @retval the information of cpu topology.
+**/
+VOID
+GetCpuTopology (
+ OUT CpuTopology *CpuTopo
+ );
+
#endif /* HARDWARE_INFO_LIB */
diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
index 596a3453c70f..b17a2ae99b4e 100644
--- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
+++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
@@ -181,3 +181,39 @@ GetNumaNodeCount (
return NumberNumaNodes;
}
+
+/**
+ Get CPU topology.
+**/
+VOID
+GetCpuTopology (
+ OUT CpuTopology *CpuTopo
+ )
+{
+ UINTN SmcResult;
+ UINTN Arg0;
+ UINTN Arg1;
+ UINTN Arg2;
+ UINT32 NumCores = GetCpuCount ();
+
+ SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_TOPOLOGY, &Arg0, &Arg1, &Arg2);
+ if (SmcResult != SMC_SIP_CALL_SUCCESS) {
+ DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_TOPOLOGY call failed. We have no cpu topology information.\n", __FUNCTION__));
+ ResetShutdown ();
+ } else {
+ CpuTopo->Sockets = Arg0;
+ CpuTopo->Clusters = Arg1;
+ CpuTopo->Cores = Arg2;
+ CpuTopo->Threads = NumCores / (CpuTopo->Sockets * CpuTopo->Clusters * CpuTopo->Cores);
+ }
+
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: CPU Topology: sockets are %d, clusters are %d, cores are %d, threads are %d\n",
+ __FUNCTION__,
+ CpuTopo->Sockets,
+ CpuTopo->Clusters,
+ CpuTopo->Cores,
+ CpuTopo->Threads
+ ));
+}
--
2.45.2
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* [edk2-devel] [PATCH edk2-platforms v3 2/5] SbsaQemu: align the PPTT tables with QEMU
2024-07-09 10:47 [edk2-devel] [PATCH edk2-platforms v3 0/5] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 1/5] SbsaQemu: get the information of CPU topology via SMC calls Marcin Juszkiewicz
@ 2024-07-09 10:47 ` Marcin Juszkiewicz
2024-07-09 12:43 ` Leif Lindholm
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 3/5] SbsaQemu: update PPTT to ACPI 6.5 Marcin Juszkiewicz
` (2 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Marcin Juszkiewicz @ 2024-07-09 10:47 UTC (permalink / raw)
To: devel
Cc: Xiong Yining, Marcin Juszkiewicz, Leif Lindholm, Ard Biesheuvel,
Graeme Gregory, Chen Baozi
From: Xiong Yining <xiongyining1480@phytium.com.cn>
To align the CPU topology information recognized by the operating system
with the CPU topology information configured by QEMU, we need to make
use of the CPU topology information to create complex PPTT tables
setups.
We can get the CPU topology information via SMC.
Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 11 ++
.../Include/IndustryStandard/SbsaQemuAcpi.h | 32 ----
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 187 +++++++++++++++-----
3 files changed, 158 insertions(+), 72 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index e5f0748bb16e..085c681ba55f 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -88,4 +88,15 @@ typedef struct {
ClockDomain /* Clock Domain */ \
}
+#define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, ACPIProcessorID, NumberOfPrivateResources) \
+ { \
+ EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type */ \
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources * sizeof (UINT32), /* Length */ \
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, /* Reserved */ \
+ Flags, /* Flags */ \
+ Parent, /* Parent */ \
+ ACPIProcessorID, /* ACPI Processor ID */ \
+ NumberOfPrivateResources /* Number of private resources */ \
+ }
+
#endif
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index ae151210c2c6..2f87591e737a 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -166,36 +166,4 @@ typedef struct {
64 /* LineSize */ \
}
-#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT { \
- EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR), \
- { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
- { \
- EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ \
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
- EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */ \
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
- }, \
- 0, /* Parent */ \
- 0, /* AcpiProcessorId */ \
- 0, /* NumberOfPrivateResources */ \
- }
-
-#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT { \
- EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
- (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32))), \
- { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
- { \
- EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */ \
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorValid */ \
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
- EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ \
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
- }, \
- 0, /* Parent */ \
- 0, /* AcpiProcessorId */ \
- 2, /* NumberOfPrivateResources */ \
- }
-
#endif
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index e0eef54ff907..465a69d7328c 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -505,14 +505,51 @@ AddPpttTable (
EFI_PHYSICAL_ADDRESS PageAddress;
UINT8 *New;
UINT32 CpuId;
- UINT32 NumCores = GetCpuCount ();
+ CpuTopology CpuTopo;
+
+ GetCpuTopology (&CpuTopo);
EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT;
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PPTT_CORE_STRUCT;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS SocketFlags = {
+ EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ };
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS ClusterFlags = {
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ };
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ };
+
+ if (CpuTopo.Threads > 1) {
+ // The Thread structure is the leaf structure, adjust the value of CoreFlags.
+ CoreFlags.AcpiProcessorIdValid = EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID;
+ CoreFlags.NodeIsALeaf = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
+ }
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ };
EFI_ACPI_DESCRIPTION_HEADER Header =
SBSAQEMU_ACPI_HEADER (
@@ -522,10 +559,16 @@ AddPpttTable (
);
TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
- (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) +
- (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) +
- (sizeof (UINT32) * 2 * NumCores);
+ CpuTopo.Sockets * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
+ CpuTopo.Clusters * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3 +
+ CpuTopo.Cores * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
+ sizeof (UINT32) * 2)));
+
+ if (CpuTopo.Threads > 1) {
+ TableSize += CpuTopo.Sockets * CpuTopo.Clusters * CpuTopo.Cores * CpuTopo.Threads *
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ }
Status = gBS->AllocatePages (
AllocateAnyPages,
@@ -546,39 +589,103 @@ AddPpttTable (
((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length = TableSize;
New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
- // Add the Cluster PPTT structure
- CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
-
- // Add L1 D Cache structure
- CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2_CACHE_INDEX;
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
-
- // Add L1 I Cache structure
- CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2_CACHE_INDEX;
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
-
- // Add L2 Cache structure
- CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 0; /* L2 is LLC */
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
-
- for (CpuId = 0; CpuId < NumCores; CpuId++) {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr;
- UINT32 *PrivateResourcePtr;
-
- CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
- CorePtr = (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *)New;
- CorePtr->Parent = CLUSTER_INDEX;
- CorePtr->AcpiProcessorId = CpuId;
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
-
- PrivateResourcePtr = (UINT32 *)New;
- PrivateResourcePtr[0] = L1_D_CACHE_INDEX;
- PrivateResourcePtr[1] = L1_I_CACHE_INDEX;
- New += (2 * sizeof (UINT32));
+ UINT32 SocketNum, ClusterNum, CoreNum, ThreadNum;
+ UINT32 SocketIndex, ClusterIndex, CoreIndex, L1DCacheIndex, L1ICacheIndex, L2CacheIndex;
+
+ CpuId = 0;
+ SocketIndex = sizeof (EFI_ACPI_DESCRIPTION_HEADER);
+ for (SocketNum = 0; SocketNum < CpuTopo.Sockets; SocketNum++) {
+ // Add the Socket PPTT structure
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Socket = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ SocketFlags,
+ 0,
+ 0,
+ 0
+ );
+ CopyMem (New, &Socket, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+
+ ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) {
+ L1DCacheIndex = ClusterIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ CoreIndex = L2CacheIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ // Add the Cluster PPTT structure
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ ClusterFlags,
+ SocketIndex,
+ 0,
+ 0
+ );
+ CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+
+ // Add L1 D Cache structure
+ CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ // Add L1 I Cache structure
+ CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ // Add L2 Cache structure
+ CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
+ UINT32 *PrivateResourcePtr;
+ UINT32 CoreCpuId;
+
+ if (CpuTopo.Threads == 1) {
+ CoreCpuId = CpuId;
+ } else {
+ CoreCpuId = 0;
+ }
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ CoreFlags,
+ ClusterIndex,
+ CoreCpuId,
+ 2
+ );
+ CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+
+ PrivateResourcePtr = (UINT32 *)New;
+ PrivateResourcePtr[0] = L1DCacheIndex;
+ PrivateResourcePtr[1] = L1ICacheIndex;
+ New += (2 * sizeof (UINT32));
+
+ if (CpuTopo.Threads == 1) {
+ CpuId++;
+ } else {
+ // Add the Thread PPTT structure
+ for (ThreadNum = 0; ThreadNum < CpuTopo.Threads; ThreadNum++) {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ ThreadFlags,
+ CoreIndex,
+ CpuId,
+ 0
+ );
+ CopyMem (New, &Thread, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ CpuId++;
+ }
+
+ CoreIndex += CpuTopo.Threads * sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ }
+
+ CoreIndex += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+ }
+
+ ClusterIndex = CoreIndex;
+ }
+
+ SocketIndex = ClusterIndex;
}
// Perform Checksum
--
2.45.2
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* [edk2-devel] [PATCH edk2-platforms v3 3/5] SbsaQemu: update PPTT to ACPI 6.5
2024-07-09 10:47 [edk2-devel] [PATCH edk2-platforms v3 0/5] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 1/5] SbsaQemu: get the information of CPU topology via SMC calls Marcin Juszkiewicz
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 2/5] SbsaQemu: align the PPTT tables with QEMU Marcin Juszkiewicz
@ 2024-07-09 10:47 ` Marcin Juszkiewicz
2024-07-09 12:44 ` Leif Lindholm
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 4/5] SbsaQemu: provide cache info per core in PPTT Marcin Juszkiewicz
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 5/5] SbsaQemu: introduce helper in PPTT generation Marcin Juszkiewicz
4 siblings, 1 reply; 16+ messages in thread
From: Marcin Juszkiewicz @ 2024-07-09 10:47 UTC (permalink / raw)
To: devel
Cc: Xiong Yining, Marcin Juszkiewicz, Leif Lindholm, Ard Biesheuvel,
Graeme Gregory, Chen Baozi
ACPI 6.5 is the newest version of specification so far. The only change
to make is handling of CacheId (has to be unique and higher than zero).
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 4 +-
.../Include/IndustryStandard/SbsaQemuAcpi.h | 46 ++++---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 127 ++++++++++----------
3 files changed, 94 insertions(+), 83 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index 085c681ba55f..5aaf02e3ca30 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -90,8 +90,8 @@ typedef struct {
#define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, ACPIProcessorID, NumberOfPrivateResources) \
{ \
- EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type */ \
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources * sizeof (UINT32), /* Length */ \
+ EFI_ACPI_6_5_PPTT_TYPE_PROCESSOR, /* Type */ \
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources * sizeof (UINT32), /* Length */ \
{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, /* Reserved */ \
Flags, /* Flags */ \
Parent, /* Parent */ \
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index 2f87591e737a..fa2e2b30bb7d 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -87,13 +87,13 @@ typedef struct {
#define SBSAQEMU_L2_CACHE_ASSC 8
#define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
-#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR))
-#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
-#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
+#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR))
+#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
+#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
#define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT { \
- EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
+ EFI_ACPI_6_5_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE), \
{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
{ \
1, /* SizePropertyValid */ \
@@ -103,22 +103,24 @@ typedef struct {
1, /* CacheTypeValid */ \
1, /* WritePolicyValid */ \
1, /* LineSizeValid */ \
+ 1, /* CacheIdValid */ \
}, \
0, /* NextLevelOfCache */ \
SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ \
SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ \
SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ \
{ \
- EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
- EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
- EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
}, \
- 64 /* LineSize */ \
+ 64, /* LineSize */ \
+ 0 /* CacheId */ \
}
#define SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT { \
- EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
+ EFI_ACPI_6_5_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE), \
{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
{ \
1, /* SizePropertyValid */ \
@@ -128,22 +130,24 @@ typedef struct {
1, /* CacheTypeValid */ \
1, /* WritePolicyValid */ \
1, /* LineSizeValid */ \
+ 1, /* CacheIdValid */ \
}, \
0, /* NextLevelOfCache */ \
SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ \
SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ \
SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ \
{ \
- EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, \
- EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
0, \
}, \
- 64 /* LineSize */ \
+ 64, /* LineSize */ \
+ 0 /* CacheId */ \
}
#define SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT { \
- EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
+ EFI_ACPI_6_5_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE), \
{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
{ \
1, /* SizePropertyValid */ \
@@ -153,17 +157,19 @@ typedef struct {
1, /* CacheTypeValid */ \
1, /* WritePolicyValid */ \
1, /* LineSizeValid */ \
+ 1, /* CacheIdValid */ \
}, \
0, /* NextLevelOfCache */ \
SBSAQEMU_L2_CACHE_SIZE, /* Size */ \
SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ \
SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ \
{ \
- EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
- EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
- EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
}, \
- 64 /* LineSize */ \
+ 64, /* LineSize */ \
+ 0 /* CacheId */ \
}
#endif
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 465a69d7328c..cf0102d11f1f 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -506,35 +506,36 @@ AddPpttTable (
UINT8 *New;
UINT32 CpuId;
CpuTopology CpuTopo;
+ UINT32 CacheId;
GetCpuTopology (&CpuTopo);
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS SocketFlags = {
- EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
- EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS SocketFlags = {
+ EFI_ACPI_6_5_PPTT_PACKAGE_PHYSICAL,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
};
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS ClusterFlags = {
- EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
- EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS ClusterFlags = {
+ EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
};
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
- EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
- EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
+ EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
};
if (CpuTopo.Threads > 1) {
@@ -543,31 +544,31 @@ AddPpttTable (
CoreFlags.NodeIsALeaf = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
}
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
- EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD,
- EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
+ EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD,
+ EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
};
EFI_ACPI_DESCRIPTION_HEADER Header =
SBSAQEMU_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
EFI_ACPI_DESCRIPTION_HEADER,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
);
TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
- CpuTopo.Sockets * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
- CpuTopo.Clusters * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3 +
- CpuTopo.Cores * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
+ CpuTopo.Sockets * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
+ CpuTopo.Clusters * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
+ CpuTopo.Cores * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
sizeof (UINT32) * 2)));
if (CpuTopo.Threads > 1) {
TableSize += CpuTopo.Sockets * CpuTopo.Clusters * CpuTopo.Cores * CpuTopo.Threads *
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
}
Status = gBS->AllocatePages (
@@ -593,48 +594,52 @@ AddPpttTable (
UINT32 SocketIndex, ClusterIndex, CoreIndex, L1DCacheIndex, L1ICacheIndex, L2CacheIndex;
CpuId = 0;
+ CacheId = 1; // 0 is not a valid Cache ID.
SocketIndex = sizeof (EFI_ACPI_DESCRIPTION_HEADER);
for (SocketNum = 0; SocketNum < CpuTopo.Sockets; SocketNum++) {
// Add the Socket PPTT structure
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Socket = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Socket = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
SocketFlags,
0,
0,
0
);
- CopyMem (New, &Socket, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ CopyMem (New, &Socket, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) {
- L1DCacheIndex = ClusterIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
- L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
- L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
- CoreIndex = L2CacheIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ L1DCacheIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+ L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+ L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+ CoreIndex = L2CacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
// Add the Cluster PPTT structure
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
ClusterFlags,
SocketIndex,
0,
0
);
- CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
// Add L1 D Cache structure
- CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ L1DCache.CacheId = CacheId++;
+ CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
// Add L1 I Cache structure
- CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ L1ICache.CacheId = CacheId++;
+ CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
// Add L2 Cache structure
- CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ L2Cache.CacheId = CacheId++;
+ CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
UINT32 *PrivateResourcePtr;
@@ -646,14 +651,14 @@ AddPpttTable (
CoreCpuId = 0;
}
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
CoreFlags,
ClusterIndex,
CoreCpuId,
2
);
- CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ CopyMem (New, &Core, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
PrivateResourcePtr = (UINT32 *)New;
PrivateResourcePtr[0] = L1DCacheIndex;
@@ -665,21 +670,21 @@ AddPpttTable (
} else {
// Add the Thread PPTT structure
for (ThreadNum = 0; ThreadNum < CpuTopo.Threads; ThreadNum++) {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
ThreadFlags,
CoreIndex,
CpuId,
0
);
- CopyMem (New, &Thread, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ CopyMem (New, &Thread, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
CpuId++;
}
- CoreIndex += CpuTopo.Threads * sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ CoreIndex += CpuTopo.Threads * sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
}
- CoreIndex += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+ CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
}
ClusterIndex = CoreIndex;
--
2.45.2
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* [edk2-devel] [PATCH edk2-platforms v3 4/5] SbsaQemu: provide cache info per core in PPTT
2024-07-09 10:47 [edk2-devel] [PATCH edk2-platforms v3 0/5] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
` (2 preceding siblings ...)
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 3/5] SbsaQemu: update PPTT to ACPI 6.5 Marcin Juszkiewicz
@ 2024-07-09 10:47 ` Marcin Juszkiewicz
2024-07-09 13:01 ` Leif Lindholm
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 5/5] SbsaQemu: introduce helper in PPTT generation Marcin Juszkiewicz
4 siblings, 1 reply; 16+ messages in thread
From: Marcin Juszkiewicz @ 2024-07-09 10:47 UTC (permalink / raw)
To: devel
Cc: Xiong Yining, Marcin Juszkiewicz, Leif Lindholm, Ard Biesheuvel,
Graeme Gregory, Chen Baozi
During Linaro Connect MAD24 I was asked to move cache information from
being 'per cluster' to be 'per core'. This is a move for implementing
MPAM support.
So topology moves from:
Socket -> Clusters -> Cores + Caches -> Threads (if exist)
to:
Socket -> Clusters -> Cores -> Caches + Threads (if exist)
Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
implement them at all so we can tell whatever.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 47 +++++++++++---------
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index cf0102d11f1f..a7a9664abdcb 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -562,8 +562,8 @@ AddPpttTable (
TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
CpuTopo.Sockets * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
CpuTopo.Clusters * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
- sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
CpuTopo.Cores * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
sizeof (UINT32) * 2)));
if (CpuTopo.Threads > 1) {
@@ -609,10 +609,7 @@ AddPpttTable (
ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) {
- L1DCacheIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
- L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
- CoreIndex = L2CacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+ CoreIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
// Add the Cluster PPTT structure
EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
@@ -624,27 +621,15 @@ AddPpttTable (
CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- // Add L1 D Cache structure
- L1DCache.CacheId = CacheId++;
- CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
- // Add L1 I Cache structure
- L1ICache.CacheId = CacheId++;
- CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
- // Add L2 Cache structure
- L2Cache.CacheId = CacheId++;
- CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
UINT32 *PrivateResourcePtr;
UINT32 CoreCpuId;
+ // two UINT32s for PrivateResourcePtr data
+ L1DCacheIndex = CoreIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+ L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+ L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
if (CpuTopo.Threads == 1) {
CoreCpuId = CpuId;
} else {
@@ -665,6 +650,23 @@ AddPpttTable (
PrivateResourcePtr[1] = L1ICacheIndex;
New += (2 * sizeof (UINT32));
+ // Add L1 D Cache structure
+ L1DCache.CacheId = CacheId++;
+ CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+ // Add L1 I Cache structure
+ L1ICache.CacheId = CacheId++;
+ CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+ // Add L2 Cache structure
+ L2Cache.CacheId = CacheId++;
+ CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
if (CpuTopo.Threads == 1) {
CpuId++;
} else {
@@ -685,6 +687,7 @@ AddPpttTable (
}
CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+ CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
}
ClusterIndex = CoreIndex;
--
2.45.2
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* [edk2-devel] [PATCH edk2-platforms v3 5/5] SbsaQemu: introduce helper in PPTT generation
2024-07-09 10:47 [edk2-devel] [PATCH edk2-platforms v3 0/5] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
` (3 preceding siblings ...)
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 4/5] SbsaQemu: provide cache info per core in PPTT Marcin Juszkiewicz
@ 2024-07-09 10:47 ` Marcin Juszkiewicz
2024-07-09 13:00 ` Leif Lindholm
4 siblings, 1 reply; 16+ messages in thread
From: Marcin Juszkiewicz @ 2024-07-09 10:47 UTC (permalink / raw)
To: devel
Cc: Xiong Yining, Marcin Juszkiewicz, Leif Lindholm, Ard Biesheuvel,
Graeme Gregory, Chen Baozi
Function AddPpttTable() adding PPTT got too long. This change moves part
of it into helper function AddCoresToPpttTable() which takes care of
generating entries for Core and below (Cache, Thread).
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 237 +++++++++++---------
1 file changed, 133 insertions(+), 104 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index a7a9664abdcb..a4b2ee2fdcb0 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -29,6 +29,9 @@
static UINTN GicItsBase;
+static UINTN CpuId;
+static UINTN CacheId;
+
#pragma pack ()
/*
@@ -491,6 +494,126 @@ AddSsdtTable (
return Status;
}
+UINT32
+AddCoresToPpttTable (
+ UINT8 *New,
+ UINT32 ClusterIndex,
+ CpuTopology CpuTopo
+ )
+{
+ UINT32 L1DCacheIndex;
+ UINT32 L1ICacheIndex;
+ UINT32 L2CacheIndex;
+ UINT32 CoreIndex;
+ UINT32 Index;
+ UINT32 CoreCpuId;
+ UINT32 CoreNum;
+ UINT32 ThreadNum;
+ UINT32 *PrivateResourcePtr;
+
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
+ EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
+ };
+
+ if (CpuTopo.Threads > 1) {
+ // The Thread structure is the leaf structure, adjust the value of CoreFlags.
+ CoreFlags.AcpiProcessorIdValid = EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID;
+ CoreFlags.NodeIsALeaf = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
+ }
+
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
+ EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD,
+ EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
+ };
+
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
+
+ CoreIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+ Index = CoreIndex;
+
+ for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
+ if (CpuTopo.Threads == 1) {
+ CoreCpuId = CpuId;
+ } else {
+ CoreCpuId = 0;
+ }
+
+ // space for Core + PrivateResourcePtr
+ Index += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+ Index += sizeof (UINT32) * 2;
+
+ L1DCacheIndex = Index;
+ L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+ L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ CoreFlags,
+ ClusterIndex,
+ CoreCpuId,
+ 2
+ );
+
+ CopyMem (New, &Core, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+
+ PrivateResourcePtr = (UINT32 *)New;
+ PrivateResourcePtr[0] = L1DCacheIndex;
+ PrivateResourcePtr[1] = L1ICacheIndex;
+ New += (2 * sizeof (UINT32));
+
+ // Add L1 D Cache structure
+ L1DCache.CacheId = CacheId++;
+ CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+ // Add L1 I Cache structure
+ L1ICache.CacheId = CacheId++;
+ CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+ // Add L2 Cache structure
+ L2Cache.CacheId = CacheId++;
+ CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+ Index += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
+
+ if (CpuTopo.Threads == 1) {
+ CpuId++;
+ } else {
+ // Add the Thread PPTT structure
+ for (ThreadNum = 0; ThreadNum < CpuTopo.Threads; ThreadNum++) {
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ ThreadFlags,
+ CoreIndex,
+ CpuId,
+ 0
+ );
+ CopyMem (New, &Thread, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+ CpuId++;
+ }
+
+ Index += CpuTopo.Threads * sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+ }
+
+ CoreIndex = Index;
+ }
+
+ return CoreIndex - ClusterIndex - sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+}
+
/*
* A function that adds the PPTT ACPI table.
*/
@@ -502,18 +625,17 @@ AddPpttTable (
EFI_STATUS Status;
UINTN TableHandle;
UINT32 TableSize;
+ UINT32 CoresPartSize;
+ UINT32 SocketNum;
+ UINT32 ClusterNum;
+ UINT32 SocketIndex;
+ UINT32 ClusterIndex;
EFI_PHYSICAL_ADDRESS PageAddress;
UINT8 *New;
- UINT32 CpuId;
CpuTopology CpuTopo;
- UINT32 CacheId;
GetCpuTopology (&CpuTopo);
- EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
- EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
- EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
-
EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS SocketFlags = {
EFI_ACPI_6_5_PPTT_PACKAGE_PHYSICAL,
EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID,
@@ -530,28 +652,6 @@ AddPpttTable (
EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
};
- EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
- EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
- EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
- EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
- EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
- EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
- };
-
- if (CpuTopo.Threads > 1) {
- // The Thread structure is the leaf structure, adjust the value of CoreFlags.
- CoreFlags.AcpiProcessorIdValid = EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID;
- CoreFlags.NodeIsALeaf = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
- }
-
- EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
- EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
- EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
- EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD,
- EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
- EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
- };
-
EFI_ACPI_DESCRIPTION_HEADER Header =
SBSAQEMU_ACPI_HEADER (
EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
@@ -590,11 +690,9 @@ AddPpttTable (
((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length = TableSize;
New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
- UINT32 SocketNum, ClusterNum, CoreNum, ThreadNum;
- UINT32 SocketIndex, ClusterIndex, CoreIndex, L1DCacheIndex, L1ICacheIndex, L2CacheIndex;
+ CpuId = 0;
+ CacheId = 1; // 0 is not a valid Cache ID.
- CpuId = 0;
- CacheId = 1; // 0 is not a valid Cache ID.
SocketIndex = sizeof (EFI_ACPI_DESCRIPTION_HEADER);
for (SocketNum = 0; SocketNum < CpuTopo.Sockets; SocketNum++) {
// Add the Socket PPTT structure
@@ -609,8 +707,6 @@ AddPpttTable (
ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) {
- CoreIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
-
// Add the Cluster PPTT structure
EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
ClusterFlags,
@@ -621,76 +717,9 @@ AddPpttTable (
CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
- UINT32 *PrivateResourcePtr;
- UINT32 CoreCpuId;
-
- // two UINT32s for PrivateResourcePtr data
- L1DCacheIndex = CoreIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
- L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
- L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
- if (CpuTopo.Threads == 1) {
- CoreCpuId = CpuId;
- } else {
- CoreCpuId = 0;
- }
-
- EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
- CoreFlags,
- ClusterIndex,
- CoreCpuId,
- 2
- );
- CopyMem (New, &Core, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
-
- PrivateResourcePtr = (UINT32 *)New;
- PrivateResourcePtr[0] = L1DCacheIndex;
- PrivateResourcePtr[1] = L1ICacheIndex;
- New += (2 * sizeof (UINT32));
-
- // Add L1 D Cache structure
- L1DCache.CacheId = CacheId++;
- CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
- // Add L1 I Cache structure
- L1ICache.CacheId = CacheId++;
- CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
- // Add L2 Cache structure
- L2Cache.CacheId = CacheId++;
- CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
- if (CpuTopo.Threads == 1) {
- CpuId++;
- } else {
- // Add the Thread PPTT structure
- for (ThreadNum = 0; ThreadNum < CpuTopo.Threads; ThreadNum++) {
- EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
- ThreadFlags,
- CoreIndex,
- CpuId,
- 0
- );
- CopyMem (New, &Thread, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- CpuId++;
- }
-
- CoreIndex += CpuTopo.Threads * sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- }
-
- CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
- CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
- }
-
- ClusterIndex = CoreIndex;
+ CoresPartSize = AddCoresToPpttTable (New, ClusterIndex, CpuTopo);
+ ClusterIndex += CoresPartSize;
+ New += CoresPartSize;
}
SocketIndex = ClusterIndex;
--
2.45.2
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* Re: [edk2-devel] [PATCH edk2-platforms v3 1/5] SbsaQemu: get the information of CPU topology via SMC calls
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 1/5] SbsaQemu: get the information of CPU topology via SMC calls Marcin Juszkiewicz
@ 2024-07-09 12:40 ` Leif Lindholm
[not found] ` <17E08BE30DD079C5.26166@groups.io>
1 sibling, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2024-07-09 12:40 UTC (permalink / raw)
To: Marcin Juszkiewicz
Cc: devel, Xiong Yining, Ard Biesheuvel, Graeme Gregory, Chen Baozi
On Tue, Jul 09, 2024 at 12:47:06 +0200, Marcin Juszkiewicz wrote:
> Provide functions to check for CPU topology information:
> - the number of sockets on sbsa-ref platform.
> - the number of clusters in one socket.
> - the number of cores in one cluster.
> - the number of threads in one core.
>
> As SMC calls can return up to 4 return values, the number of sockets,
> clusters and cores are read from TF-A using platform specific SMC call.
> Number of threads is caluculated using the cpu count and the number of
> sockets, clusters and cores.
>
> Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> ---
> .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 1 +
> .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h | 26 ++++++++++++++
> .../SbsaQemuHardwareInfoLib.c | 36 ++++++++++++++++++++
> 3 files changed, 63 insertions(+)
>
> diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
> index af6b120561ad..b57573735ace 100644
> --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
> +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
> @@ -16,6 +16,7 @@
> #define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101)
> #define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200)
> #define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201)
> +#define SIP_SVC_GET_CPU_TOPOLOGY SMC_SIP_FUNCTION_ID(202)
> #define SIP_SVC_GET_MEMORY_NODE_COUNT SMC_SIP_FUNCTION_ID(300)
> #define SIP_SVC_GET_MEMORY_NODE SMC_SIP_FUNCTION_ID(301)
>
> diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
> index e5076274fa0a..cef6f6f58194 100644
> --- a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
> +++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
> @@ -15,6 +15,19 @@ typedef struct {
> UINT64 AddressSize;
> } MemoryInfo;
>
> +/**
> + Sockets: the number of sockets on sbsa-ref platform.
> + Clusters: the number of clusters in one socket.
> + Cores: the number of cores in one cluster.
> + Threads: the number of threads in one core.
> +**/
> +typedef struct {
> + UINT32 Sockets;
> + UINT32 Clusters;
> + UINT32 Cores;
> + UINT32 Threads;
> +} CpuTopology;
> +
> /**
> Get CPU count from information passed by Qemu.
>
> @@ -83,4 +96,17 @@ GetNumaNodeCount (
> VOID
> );
>
> +/**
> + Get cpu topology(sockets, clusters, cores, threads) from device tree passed by Qemu.
We don't need to talk about qemu internals that will change in the
future. "Get cpu topology ... from Qemu.)
Other than that:
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
/
Leif
> +
> + @param [out] CpuTopo A pointer to the cpu topology.
> +
> +
> + @retval the information of cpu topology.
> +**/
> +VOID
> +GetCpuTopology (
> + OUT CpuTopology *CpuTopo
> + );
> +
> #endif /* HARDWARE_INFO_LIB */
> diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
> index 596a3453c70f..b17a2ae99b4e 100644
> --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
> +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
> @@ -181,3 +181,39 @@ GetNumaNodeCount (
>
> return NumberNumaNodes;
> }
> +
> +/**
> + Get CPU topology.
> +**/
> +VOID
> +GetCpuTopology (
> + OUT CpuTopology *CpuTopo
> + )
> +{
> + UINTN SmcResult;
> + UINTN Arg0;
> + UINTN Arg1;
> + UINTN Arg2;
> + UINT32 NumCores = GetCpuCount ();
> +
> + SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_TOPOLOGY, &Arg0, &Arg1, &Arg2);
> + if (SmcResult != SMC_SIP_CALL_SUCCESS) {
> + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_TOPOLOGY call failed. We have no cpu topology information.\n", __FUNCTION__));
> + ResetShutdown ();
> + } else {
> + CpuTopo->Sockets = Arg0;
> + CpuTopo->Clusters = Arg1;
> + CpuTopo->Cores = Arg2;
> + CpuTopo->Threads = NumCores / (CpuTopo->Sockets * CpuTopo->Clusters * CpuTopo->Cores);
> + }
> +
> + DEBUG ((
> + DEBUG_INFO,
> + "%a: CPU Topology: sockets are %d, clusters are %d, cores are %d, threads are %d\n",
> + __FUNCTION__,
> + CpuTopo->Sockets,
> + CpuTopo->Clusters,
> + CpuTopo->Cores,
> + CpuTopo->Threads
> + ));
> +}
>
> --
> 2.45.2
>
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* Re: [edk2-devel] [PATCH edk2-platforms v3 1/5] SbsaQemu: get the information of CPU topology via SMC calls
[not found] ` <17E08BE30DD079C5.26166@groups.io>
@ 2024-07-09 12:42 ` Leif Lindholm
0 siblings, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2024-07-09 12:42 UTC (permalink / raw)
To: Marcin Juszkiewicz
Cc: devel, Xiong Yining, Ard Biesheuvel, Graeme Gregory, Chen Baozi
On 2024-07-09 13:40, Leif Lindholm wrote:
> On Tue, Jul 09, 2024 at 12:47:06 +0200, Marcin Juszkiewicz wrote:
>> Provide functions to check for CPU topology information:
>> - the number of sockets on sbsa-ref platform.
>> - the number of clusters in one socket.
>> - the number of cores in one cluster.
>> - the number of threads in one core.
>>
>> As SMC calls can return up to 4 return values, the number of sockets,
>> clusters and cores are read from TF-A using platform specific SMC call.
>> Number of threads is caluculated using the cpu count and the number of
>> sockets, clusters and cores.
>>
>> Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
>> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
>> ---
>> .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 1 +
>> .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h | 26 ++++++++++++++
>> .../SbsaQemuHardwareInfoLib.c | 36 ++++++++++++++++++++
>> 3 files changed, 63 insertions(+)
>>
>> diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
>> index af6b120561ad..b57573735ace 100644
>> --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
>> +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
>> @@ -16,6 +16,7 @@
>> #define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101)
>> #define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200)
>> #define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201)
>> +#define SIP_SVC_GET_CPU_TOPOLOGY SMC_SIP_FUNCTION_ID(202)
>> #define SIP_SVC_GET_MEMORY_NODE_COUNT SMC_SIP_FUNCTION_ID(300)
>> #define SIP_SVC_GET_MEMORY_NODE SMC_SIP_FUNCTION_ID(301)
>>
>> diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
>> index e5076274fa0a..cef6f6f58194 100644
>> --- a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
>> +++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
>> @@ -15,6 +15,19 @@ typedef struct {
>> UINT64 AddressSize;
>> } MemoryInfo;
>>
>> +/**
>> + Sockets: the number of sockets on sbsa-ref platform.
>> + Clusters: the number of clusters in one socket.
>> + Cores: the number of cores in one cluster.
>> + Threads: the number of threads in one core.
>> +**/
>> +typedef struct {
>> + UINT32 Sockets;
>> + UINT32 Clusters;
>> + UINT32 Cores;
>> + UINT32 Threads;
>> +} CpuTopology;
>> +
>> /**
>> Get CPU count from information passed by Qemu.
>>
>> @@ -83,4 +96,17 @@ GetNumaNodeCount (
>> VOID
>> );
>>
>> +/**
>> + Get cpu topology(sockets, clusters, cores, threads) from device tree passed by Qemu.
>
> We don't need to talk about qemu internals that will change in the
> future. "Get cpu topology ... from Qemu.)
No, hang on, that's rubbish. "from TF-A".
/
Leif
>
> Other than that:
> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
>
> /
> Leif
>
>> +
>> + @param [out] CpuTopo A pointer to the cpu topology.
>> +
>> +
>> + @retval the information of cpu topology.
>> +**/
>> +VOID
>> +GetCpuTopology (
>> + OUT CpuTopology *CpuTopo
>> + );
>> +
>> #endif /* HARDWARE_INFO_LIB */
>> diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
>> index 596a3453c70f..b17a2ae99b4e 100644
>> --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
>> +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
>> @@ -181,3 +181,39 @@ GetNumaNodeCount (
>>
>> return NumberNumaNodes;
>> }
>> +
>> +/**
>> + Get CPU topology.
>> +**/
>> +VOID
>> +GetCpuTopology (
>> + OUT CpuTopology *CpuTopo
>> + )
>> +{
>> + UINTN SmcResult;
>> + UINTN Arg0;
>> + UINTN Arg1;
>> + UINTN Arg2;
>> + UINT32 NumCores = GetCpuCount ();
>> +
>> + SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_TOPOLOGY, &Arg0, &Arg1, &Arg2);
>> + if (SmcResult != SMC_SIP_CALL_SUCCESS) {
>> + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_TOPOLOGY call failed. We have no cpu topology information.\n", __FUNCTION__));
>> + ResetShutdown ();
>> + } else {
>> + CpuTopo->Sockets = Arg0;
>> + CpuTopo->Clusters = Arg1;
>> + CpuTopo->Cores = Arg2;
>> + CpuTopo->Threads = NumCores / (CpuTopo->Sockets * CpuTopo->Clusters * CpuTopo->Cores);
>> + }
>> +
>> + DEBUG ((
>> + DEBUG_INFO,
>> + "%a: CPU Topology: sockets are %d, clusters are %d, cores are %d, threads are %d\n",
>> + __FUNCTION__,
>> + CpuTopo->Sockets,
>> + CpuTopo->Clusters,
>> + CpuTopo->Cores,
>> + CpuTopo->Threads
>> + ));
>> +}
>>
>> --
>> 2.45.2
>>
>
>
>
>
>
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* Re: [edk2-devel] [PATCH edk2-platforms v3 2/5] SbsaQemu: align the PPTT tables with QEMU
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 2/5] SbsaQemu: align the PPTT tables with QEMU Marcin Juszkiewicz
@ 2024-07-09 12:43 ` Leif Lindholm
0 siblings, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2024-07-09 12:43 UTC (permalink / raw)
To: devel, marcin.juszkiewicz
Cc: Xiong Yining, Ard Biesheuvel, Graeme Gregory, Chen Baozi
On Tue, Jul 09, 2024 at 12:47:07 +0200, Marcin Juszkiewicz wrote:
> From: Xiong Yining <xiongyining1480@phytium.com.cn>
>
> To align the CPU topology information recognized by the operating system
> with the CPU topology information configured by QEMU, we need to make
> use of the CPU topology information to create complex PPTT tables
> setups.
>
> We can get the CPU topology information via SMC.
>
> Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
/
Leif
> ---
> .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 11 ++
> .../Include/IndustryStandard/SbsaQemuAcpi.h | 32 ----
> .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 187 +++++++++++++++-----
> 3 files changed, 158 insertions(+), 72 deletions(-)
>
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
> index e5f0748bb16e..085c681ba55f 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
> @@ -88,4 +88,15 @@ typedef struct {
> ClockDomain /* Clock Domain */ \
> }
>
> +#define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, ACPIProcessorID, NumberOfPrivateResources) \
> + { \
> + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type */ \
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources * sizeof (UINT32), /* Length */ \
> + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, /* Reserved */ \
> + Flags, /* Flags */ \
> + Parent, /* Parent */ \
> + ACPIProcessorID, /* ACPI Processor ID */ \
> + NumberOfPrivateResources /* Number of private resources */ \
> + }
> +
> #endif
> diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> index ae151210c2c6..2f87591e737a 100644
> --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> @@ -166,36 +166,4 @@ typedef struct {
> 64 /* LineSize */ \
> }
>
> -#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT { \
> - EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
> - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR), \
> - { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> - { \
> - EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ \
> - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
> - EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
> - EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */ \
> - EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
> - }, \
> - 0, /* Parent */ \
> - 0, /* AcpiProcessorId */ \
> - 0, /* NumberOfPrivateResources */ \
> - }
> -
> -#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT { \
> - EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
> - (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32))), \
> - { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> - { \
> - EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */ \
> - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorValid */ \
> - EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
> - EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ \
> - EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
> - }, \
> - 0, /* Parent */ \
> - 0, /* AcpiProcessorId */ \
> - 2, /* NumberOfPrivateResources */ \
> - }
> -
> #endif
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> index e0eef54ff907..465a69d7328c 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> @@ -505,14 +505,51 @@ AddPpttTable (
> EFI_PHYSICAL_ADDRESS PageAddress;
> UINT8 *New;
> UINT32 CpuId;
> - UINT32 NumCores = GetCpuCount ();
> + CpuTopology CpuTopo;
> +
> + GetCpuTopology (&CpuTopo);
>
> EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
> EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
> EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
>
> - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT;
> - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PPTT_CORE_STRUCT;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS SocketFlags = {
> + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
> + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
> + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
> + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
> + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
> + };
> +
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS ClusterFlags = {
> + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
> + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
> + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
> + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
> + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
> + };
> +
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
> + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
> + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
> + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
> + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
> + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
> + };
> +
> + if (CpuTopo.Threads > 1) {
> + // The Thread structure is the leaf structure, adjust the value of CoreFlags.
> + CoreFlags.AcpiProcessorIdValid = EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID;
> + CoreFlags.NodeIsALeaf = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
> + }
> +
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
> + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
> + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
> + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD,
> + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
> + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
> + };
>
> EFI_ACPI_DESCRIPTION_HEADER Header =
> SBSAQEMU_ACPI_HEADER (
> @@ -522,10 +559,16 @@ AddPpttTable (
> );
>
> TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
> - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
> - (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) +
> - (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) +
> - (sizeof (UINT32) * 2 * NumCores);
> + CpuTopo.Sockets * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
> + CpuTopo.Clusters * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3 +
> + CpuTopo.Cores * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
> + sizeof (UINT32) * 2)));
> +
> + if (CpuTopo.Threads > 1) {
> + TableSize += CpuTopo.Sockets * CpuTopo.Clusters * CpuTopo.Cores * CpuTopo.Threads *
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> + }
>
> Status = gBS->AllocatePages (
> AllocateAnyPages,
> @@ -546,39 +589,103 @@ AddPpttTable (
> ((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length = TableSize;
> New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
>
> - // Add the Cluster PPTT structure
> - CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
> - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> -
> - // Add L1 D Cache structure
> - CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> - ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2_CACHE_INDEX;
> - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> -
> - // Add L1 I Cache structure
> - CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> - ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2_CACHE_INDEX;
> - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> -
> - // Add L2 Cache structure
> - CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> - ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 0; /* L2 is LLC */
> - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> -
> - for (CpuId = 0; CpuId < NumCores; CpuId++) {
> - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr;
> - UINT32 *PrivateResourcePtr;
> -
> - CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
> - CorePtr = (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *)New;
> - CorePtr->Parent = CLUSTER_INDEX;
> - CorePtr->AcpiProcessorId = CpuId;
> - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> -
> - PrivateResourcePtr = (UINT32 *)New;
> - PrivateResourcePtr[0] = L1_D_CACHE_INDEX;
> - PrivateResourcePtr[1] = L1_I_CACHE_INDEX;
> - New += (2 * sizeof (UINT32));
> + UINT32 SocketNum, ClusterNum, CoreNum, ThreadNum;
> + UINT32 SocketIndex, ClusterIndex, CoreIndex, L1DCacheIndex, L1ICacheIndex, L2CacheIndex;
> +
> + CpuId = 0;
> + SocketIndex = sizeof (EFI_ACPI_DESCRIPTION_HEADER);
> + for (SocketNum = 0; SocketNum < CpuTopo.Sockets; SocketNum++) {
> + // Add the Socket PPTT structure
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Socket = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> + SocketFlags,
> + 0,
> + 0,
> + 0
> + );
> + CopyMem (New, &Socket, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> +
> + ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> + for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) {
> + L1DCacheIndex = ClusterIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> + L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> + L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> + CoreIndex = L2CacheIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> +
> + // Add the Cluster PPTT structure
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> + ClusterFlags,
> + SocketIndex,
> + 0,
> + 0
> + );
> + CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> +
> + // Add L1 D Cache structure
> + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> +
> + // Add L1 I Cache structure
> + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> +
> + // Add L2 Cache structure
> + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> +
> + for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
> + UINT32 *PrivateResourcePtr;
> + UINT32 CoreCpuId;
> +
> + if (CpuTopo.Threads == 1) {
> + CoreCpuId = CpuId;
> + } else {
> + CoreCpuId = 0;
> + }
> +
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> + CoreFlags,
> + ClusterIndex,
> + CoreCpuId,
> + 2
> + );
> + CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> +
> + PrivateResourcePtr = (UINT32 *)New;
> + PrivateResourcePtr[0] = L1DCacheIndex;
> + PrivateResourcePtr[1] = L1ICacheIndex;
> + New += (2 * sizeof (UINT32));
> +
> + if (CpuTopo.Threads == 1) {
> + CpuId++;
> + } else {
> + // Add the Thread PPTT structure
> + for (ThreadNum = 0; ThreadNum < CpuTopo.Threads; ThreadNum++) {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> + ThreadFlags,
> + CoreIndex,
> + CpuId,
> + 0
> + );
> + CopyMem (New, &Thread, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> + CpuId++;
> + }
> +
> + CoreIndex += CpuTopo.Threads * sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> + }
> +
> + CoreIndex += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
> + }
> +
> + ClusterIndex = CoreIndex;
> + }
> +
> + SocketIndex = ClusterIndex;
> }
>
> // Perform Checksum
>
> --
> 2.45.2
>
>
>
>
>
>
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [PATCH edk2-platforms v3 3/5] SbsaQemu: update PPTT to ACPI 6.5
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 3/5] SbsaQemu: update PPTT to ACPI 6.5 Marcin Juszkiewicz
@ 2024-07-09 12:44 ` Leif Lindholm
0 siblings, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2024-07-09 12:44 UTC (permalink / raw)
To: Marcin Juszkiewicz
Cc: devel, Xiong Yining, Ard Biesheuvel, Graeme Gregory, Chen Baozi
On Tue, Jul 09, 2024 at 12:47:08 +0200, Marcin Juszkiewicz wrote:
> ACPI 6.5 is the newest version of specification so far. The only change
"The only functional change..."
With that:
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
/
Leif
> to make is handling of CacheId (has to be unique and higher than zero).
>
> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> ---
> .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 4 +-
> .../Include/IndustryStandard/SbsaQemuAcpi.h | 46 ++++---
> .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 127 ++++++++++----------
> 3 files changed, 94 insertions(+), 83 deletions(-)
>
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
> index 085c681ba55f..5aaf02e3ca30 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
> @@ -90,8 +90,8 @@ typedef struct {
>
> #define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, ACPIProcessorID, NumberOfPrivateResources) \
> { \
> - EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type */ \
> - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources * sizeof (UINT32), /* Length */ \
> + EFI_ACPI_6_5_PPTT_TYPE_PROCESSOR, /* Type */ \
> + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources * sizeof (UINT32), /* Length */ \
> { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, /* Reserved */ \
> Flags, /* Flags */ \
> Parent, /* Parent */ \
> diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> index 2f87591e737a..fa2e2b30bb7d 100644
> --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> @@ -87,13 +87,13 @@ typedef struct {
> #define SBSAQEMU_L2_CACHE_ASSC 8
>
> #define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
> -#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR))
> -#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
> -#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
> +#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR))
> +#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
> +#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
>
> #define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT { \
> - EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
> - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
> + EFI_ACPI_6_5_PPTT_TYPE_CACHE, \
> + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE), \
> { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> { \
> 1, /* SizePropertyValid */ \
> @@ -103,22 +103,24 @@ typedef struct {
> 1, /* CacheTypeValid */ \
> 1, /* WritePolicyValid */ \
> 1, /* LineSizeValid */ \
> + 1, /* CacheIdValid */ \
> }, \
> 0, /* NextLevelOfCache */ \
> SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ \
> SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ \
> SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ \
> { \
> - EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
> - EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
> - EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
> + EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
> + EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
> + EFI_ACPI_6_5_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
> }, \
> - 64 /* LineSize */ \
> + 64, /* LineSize */ \
> + 0 /* CacheId */ \
> }
>
> #define SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT { \
> - EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
> - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
> + EFI_ACPI_6_5_PPTT_TYPE_CACHE, \
> + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE), \
> { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> { \
> 1, /* SizePropertyValid */ \
> @@ -128,22 +130,24 @@ typedef struct {
> 1, /* CacheTypeValid */ \
> 1, /* WritePolicyValid */ \
> 1, /* LineSizeValid */ \
> + 1, /* CacheIdValid */ \
> }, \
> 0, /* NextLevelOfCache */ \
> SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ \
> SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ \
> SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ \
> { \
> - EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, \
> - EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
> + EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ, \
> + EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
> 0, \
> }, \
> - 64 /* LineSize */ \
> + 64, /* LineSize */ \
> + 0 /* CacheId */ \
> }
>
> #define SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT { \
> - EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
> - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
> + EFI_ACPI_6_5_PPTT_TYPE_CACHE, \
> + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE), \
> { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> { \
> 1, /* SizePropertyValid */ \
> @@ -153,17 +157,19 @@ typedef struct {
> 1, /* CacheTypeValid */ \
> 1, /* WritePolicyValid */ \
> 1, /* LineSizeValid */ \
> + 1, /* CacheIdValid */ \
> }, \
> 0, /* NextLevelOfCache */ \
> SBSAQEMU_L2_CACHE_SIZE, /* Size */ \
> SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ \
> SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ \
> { \
> - EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
> - EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
> - EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
> + EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
> + EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
> + EFI_ACPI_6_5_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
> }, \
> - 64 /* LineSize */ \
> + 64, /* LineSize */ \
> + 0 /* CacheId */ \
> }
>
> #endif
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> index 465a69d7328c..cf0102d11f1f 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> @@ -506,35 +506,36 @@ AddPpttTable (
> UINT8 *New;
> UINT32 CpuId;
> CpuTopology CpuTopo;
> + UINT32 CacheId;
>
> GetCpuTopology (&CpuTopo);
>
> - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
> - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
> - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
> + EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
> + EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
> + EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
>
> - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS SocketFlags = {
> - EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
> - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
> - EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
> - EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
> - EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
> + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS SocketFlags = {
> + EFI_ACPI_6_5_PPTT_PACKAGE_PHYSICAL,
> + EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID,
> + EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
> + EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF,
> + EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
> };
>
> - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS ClusterFlags = {
> - EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
> - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
> - EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
> - EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
> - EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
> + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS ClusterFlags = {
> + EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
> + EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID,
> + EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
> + EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF,
> + EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
> };
>
> - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
> - EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
> - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
> - EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
> - EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
> - EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
> + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
> + EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
> + EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
> + EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
> + EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
> + EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
> };
>
> if (CpuTopo.Threads > 1) {
> @@ -543,31 +544,31 @@ AddPpttTable (
> CoreFlags.NodeIsALeaf = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
> }
>
> - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
> - EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
> - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
> - EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD,
> - EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
> - EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
> + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
> + EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
> + EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
> + EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD,
> + EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
> + EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
> };
>
> EFI_ACPI_DESCRIPTION_HEADER Header =
> SBSAQEMU_ACPI_HEADER (
> - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> + EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> EFI_ACPI_DESCRIPTION_HEADER,
> - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
> + EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
> );
>
> TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
> - CpuTopo.Sockets * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
> - CpuTopo.Clusters * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
> - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3 +
> - CpuTopo.Cores * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
> + CpuTopo.Sockets * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> + CpuTopo.Clusters * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
> + CpuTopo.Cores * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> sizeof (UINT32) * 2)));
>
> if (CpuTopo.Threads > 1) {
> TableSize += CpuTopo.Sockets * CpuTopo.Clusters * CpuTopo.Cores * CpuTopo.Threads *
> - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> }
>
> Status = gBS->AllocatePages (
> @@ -593,48 +594,52 @@ AddPpttTable (
> UINT32 SocketIndex, ClusterIndex, CoreIndex, L1DCacheIndex, L1ICacheIndex, L2CacheIndex;
>
> CpuId = 0;
> + CacheId = 1; // 0 is not a valid Cache ID.
> SocketIndex = sizeof (EFI_ACPI_DESCRIPTION_HEADER);
> for (SocketNum = 0; SocketNum < CpuTopo.Sockets; SocketNum++) {
> // Add the Socket PPTT structure
> - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Socket = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Socket = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> SocketFlags,
> 0,
> 0,
> 0
> );
> - CopyMem (New, &Socket, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
> - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> + CopyMem (New, &Socket, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
>
> - ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> + ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) {
> - L1DCacheIndex = ClusterIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> - L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> - L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> - CoreIndex = L2CacheIndex + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> + L1DCacheIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> + L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> + L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> + CoreIndex = L2CacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
>
> // Add the Cluster PPTT structure
> - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> ClusterFlags,
> SocketIndex,
> 0,
> 0
> );
> - CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
> - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> + CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
>
> // Add L1 D Cache structure
> - CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> - ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> + L1DCache.CacheId = CacheId++;
> + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
>
> // Add L1 I Cache structure
> - CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> - ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> + L1ICache.CacheId = CacheId++;
> + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
>
> // Add L2 Cache structure
> - CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> + L2Cache.CacheId = CacheId++;
> + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
>
> for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
> UINT32 *PrivateResourcePtr;
> @@ -646,14 +651,14 @@ AddPpttTable (
> CoreCpuId = 0;
> }
>
> - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> CoreFlags,
> ClusterIndex,
> CoreCpuId,
> 2
> );
> - CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
> - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> + CopyMem (New, &Core, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
>
> PrivateResourcePtr = (UINT32 *)New;
> PrivateResourcePtr[0] = L1DCacheIndex;
> @@ -665,21 +670,21 @@ AddPpttTable (
> } else {
> // Add the Thread PPTT structure
> for (ThreadNum = 0; ThreadNum < CpuTopo.Threads; ThreadNum++) {
> - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> ThreadFlags,
> CoreIndex,
> CpuId,
> 0
> );
> - CopyMem (New, &Thread, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
> - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> + CopyMem (New, &Thread, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> CpuId++;
> }
>
> - CoreIndex += CpuTopo.Threads * sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> + CoreIndex += CpuTopo.Threads * sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> }
>
> - CoreIndex += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
> + CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
> }
>
> ClusterIndex = CoreIndex;
>
> --
> 2.45.2
>
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [PATCH edk2-platforms v3 5/5] SbsaQemu: introduce helper in PPTT generation
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 5/5] SbsaQemu: introduce helper in PPTT generation Marcin Juszkiewicz
@ 2024-07-09 13:00 ` Leif Lindholm
2024-07-09 13:12 ` Marcin Juszkiewicz
0 siblings, 1 reply; 16+ messages in thread
From: Leif Lindholm @ 2024-07-09 13:00 UTC (permalink / raw)
To: Marcin Juszkiewicz
Cc: devel, Xiong Yining, Ard Biesheuvel, Graeme Gregory, Chen Baozi
On Tue, Jul 09, 2024 at 12:47:10 +0200, Marcin Juszkiewicz wrote:
> Function AddPpttTable() adding PPTT got too long. This change moves part
> of it into helper function AddCoresToPpttTable() which takes care of
> generating entries for Core and below (Cache, Thread).
>
> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> ---
> .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 237 +++++++++++---------
> 1 file changed, 133 insertions(+), 104 deletions(-)
>
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> index a7a9664abdcb..a4b2ee2fdcb0 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> @@ -29,6 +29,9 @@
>
> static UINTN GicItsBase;
>
> +static UINTN CpuId;
> +static UINTN CacheId;
> +
static variables are supposed to have g (global) or m (module) prefix.
This is local, so m.
(Yes, that means I missed that when reviewing the GitIts bits.)
Also, why are these in a #pragma pack(1) block?
> #pragma pack ()
>
> /*
> @@ -491,6 +494,126 @@ AddSsdtTable (
> return Status;
> }
>
STATIC
> +UINT32
> +AddCoresToPpttTable (
> + UINT8 *New,
> + UINT32 ClusterIndex,
> + CpuTopology CpuTopo
> + )
> +{
> + UINT32 L1DCacheIndex;
> + UINT32 L1ICacheIndex;
> + UINT32 L2CacheIndex;
> + UINT32 CoreIndex;
> + UINT32 Index;
> + UINT32 CoreCpuId;
> + UINT32 CoreNum;
> + UINT32 ThreadNum;
> + UINT32 *PrivateResourcePtr;
> +
> + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
> + EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
> + EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
> + EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
> + EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
> + EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
> + };
> +
> + if (CpuTopo.Threads > 1) {
> + // The Thread structure is the leaf structure, adjust the value of CoreFlags.
> + CoreFlags.AcpiProcessorIdValid = EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID;
> + CoreFlags.NodeIsALeaf = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
> + }
> +
> + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
> + EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
> + EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
> + EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD,
> + EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
> + EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
> + };
> +
> + EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
> + EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
> + EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
> +
> + CoreIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> + Index = CoreIndex;
> +
> + for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
> + if (CpuTopo.Threads == 1) {
> + CoreCpuId = CpuId;
> + } else {
> + CoreCpuId = 0;
> + }
> +
> + // space for Core + PrivateResourcePtr
> + Index += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> + Index += sizeof (UINT32) * 2;
> +
> + L1DCacheIndex = Index;
> + L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> + L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> +
> + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> + CoreFlags,
> + ClusterIndex,
> + CoreCpuId,
> + 2
> + );
> +
> + CopyMem (New, &Core, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> +
> + PrivateResourcePtr = (UINT32 *)New;
> + PrivateResourcePtr[0] = L1DCacheIndex;
> + PrivateResourcePtr[1] = L1ICacheIndex;
> + New += (2 * sizeof (UINT32));
> +
> + // Add L1 D Cache structure
> + L1DCache.CacheId = CacheId++;
> + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> +
> + // Add L1 I Cache structure
> + L1ICache.CacheId = CacheId++;
> + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> +
> + // Add L2 Cache structure
> + L2Cache.CacheId = CacheId++;
> + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> +
> + Index += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
> +
> + if (CpuTopo.Threads == 1) {
> + CpuId++;
> + } else {
> + // Add the Thread PPTT structure
> + for (ThreadNum = 0; ThreadNum < CpuTopo.Threads; ThreadNum++) {
> + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> + ThreadFlags,
> + CoreIndex,
> + CpuId,
> + 0
> + );
> + CopyMem (New, &Thread, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> + CpuId++;
> + }
> +
> + Index += CpuTopo.Threads * sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> + }
> +
> + CoreIndex = Index;
> + }
> +
> + return CoreIndex - ClusterIndex - sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> +}
> +
> /*
> * A function that adds the PPTT ACPI table.
> */
> @@ -502,18 +625,17 @@ AddPpttTable (
> EFI_STATUS Status;
> UINTN TableHandle;
> UINT32 TableSize;
> + UINT32 CoresPartSize;
> + UINT32 SocketNum;
> + UINT32 ClusterNum;
> + UINT32 SocketIndex;
> + UINT32 ClusterIndex;
> EFI_PHYSICAL_ADDRESS PageAddress;
> UINT8 *New;
> - UINT32 CpuId;
> CpuTopology CpuTopo;
> - UINT32 CacheId;
>
> GetCpuTopology (&CpuTopo);
>
> - EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
> - EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
> - EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
> -
> EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS SocketFlags = {
> EFI_ACPI_6_5_PPTT_PACKAGE_PHYSICAL,
> EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID,
> @@ -530,28 +652,6 @@ AddPpttTable (
> EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
> };
>
> - EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
> - EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
> - EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
> - EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
> - EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
> - EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
> - };
> -
> - if (CpuTopo.Threads > 1) {
> - // The Thread structure is the leaf structure, adjust the value of CoreFlags.
> - CoreFlags.AcpiProcessorIdValid = EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID;
> - CoreFlags.NodeIsALeaf = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
> - }
> -
> - EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
> - EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
> - EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
> - EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD,
> - EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
> - EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
> - };
> -
> EFI_ACPI_DESCRIPTION_HEADER Header =
> SBSAQEMU_ACPI_HEADER (
> EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> @@ -590,11 +690,9 @@ AddPpttTable (
> ((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length = TableSize;
> New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
>
> - UINT32 SocketNum, ClusterNum, CoreNum, ThreadNum;
> - UINT32 SocketIndex, ClusterIndex, CoreIndex, L1DCacheIndex, L1ICacheIndex, L2CacheIndex;
> + CpuId = 0;
> + CacheId = 1; // 0 is not a valid Cache ID.
>
> - CpuId = 0;
> - CacheId = 1; // 0 is not a valid Cache ID.
> SocketIndex = sizeof (EFI_ACPI_DESCRIPTION_HEADER);
> for (SocketNum = 0; SocketNum < CpuTopo.Sockets; SocketNum++) {
> // Add the Socket PPTT structure
> @@ -609,8 +707,6 @@ AddPpttTable (
>
> ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) {
> - CoreIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> -
> // Add the Cluster PPTT structure
> EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> ClusterFlags,
> @@ -621,76 +717,9 @@ AddPpttTable (
> CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
> New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
>
> - for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
> - UINT32 *PrivateResourcePtr;
> - UINT32 CoreCpuId;
> -
> - // two UINT32s for PrivateResourcePtr data
> - L1DCacheIndex = CoreIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
> - L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> - L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> -
> - if (CpuTopo.Threads == 1) {
> - CoreCpuId = CpuId;
> - } else {
> - CoreCpuId = 0;
> - }
> -
> - EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> - CoreFlags,
> - ClusterIndex,
> - CoreCpuId,
> - 2
> - );
> - CopyMem (New, &Core, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
> - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> -
> - PrivateResourcePtr = (UINT32 *)New;
> - PrivateResourcePtr[0] = L1DCacheIndex;
> - PrivateResourcePtr[1] = L1ICacheIndex;
> - New += (2 * sizeof (UINT32));
> -
> - // Add L1 D Cache structure
> - L1DCache.CacheId = CacheId++;
> - CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> - ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> -
> - // Add L1 I Cache structure
> - L1ICache.CacheId = CacheId++;
> - CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> - ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> -
> - // Add L2 Cache structure
> - L2Cache.CacheId = CacheId++;
> - CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> -
> - if (CpuTopo.Threads == 1) {
> - CpuId++;
> - } else {
> - // Add the Thread PPTT structure
> - for (ThreadNum = 0; ThreadNum < CpuTopo.Threads; ThreadNum++) {
> - EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> - ThreadFlags,
> - CoreIndex,
> - CpuId,
> - 0
> - );
> - CopyMem (New, &Thread, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
> - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> - CpuId++;
> - }
> -
> - CoreIndex += CpuTopo.Threads * sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> - }
> -
> - CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
> - CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
> - }
> -
> - ClusterIndex = CoreIndex;
> + CoresPartSize = AddCoresToPpttTable (New, ClusterIndex, CpuTopo);
> + ClusterIndex += CoresPartSize;
This sounds like ClisterIndex is no longer an Index after this patch.
Should it be renamed?
/
Leif
> + New += CoresPartSize;
> }
>
> SocketIndex = ClusterIndex;
>
> --
> 2.45.2
>
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* Re: [edk2-devel] [PATCH edk2-platforms v3 4/5] SbsaQemu: provide cache info per core in PPTT
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 4/5] SbsaQemu: provide cache info per core in PPTT Marcin Juszkiewicz
@ 2024-07-09 13:01 ` Leif Lindholm
2024-07-10 13:58 ` Jonathan Cameron via groups.io
0 siblings, 1 reply; 16+ messages in thread
From: Leif Lindholm @ 2024-07-09 13:01 UTC (permalink / raw)
To: Marcin Juszkiewicz
Cc: devel, Xiong Yining, Ard Biesheuvel, Graeme Gregory, Chen Baozi
On Tue, Jul 09, 2024 at 12:47:09 +0200, Marcin Juszkiewicz wrote:
> During Linaro Connect MAD24 I was asked to move cache information from
> being 'per cluster' to be 'per core'. This is a move for implementing
> MPAM support.
>
> So topology moves from:
>
> Socket -> Clusters -> Cores + Caches -> Threads (if exist)
>
> to:
>
> Socket -> Clusters -> Cores -> Caches + Threads (if exist)
>
> Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
> implement them at all so we can tell whatever.
>
> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
/
Leif
> ---
> .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 47 +++++++++++---------
> 1 file changed, 25 insertions(+), 22 deletions(-)
>
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> index cf0102d11f1f..a7a9664abdcb 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> @@ -562,8 +562,8 @@ AddPpttTable (
> TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
> CpuTopo.Sockets * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> CpuTopo.Clusters * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> - sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
> CpuTopo.Cores * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
> sizeof (UINT32) * 2)));
>
> if (CpuTopo.Threads > 1) {
> @@ -609,10 +609,7 @@ AddPpttTable (
>
> ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) {
> - L1DCacheIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> - L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> - L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> - CoreIndex = L2CacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> + CoreIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
>
> // Add the Cluster PPTT structure
> EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> @@ -624,27 +621,15 @@ AddPpttTable (
> CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
> New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
>
> - // Add L1 D Cache structure
> - L1DCache.CacheId = CacheId++;
> - CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> - ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> -
> - // Add L1 I Cache structure
> - L1ICache.CacheId = CacheId++;
> - CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> - ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> -
> - // Add L2 Cache structure
> - L2Cache.CacheId = CacheId++;
> - CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> -
> for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
> UINT32 *PrivateResourcePtr;
> UINT32 CoreCpuId;
>
> + // two UINT32s for PrivateResourcePtr data
> + L1DCacheIndex = CoreIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
> + L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> + L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> +
> if (CpuTopo.Threads == 1) {
> CoreCpuId = CpuId;
> } else {
> @@ -665,6 +650,23 @@ AddPpttTable (
> PrivateResourcePtr[1] = L1ICacheIndex;
> New += (2 * sizeof (UINT32));
>
> + // Add L1 D Cache structure
> + L1DCache.CacheId = CacheId++;
> + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> +
> + // Add L1 I Cache structure
> + L1ICache.CacheId = CacheId++;
> + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> +
> + // Add L2 Cache structure
> + L2Cache.CacheId = CacheId++;
> + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> +
> if (CpuTopo.Threads == 1) {
> CpuId++;
> } else {
> @@ -685,6 +687,7 @@ AddPpttTable (
> }
>
> CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
> + CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
> }
>
> ClusterIndex = CoreIndex;
>
> --
> 2.45.2
>
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* Re: [edk2-devel] [PATCH edk2-platforms v3 5/5] SbsaQemu: introduce helper in PPTT generation
2024-07-09 13:00 ` Leif Lindholm
@ 2024-07-09 13:12 ` Marcin Juszkiewicz
2024-07-09 13:15 ` Leif Lindholm
0 siblings, 1 reply; 16+ messages in thread
From: Marcin Juszkiewicz @ 2024-07-09 13:12 UTC (permalink / raw)
To: devel, quic_llindhol
Cc: devel, Xiong Yining, Ard Biesheuvel, Graeme Gregory, Chen Baozi
Dnia wtorek, 9 lipca 2024 15:00:12 CEST Leif Lindholm via groups.io pisze:
> On Tue, Jul 09, 2024 at 12:47:10 +0200, Marcin Juszkiewicz wrote:
> > Function AddPpttTable() adding PPTT got too long. This change moves part
> > of it into helper function AddCoresToPpttTable() which takes care of
> > generating entries for Core and below (Cache, Thread).
> >
> > Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> > ---
> >
> > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 237
> > +++++++++++--------- 1 file changed, 133 insertions(+), 104 deletions(-)
> >
> > diff --git
> > a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index
> > a7a9664abdcb..a4b2ee2fdcb0 100644
> > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > @@ -29,6 +29,9 @@
> >
> > static UINTN GicItsBase;
> >
> > +static UINTN CpuId;
> > +static UINTN CacheId;
> > +
>
> static variables are supposed to have g (global) or m (module) prefix.
> This is local, so m.
> (Yes, that means I missed that when reviewing the GitIts bits.)
>
> Also, why are these in a #pragma pack(1) block?
Added right after GicItsBase. Moved out of block.
> > #pragma pack ()
> STATIC
>
> > +UINT32
> > +AddCoresToPpttTable (
> > + UINT8 *New,
> > + UINT32 ClusterIndex,
> > + CpuTopology CpuTopo
> > + )
done
> > - ClusterIndex = CoreIndex;
> > + CoresPartSize = AddCoresToPpttTable (New, ClusterIndex, CpuTopo);
> > + ClusterIndex += CoresPartSize;
>
> This sounds like ClisterIndex is no longer an Index after this patch.
> Should it be renamed?
It is still an Index. CoresPartSize is a size taken by Core/Cache/Thread part
of this Cluster.
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* Re: [edk2-devel] [PATCH edk2-platforms v3 5/5] SbsaQemu: introduce helper in PPTT generation
2024-07-09 13:12 ` Marcin Juszkiewicz
@ 2024-07-09 13:15 ` Leif Lindholm
0 siblings, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2024-07-09 13:15 UTC (permalink / raw)
To: devel, marcin.juszkiewicz
Cc: Xiong Yining, Ard Biesheuvel, Graeme Gregory, Chen Baozi
On Tue, Jul 09, 2024 at 15:12:37 +0200, Marcin Juszkiewicz wrote:
> Dnia wtorek, 9 lipca 2024 15:00:12 CEST Leif Lindholm via groups.io pisze:
> > On Tue, Jul 09, 2024 at 12:47:10 +0200, Marcin Juszkiewicz wrote:
> > > Function AddPpttTable() adding PPTT got too long. This change moves part
> > > of it into helper function AddCoresToPpttTable() which takes care of
> > > generating entries for Core and below (Cache, Thread).
> > >
> > > Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> > > ---
> > >
> > > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 237
> > > +++++++++++--------- 1 file changed, 133 insertions(+), 104 deletions(-)
> > >
> > > diff --git
> > > a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index
> > > a7a9664abdcb..a4b2ee2fdcb0 100644
> > > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > @@ -29,6 +29,9 @@
> > >
> > > static UINTN GicItsBase;
> > >
> > > +static UINTN CpuId;
> > > +static UINTN CacheId;
> > > +
> >
> > static variables are supposed to have g (global) or m (module) prefix.
> > This is local, so m.
> > (Yes, that means I missed that when reviewing the GitIts bits.)
> >
> > Also, why are these in a #pragma pack(1) block?
>
> Added right after GicItsBase. Moved out of block.
I don't think it makes any sense for GicItsBase either, but that's not
part of this review.
> > > #pragma pack ()
>
> > STATIC
> >
> > > +UINT32
> > > +AddCoresToPpttTable (
> > > + UINT8 *New,
> > > + UINT32 ClusterIndex,
> > > + CpuTopology CpuTopo
> > > + )
>
> done
>
> > > - ClusterIndex = CoreIndex;
> > > + CoresPartSize = AddCoresToPpttTable (New, ClusterIndex, CpuTopo);
> > > + ClusterIndex += CoresPartSize;
> >
> > This sounds like ClisterIndex is no longer an Index after this patch.
> > Should it be renamed?
>
> It is still an Index. CoresPartSize is a size taken by Core/Cache/Thread part
> of this Cluster.
But doesn't that make it an offset instead of an index?
/
Leif
>
>
>
>
>
>
>
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* Re: [edk2-devel] [PATCH edk2-platforms v3 4/5] SbsaQemu: provide cache info per core in PPTT
2024-07-09 13:01 ` Leif Lindholm
@ 2024-07-10 13:58 ` Jonathan Cameron via groups.io
2024-07-10 14:39 ` Leif Lindholm
0 siblings, 1 reply; 16+ messages in thread
From: Jonathan Cameron via groups.io @ 2024-07-10 13:58 UTC (permalink / raw)
To: Leif Lindholm
Cc: devel, Marcin Juszkiewicz, Xiong Yining, Ard Biesheuvel,
Graeme Gregory, Chen Baozi
On Tue, 9 Jul 2024 14:01:53 +0100
"Leif Lindholm" <quic_llindhol@quicinc.com> wrote:
> On Tue, Jul 09, 2024 at 12:47:09 +0200, Marcin Juszkiewicz wrote:
> > During Linaro Connect MAD24 I was asked to move cache information from
> > being 'per cluster' to be 'per core'. This is a move for implementing
> > MPAM support.
> >
> > So topology moves from:
> >
> > Socket -> Clusters -> Cores + Caches -> Threads (if exist)
> >
> > to:
> >
> > Socket -> Clusters -> Cores -> Caches + Threads (if exist)
> >
> > Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
> > implement them at all so we can tell whatever.
They should match the system registers.
CCSIDR etc which are provided by QEMU.
Here's some old code for doing PPTT cache entry generation for arm-virt.
https://lore.kernel.org/qemu-devel/20230808115713.2613-2-Jonathan.Cameron@huawei.com/
The numbers might happen to match what it has for the cpu you are using though.
https://elixir.bootlin.com/qemu/latest/source/target/arm/tcg/cpu64.c#L1051
For n2 that looks to be 64+64+512...
> >
> > Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
>
> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
>
> /
> Leif
>
> > ---
> > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 47 +++++++++++---------
> > 1 file changed, 25 insertions(+), 22 deletions(-)
> >
> > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > index cf0102d11f1f..a7a9664abdcb 100644
> > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > @@ -562,8 +562,8 @@ AddPpttTable (
> > TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
> > CpuTopo.Sockets * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> > CpuTopo.Clusters * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> > - sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
> > CpuTopo.Cores * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> > + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
> > sizeof (UINT32) * 2)));
> >
> > if (CpuTopo.Threads > 1) {
> > @@ -609,10 +609,7 @@ AddPpttTable (
> >
> > ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> > for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) {
> > - L1DCacheIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> > - L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > - L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > - CoreIndex = L2CacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > + CoreIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> >
> > // Add the Cluster PPTT structure
> > EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> > @@ -624,27 +621,15 @@ AddPpttTable (
> > CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
> > New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> >
> > - // Add L1 D Cache structure
> > - L1DCache.CacheId = CacheId++;
> > - CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > - ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> > - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > -
> > - // Add L1 I Cache structure
> > - L1ICache.CacheId = CacheId++;
> > - CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > - ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> > - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > -
> > - // Add L2 Cache structure
> > - L2Cache.CacheId = CacheId++;
> > - CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > -
> > for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
> > UINT32 *PrivateResourcePtr;
> > UINT32 CoreCpuId;
> >
> > + // two UINT32s for PrivateResourcePtr data
> > + L1DCacheIndex = CoreIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
> > + L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > + L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > +
> > if (CpuTopo.Threads == 1) {
> > CoreCpuId = CpuId;
> > } else {
> > @@ -665,6 +650,23 @@ AddPpttTable (
> > PrivateResourcePtr[1] = L1ICacheIndex;
> > New += (2 * sizeof (UINT32));
> >
> > + // Add L1 D Cache structure
> > + L1DCache.CacheId = CacheId++;
> > + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> > + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > +
> > + // Add L1 I Cache structure
> > + L1ICache.CacheId = CacheId++;
> > + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> > + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > +
> > + // Add L2 Cache structure
> > + L2Cache.CacheId = CacheId++;
> > + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > +
> > if (CpuTopo.Threads == 1) {
> > CpuId++;
> > } else {
> > @@ -685,6 +687,7 @@ AddPpttTable (
> > }
> >
> > CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
> > + CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
> > }
> >
> > ClusterIndex = CoreIndex;
> >
> > --
> > 2.45.2
> >
>
>
>
>
>
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* Re: [edk2-devel] [PATCH edk2-platforms v3 4/5] SbsaQemu: provide cache info per core in PPTT
2024-07-10 13:58 ` Jonathan Cameron via groups.io
@ 2024-07-10 14:39 ` Leif Lindholm
0 siblings, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2024-07-10 14:39 UTC (permalink / raw)
To: Jonathan Cameron
Cc: devel, Marcin Juszkiewicz, Xiong Yining, Ard Biesheuvel,
Graeme Gregory, Chen Baozi
On Wed, Jul 10, 2024 at 14:58:52 +0100, Jonathan Cameron wrote:
> On Tue, 9 Jul 2024 14:01:53 +0100
> "Leif Lindholm" <quic_llindhol@quicinc.com> wrote:
>
> > On Tue, Jul 09, 2024 at 12:47:09 +0200, Marcin Juszkiewicz wrote:
> > > During Linaro Connect MAD24 I was asked to move cache information from
> > > being 'per cluster' to be 'per core'. This is a move for implementing
> > > MPAM support.
> > >
> > > So topology moves from:
> > >
> > > Socket -> Clusters -> Cores + Caches -> Threads (if exist)
> > >
> > > to:
> > >
> > > Socket -> Clusters -> Cores -> Caches + Threads (if exist)
> > >
> > > Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
> > > implement them at all so we can tell whatever.
>
> They should match the system registers.
> CCSIDR etc which are provided by QEMU.
That's a good point. Thanks for bringing that up.
edk2-platforms/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPptt.c
demonstrates how this can be done with existing edk2 interfaces and
definitions.
Ultimately, this will only ever be possible to runtime-generate in
edk2 for homogenous systems. Any big-little type setups need to get
the information from TF-A.
/
Leif
> Here's some old code for doing PPTT cache entry generation for arm-virt.
>
> https://lore.kernel.org/qemu-devel/20230808115713.2613-2-Jonathan.Cameron@huawei.com/
>
> The numbers might happen to match what it has for the cpu you are using though.
> https://elixir.bootlin.com/qemu/latest/source/target/arm/tcg/cpu64.c#L1051
>
> For n2 that looks to be 64+64+512...
>
>
>
> > >
> > > Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> >
> > Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
> >
> > /
> > Leif
> >
> > > ---
> > > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 47 +++++++++++---------
> > > 1 file changed, 25 insertions(+), 22 deletions(-)
> > >
> > > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > index cf0102d11f1f..a7a9664abdcb 100644
> > > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > @@ -562,8 +562,8 @@ AddPpttTable (
> > > TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
> > > CpuTopo.Sockets * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> > > CpuTopo.Clusters * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> > > - sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
> > > CpuTopo.Cores * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> > > + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
> > > sizeof (UINT32) * 2)));
> > >
> > > if (CpuTopo.Threads > 1) {
> > > @@ -609,10 +609,7 @@ AddPpttTable (
> > >
> > > ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> > > for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) {
> > > - L1DCacheIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> > > - L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > - L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > - CoreIndex = L2CacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > + CoreIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> > >
> > > // Add the Cluster PPTT structure
> > > EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> > > @@ -624,27 +621,15 @@ AddPpttTable (
> > > CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
> > > New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> > >
> > > - // Add L1 D Cache structure
> > > - L1DCache.CacheId = CacheId++;
> > > - CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > > - ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> > > - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > -
> > > - // Add L1 I Cache structure
> > > - L1ICache.CacheId = CacheId++;
> > > - CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > > - ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> > > - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > -
> > > - // Add L2 Cache structure
> > > - L2Cache.CacheId = CacheId++;
> > > - CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > > - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > -
> > > for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
> > > UINT32 *PrivateResourcePtr;
> > > UINT32 CoreCpuId;
> > >
> > > + // two UINT32s for PrivateResourcePtr data
> > > + L1DCacheIndex = CoreIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
> > > + L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > + L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > +
> > > if (CpuTopo.Threads == 1) {
> > > CoreCpuId = CpuId;
> > > } else {
> > > @@ -665,6 +650,23 @@ AddPpttTable (
> > > PrivateResourcePtr[1] = L1ICacheIndex;
> > > New += (2 * sizeof (UINT32));
> > >
> > > + // Add L1 D Cache structure
> > > + L1DCache.CacheId = CacheId++;
> > > + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > > + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> > > + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > +
> > > + // Add L1 I Cache structure
> > > + L1ICache.CacheId = CacheId++;
> > > + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > > + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
> > > + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > +
> > > + // Add L2 Cache structure
> > > + L2Cache.CacheId = CacheId++;
> > > + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > > + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > +
> > > if (CpuTopo.Threads == 1) {
> > > CpuId++;
> > > } else {
> > > @@ -685,6 +687,7 @@ AddPpttTable (
> > > }
> > >
> > > CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
> > > + CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
> > > }
> > >
> > > ClusterIndex = CoreIndex;
> > >
> > > --
> > > 2.45.2
> > >
> >
> >
> >
> >
> >
>
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^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2024-07-10 14:40 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-07-09 10:47 [edk2-devel] [PATCH edk2-platforms v3 0/5] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 1/5] SbsaQemu: get the information of CPU topology via SMC calls Marcin Juszkiewicz
2024-07-09 12:40 ` Leif Lindholm
[not found] ` <17E08BE30DD079C5.26166@groups.io>
2024-07-09 12:42 ` Leif Lindholm
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 2/5] SbsaQemu: align the PPTT tables with QEMU Marcin Juszkiewicz
2024-07-09 12:43 ` Leif Lindholm
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 3/5] SbsaQemu: update PPTT to ACPI 6.5 Marcin Juszkiewicz
2024-07-09 12:44 ` Leif Lindholm
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 4/5] SbsaQemu: provide cache info per core in PPTT Marcin Juszkiewicz
2024-07-09 13:01 ` Leif Lindholm
2024-07-10 13:58 ` Jonathan Cameron via groups.io
2024-07-10 14:39 ` Leif Lindholm
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 5/5] SbsaQemu: introduce helper in PPTT generation Marcin Juszkiewicz
2024-07-09 13:00 ` Leif Lindholm
2024-07-09 13:12 ` Marcin Juszkiewicz
2024-07-09 13:15 ` Leif Lindholm
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