From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=17.151.62.25; helo=mail-in2.apple.com; envelope-from=afish@apple.com; receiver=edk2-devel@lists.01.org Received: from mail-in2.apple.com (mail-out2.apple.com [17.151.62.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8D36B2095B081 for ; Thu, 5 Oct 2017 09:58:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; d=apple.com; s=mailout2048s; c=relaxed/simple; q=dns/txt; i=@apple.com; t=1507222928; h=From:Sender:Reply-To:Subject:Date:Message-id:To:Cc:MIME-version:Content-type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-reply-to:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=r9h9F/mglMmp1K0pq6GxY8lRuUW/WPZ9fHosnxhvqok=; b=zrFQ965xAVWITU4Lhinn4dMQrjFpvQjtxdR9bzQ+4T/K3xKD4rRDEiIlQjuHH3OW BN3HFYIF3Ee2SqlNrFzoVmii9zs0dmgRv/LgeoX0+JiMxCq9WSCe9ssARMEZu9sn BWIXLHOlPNN+pr3ikYICIUIEcmzbxenvRaxUnNM2jNlzIHBmdsYvRvzrXpKYcGyg 8EBgI6Bn3QZDqDpBaGEuXJ2QEeHREfgfRCBJDXbVwWGI829I7At+wfv6pnsDPn8J ZjzxwsirzqrS4aWdgv5K2xsOd2TxzOtqlSS/E4MiWfNymFCvLfbRKuzoM3NxxYap wcZdUQroGjgwjaKW2osHJQ==; Received: from relay4.apple.com (relay4.apple.com [17.128.113.87]) (using TLS with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mail-in2.apple.com (Apple Secure Mail Relay) with SMTP id DC.9B.28433.F8566D95; Thu, 5 Oct 2017 10:02:07 -0700 (PDT) X-AuditID: 11973e11-c4e0f9c000006f11-df-59d6658f6ae4 Received: from nwk-mmpp-sz11.apple.com (nwk-mmpp-sz11.apple.com [17.128.115.155]) by relay4.apple.com (Apple SCV relay) with SMTP id 49.26.06992.F8566D95; Thu, 5 Oct 2017 10:02:07 -0700 (PDT) MIME-version: 1.0 Received: from [17.114.155.82] by nwk-mmpp-sz11.apple.com (Oracle Communications Messaging Server 8.0.1.3.20170825 64bit (built Aug 25 2017)) with ESMTPSA id <0OXD006TR0NJB820@nwk-mmpp-sz11.apple.com>; Thu, 05 Oct 2017 10:02:07 -0700 (PDT) Sender: afish@apple.com From: Andrew Fish Message-id: <352A9DE5-0BFE-47C5-BAE7-72B469DA39C2@apple.com> Date: Thu, 05 Oct 2017 10:02:08 -0700 In-reply-to: Cc: Ard Biesheuvel , "edk2-devel@lists.01.org" To: Vabhav Sharma References: X-Mailer: Apple Mail (2.3273) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPLMWRmVeSWpSXmKPExsUi2FAYrtufei3S4NJ7G4v/H3YzWuw5dJTZ on/baxYHZo871/aweXTP/sfisfHdDqYA5igum5TUnMyy1CJ9uwSujF2bvjMXzFzBVDF5ZUUD 47Eepi5GTg4JAROJX8+nsXUxcnEICaxmkjj1bStcYtqdHnaIxCFGibfvv7GAJHgFBCV+TL4H ZjMLhEk8fd8BVfSVUeLQvldgCWEBcYl3ZzYxg9hsAsoSK+Z/YIdotpF4vesiG0RNosT0/rWM XYwcHCwCqhLnP1SAhDkFYiUurt/DDDE/VaK1vZEVxBYR0JTomfob6tIHjBKzpnWyQVwqK3Fr 9iVmkISEwBo2iQn3XrNMYBSaheTYWUiOhbC1JL4/agWKcwDZ8hIHz8tChDUlnt37BFWiLfHk 3QXWBYxsqxiFchMzc3Qz84z0EgsKclL1kvNzNzGCYmS6neAOxuOrrA4xCnAwKvHwRjy6EinE mlhWXJl7iFGag0VJnPf9f6CQQHpiSWp2ampBalF8UWlOavEhRiYOTqkGxsI8432Ziy3Sv7xa LiS0Yc3ap74aXPYrTre9fWu3L17jjEJi63EVO7V7mT9rt0/QiX5x/4Puo7PxVVlrD7GfFn9n 33DnqhNzp8PFY4feLZ8cqajwqvj5G3PNLlEXCf1ShU1703dq3piX8f2/ftbmF3YHvu7N3u1U 8L7h2ongGd6phfGzdq7iXKXEUpyRaKjFXFScCABco+nPcgIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrELMWRmVeSWpSXmKPExsUi2FA8W7c/9VqkwZHX5hb/P+xmtNhz6Ciz Rf+21ywOzB53ru1h8+ie/Y/FY+O7HUwBzFFcNimpOZllqUX6dglcGbs2fWcumLmCqWLyyooG xmM9TF2MnBwSAiYS0+70sHcxcnEICRxilHj7/hsLSIJXQFDix+R7YDazQJjE0/cdUEVfGSUO 7XsFlhAWEJd4d2YTM4jNJqAssWL+B3aIZhuJ17suskHUJEpM71/L2MXIwcEioCpx/kMFSJhT IFbi4vo9zBDzUyVa2xtZQWwRAU2Jnqm/2SB2PWCUmDWtkw3iUlmJW7MvMU9g5J+F5L5ZSO6D sLUkvj9qBYpzANnyEgfPy0KENSWe3fsEVaIt8eTdBdYFjGyrGAWKUnMSK030EgsKclL1kvNz NzGCQ7owfAfjv2VWhxgFOBiVeHgjHl2JFGJNLCuuzAUGEgezkgjvpuBrkUK8KYmVValF+fFF pTmpxYcYpTlYlMR57QWAUgLpiSWp2ampBalFMFkmDk6pBsbHwpVS5/bMKy74pnvi8ZmJ059J HP/57GZFxr/ki42VBf6pDKc6uqeHCP09MTP45d2bwu8cztdXtM7kC+ZZee9cT9rEhl9feCrD lwarfW+7sOtvqvPSJjGud46n/vMcu/NlZfABEQMFydqK/s2pIV9bq66wv9slVBbny53x7Zv6 0/fPda8w/ulRYinOSDTUYi4qTgQA7ry1YmUCAAA= X-Content-Filtered-By: Mailman/MimeDel 2.1.22 Subject: Re: Clarification about InitializeCpuExceptionHandlers() and TGE bit in hcr_el2 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Oct 2017 16:58:45 -0000 Content-Type: text/plain; CHARSET=US-ASCII Content-Transfer-Encoding: 7BIT > On Oct 5, 2017, at 9:53 AM, Vabhav Sharma wrote: > > Thanks Andrew Fish, > I understand. > > In PEI Phase, No handlers are installed and there might be pending exception. ExceptionHandlers() can be installed during PEI phase like after initializing the MMU to catch unhandled exception. Please suggest? > Vabhav, It looks like for x86 InitializeCpuExceptionHandlers() is called in SEC and then in CPU PEIM calls InitializeCpuExceptionHandlers(). ~/work/src/edk2(master)>git grep InitializeCpuExceptionHandlers ArmPkg/Drivers/CpuDxe/Exception.c:37: InitializeCpuExceptionHandlers(VectorInfo); ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c:94:InitializeCpuExceptionHandlers( ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c:242:NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c:261: Status = InitializeCpuExceptionHandlers (VectorInfoList); MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h:40:InitializeCpuExceptionHandlers ( MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h:73: NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.c:35:InitializeCpuExceptionHandlers ( MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.c:74: NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/IA32/SetIdtEntry.c:44: Status = InitializeCpuExceptionHandlers (NULL); MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c:155: Status = InitializeCpuExceptionHandlers (NULL); MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c:249: Status = InitializeCpuExceptionHandlers (NULL); UefiCpuPkg/CpuMpPei/CpuMpPei.c:447: Status = InitializeCpuExceptionHandlers (VectorInfo); UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h:158:InitializeCpuExceptionHandlersWorker ( UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c:62:InitializeCpuExceptionHandlers ( UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c:69: return InitializeCpuExceptionHandlersWorker (VectorInfo, &mExceptionHandlerData); UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c:175: NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c:88:InitializeCpuExceptionHandlers ( UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c:105: Status = InitializeCpuExceptionHandlersWorker (VectorInfo, ExceptionHandlerData); UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c:156: NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c:203:InitializeCpuExceptionHandlersWorker ( UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c:64:InitializeCpuExceptionHandlers ( UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c:155: NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c:62:InitializeCpuExceptionHandlers ( UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c:69: return InitializeCpuExceptionHandlersWorker (VectorInfo, &mExceptionHandlerData); UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c:104: NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c:646: Status = InitializeCpuExceptionHandlers (NULL); UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c:157: Status = InitializeCpuExceptionHandlers (NULL); UefiCpuPkg/SecCore/SecMain.c:184: Status = InitializeCpuExceptionHandlers (NULL); At least on x86 the exceptions don't tend to pend, they just happen. So for example an ASSERT() macro can map to an INT 3 (Breakpoint) on x86, you can get GP faults for accessing a non-cononical address, etc. So catching the exception and printing out the PC, and stack trace if possible is very useful for debugging. Thanks, Andrew Fish > > Dear Arm Folks, > I request you to comment on hcr_el2 usage mentioned in below email > I understand that Enabling TGE bit will route the EL1 exception to EL2.Is there any EL1 code during UEFI execution? > > Regards, > Vabhav > > -----Original Message----- > From: afish@apple.com [mailto:afish@apple.com] > Sent: Thursday, September 28, 2017 7:31 PM > To: Vabhav Sharma > Cc: edk2-devel@lists.01.org; edk2-devel > Subject: Re: [edk2] Clarification about InitializeCpuExceptionHandlers() and TGE bit in hcr_el2 > > >> On Sep 28, 2017, at 4:23 AM, Vabhav Sharma wrote: >> >> Hi All, >> >> I see that InitializeCpuExceptionHandlers() is called from DxeMain to take over exception handlers and later from ArmCpuDxe. >> Is there any specific purpose to call it from two places during dxe phase? >> > > Vabhav, > > DxeMain is the DXE Core and that is like (micro) kernel and it is platform agnostic code. InitializeCpuExceptionHandlers() exists in that location to catch unhandled exceptions, especially in the case when no debugger stub is linked in. The CPU Dxe driver abstracts CPU specifics from the DXE Core and it adds supports for interrupts, cachability, etc. and the DXE Core uses services from this driver to abstract CPU implementation. > > To make things even more complex on some platforms PEI and DXE run in entirely different modes. For example on x86 is is common for PEI to be 32-bit and and DXE to be 64-bit. This is mostly due to how complex it is to turn on memory, and the fact that there is no good place to put the page tables prior to memory init. > > I'll let the ARM folks comment on hcr_el2 usage. > > Thanks, > > Andrew Fish > >> Additionally we are setting TGE bit three times in hcr_el2 during PrePei phase(ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c) >> and Twice in Dxe phase: dxemain(),ArmCpuDxe >> >> Please help to clarify or required to be fixed? >> >> Regards, >> Vabhav >> _______________________________________________ >> edk2-devel mailing list >> edk2-devel@lists.01.org >> https://lists.01.org/mailman/listinfo/edk2-devel > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel