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charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: quoted-printable On 11/29/21 1:04 PM, Tom Lendacky wrote: > On 11/25/21 7:12 AM, qi zhou wrote: >> =C2=A0From 5b10265fa5c7b5ca728b4f18488089de6535ed28 Mon Sep 17 00:00:00 = 2001 >> From: Qi Zhou >> Date: Thu, 25 Nov 2021 20:25:55 +0800 >> Subject: [PATCH] OvmfPkg/MemEncryptSevLib: check CPUID when read msr=20 >> during >> =C2=A0 PEI phase >> >> Tested on Intel Platform, It is like 'SEV-ES work area' can be=20 >> modified by >> os(Windows etc), and will not restored on reboot, the >> SevEsWorkArea->EncryptionMask may have a random value after reboot.=20 >> then it >> may casue fail on reboot. The msr bits already cached by=20 >> mSevStatusChecked, >> there is no need to try cache again in PEI phase. >> >> Signed-off-by: Qi Zhou >> --- >> =C2=A0 .../PeiMemEncryptSevLibInternal.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 55 +++++++------------ >> =C2=A0 1 file changed, 19 insertions(+), 36 deletions(-) >> >> diff --git=20 >> a/OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLibInternal.c=20 >> b/OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLibInternal.c >> index e2fd109d12..0819f50669 100644 >> --- a/OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLibInternal.c >> +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLibInternal.c >> @@ -38,49 +38,32 @@ InternalMemEncryptSevStatus ( >> =C2=A0=C2=A0=C2=A0 UINT32=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 RegEax; >> =C2=A0=C2=A0=C2=A0 MSR_SEV_STATUS_REGISTER=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Msr; >> =C2=A0=C2=A0=C2=A0 CPUID_MEMORY_ENCRYPTION_INFO_EAX=C2=A0 Eax; >> -=C2=A0 BOOLEAN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 ReadSevMsr; >> -=C2=A0 SEC_SEV_ES_WORK_AREA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *SevEsWorkArea; >> -=C2=A0 ReadSevMsr =3D FALSE; >> - >> -=C2=A0 SevEsWorkArea =3D (SEC_SEV_ES_WORK_AREA *) FixedPcdGet32=20 >> (PcdSevEsWorkAreaBase); >> -=C2=A0 if (SevEsWorkArea !=3D NULL && SevEsWorkArea->EncryptionMask != =3D 0) { >> -=C2=A0=C2=A0=C2=A0 // >> -=C2=A0=C2=A0=C2=A0 // The MSR has been read before, so it is safe to re= ad it again=20 >> and avoid >> -=C2=A0=C2=A0=C2=A0 // having to validate the CPUID information. >> +=C2=A0 // >> +=C2=A0 // Check if memory encryption leaf exist >> +=C2=A0 // >> +=C2=A0 AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); >> +=C2=A0 if (RegEax >=3D CPUID_MEMORY_ENCRYPTION_INFO) { >=20 What is missing in the original patch set is that now with the common=20 work area we need to check the Guest Type before accessing the SevEs=20 workarea type. I have a patch in my wip to cleanup the SEV feature=20 detection check and patiently waiting for the SEV-SNP series to land so=20 that I can submit other patches. You need something like IsSevGuest() before accessing the SevEs=20 workarea, see how its done for the SEC. https://github.com/AMDESE/ovmf/blob/snp-v13/OvmfPkg/Sec/AmdSev.c#L234 In my WIP I am moving that to common BaseMemEncryptLib. thanks > This now defeats the purpose of the workarea the already validated CPUID= =20 > information. This CPUID information will now require validating. >=20 > Wouldn't the best thing be to clear the workarea in the early boot code? >=20 > Thanks, > Tom >=20 >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // >> -=C2=A0=C2=A0=C2=A0 ReadSevMsr =3D TRUE; >> -=C2=A0 } else { >> +=C2=A0=C2=A0=C2=A0 // CPUID Fn8000_001F[EAX] Bit 1 (Sev supported) >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // >> -=C2=A0=C2=A0=C2=A0 // Check if memory encryption leaf exist >> -=C2=A0=C2=A0=C2=A0 // >> -=C2=A0=C2=A0=C2=A0 AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NU= LL, NULL); >> -=C2=A0=C2=A0=C2=A0 if (RegEax >=3D CPUID_MEMORY_ENCRYPTION_INFO) { >> +=C2=A0=C2=A0=C2=A0 AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax.Uint32,= NULL, NULL,=20 >> NULL); >> + >> +=C2=A0=C2=A0=C2=A0 if (Eax.Bits.SevBit) { >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // >> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // CPUID Fn8000_001F[EAX] Bit 1 (Sev sup= ported) >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // Check MSR_0xC0010131 Bit 0 (Sev Enabl= ed) >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // >> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, = &Eax.Uint32, NULL,=20 >> NULL, NULL); >> - >> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (Eax.Bits.SevBit) { >> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ReadSevMsr =3D TRUE; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Msr.Uint32 =3D AsmReadMsr32 (MSR_SEV_STA= TUS); >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (Msr.Bits.SevBit) { >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 mSevStatus =3D TRUE; >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >> -=C2=A0=C2=A0=C2=A0 } >> -=C2=A0 } >> - >> -=C2=A0 if (ReadSevMsr) { >> -=C2=A0=C2=A0=C2=A0 // >> -=C2=A0=C2=A0=C2=A0 // Check MSR_0xC0010131 Bit 0 (Sev Enabled) >> -=C2=A0=C2=A0=C2=A0 // >> -=C2=A0=C2=A0=C2=A0 Msr.Uint32 =3D AsmReadMsr32 (MSR_SEV_STATUS); >> -=C2=A0=C2=A0=C2=A0 if (Msr.Bits.SevBit) { >> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 mSevStatus =3D TRUE; >> -=C2=A0=C2=A0=C2=A0 } >> -=C2=A0=C2=A0=C2=A0 // >> -=C2=A0=C2=A0=C2=A0 // Check MSR_0xC0010131 Bit 1 (Sev-Es Enabled) >> -=C2=A0=C2=A0=C2=A0 // >> -=C2=A0=C2=A0=C2=A0 if (Msr.Bits.SevEsBit) { >> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 mSevEsStatus =3D TRUE; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // Check MSR_0xC0010131 Bit 1 (Sev-Es En= abled) >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (Msr.Bits.SevEsBit) { >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 mSevEsStatus =3D TRUE; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >> =C2=A0=C2=A0=C2=A0 } >>