From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web08.1215.1648597728598639731 for ; Tue, 29 Mar 2022 16:48:55 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=dwZTyR5y; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: min.m.xu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648597735; x=1680133735; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=19gEunltqWOCwD6BeTZvzibVagh7Z3ILylhBOKPPuro=; b=dwZTyR5yFvCtq8mOncRWlTW+CRQkZeoazIJ32Iv9oeeDiqQ17YGgp2O+ s5OzO0QVhBrLp/2JrWgzylLsdI7ujQPkK9X4Ow2lMSLINHBGjiZOux4O2 +REYQ7CkxVbYyL6Uw+90ILtXC4eFMunME7hxiL/6P8iPY163ZwXv2odwC ffFzkMeMDJXHe/tfSITvd4OJZ6jlt/wkuhlsjExp/9MUQ9Tm7rzvQrszw +tSciWthBFpAD0DQEwOLnbIlMi1bjVDKqiUk4fdKjx2REEAlpoc6NsANP 8Ds0+7A3reI2fuAjZNTOFtA4A0zKuQ3yqsgD9EM7o3weecnruWFvcmgXT Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10301"; a="259375721" X-IronPort-AV: E=Sophos;i="5.90,220,1643702400"; d="scan'208";a="259375721" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2022 16:48:55 -0700 X-IronPort-AV: E=Sophos;i="5.90,220,1643702400"; d="scan'208";a="521659292" Received: from zhangpen-mobl.ccr.corp.intel.com (HELO mxu9-mobl1.ccr.corp.intel.com) ([10.255.29.230]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2022 16:48:52 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [PATCH V12 38/47] OvmfPkg: Update PlatformInitLib for Tdx guest Date: Wed, 30 Mar 2022 07:46:31 +0800 Message-Id: <37d99c325e67b7d995a3c7db47b0e42b4432440b.1648555175.git.min.m.xu@intel.com> X-Mailer: git-send-email 2.29.2.windows.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 There are below changes in PlatformInitLib for Tdx guest: 1. Publish ram regions In Tdx guest, the system memory is passed in TdHob by host VMM. So the major task of PlatformTdxPublishRamRegions is to walk thru the TdHob list and transfer the ResourceDescriptorHob and MemoryAllocationHob to the hobs in DXE phase. 2. Build MemoryAllocationHob for Tdx Mailbox and Ovmf work area. 3. Update of PlatformAddressWidthInitialization. The physical address width that Tdx guest supports is either 48 or 52. 4. Update of PlatformMemMapInitialization. 0xA0000 - 0xFFFFF is VGA bios region. Platform initialization marks the region as MMIO region. Dxe code maps MMIO region as IO region. As TDX guest, MMIO region is maps as shared. However VGA BIOS doesn't need to be shared. Guest TDX Linux maps VGA BIOS as private and accesses for BIOS and stuck on repeating EPT violation. VGA BIOS (more generally ROM region) should be private. Skip marking VGA BIOA region [0xa000, 0xfffff] as MMIO in HOB. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/Include/Library/PlatformInitLib.h | 14 ++++++ OvmfPkg/Library/PlatformInitLib/IntelTdx.c | 49 +++++++++++++++++++ .../Library/PlatformInitLib/IntelTdxNull.c | 16 ++++++ OvmfPkg/Library/PlatformInitLib/MemDetect.c | 14 ++++++ OvmfPkg/Library/PlatformInitLib/Platform.c | 4 +- 5 files changed, 96 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Library/PlatformInitLib.h index 6152a43d0da7..2987a367cc9c 100644 --- a/OvmfPkg/Include/Library/PlatformInitLib.h +++ b/OvmfPkg/Include/Library/PlatformInitLib.h @@ -220,4 +220,18 @@ ProcessTdxHobList ( VOID ); +/** + In Tdx guest, the system memory is passed in TdHob by host VMM. So + the major task of PlatformTdxPublishRamRegions is to walk thru the + TdHob list and transfer the ResourceDescriptorHob and MemoryAllocationHob + to the hobs in DXE phase. + + MemoryAllocationHob should also be created for Mailbox and Ovmf work area. +**/ +VOID +EFIAPI +PlatformTdxPublishRamRegions ( + VOID + ); + #endif // PLATFORM_INIT_LIB_H_ diff --git a/OvmfPkg/Library/PlatformInitLib/IntelTdx.c b/OvmfPkg/Library/PlatformInitLib/IntelTdx.c index e9196b7ffaa7..c6d7c8bb6e0e 100644 --- a/OvmfPkg/Library/PlatformInitLib/IntelTdx.c +++ b/OvmfPkg/Library/PlatformInitLib/IntelTdx.c @@ -512,3 +512,52 @@ TransferTdxHobList ( Hob.Raw = GET_NEXT_HOB (Hob); } } + +/** + In Tdx guest, the system memory is passed in TdHob by host VMM. So + the major task of PlatformTdxPublishRamRegions is to walk thru the + TdHob list and transfer the ResourceDescriptorHob and MemoryAllocationHob + to the hobs in DXE phase. + + MemoryAllocationHob should also be created for Mailbox and Ovmf work area. +**/ +VOID +EFIAPI +PlatformTdxPublishRamRegions ( + VOID + ) +{ + if (!TdIsEnabled ()) { + return; + } + + TransferTdxHobList (); + + // + // The memory region defined by PcdOvmfSecGhcbBackupBase is pre-allocated by + // host VMM and used as the td mailbox at the beginning of system boot. + // + BuildMemoryAllocationHob ( + FixedPcdGet32 (PcdOvmfSecGhcbBackupBase), + FixedPcdGet32 (PcdOvmfSecGhcbBackupSize), + EfiACPIMemoryNVS + ); + + if (FixedPcdGet32 (PcdOvmfWorkAreaSize) != 0) { + // + // Reserve the work area. + // + // Since this memory range will be used by the Reset Vector on S3 + // resume, it must be reserved as ACPI NVS. + // + // If S3 is unsupported, then various drivers might still write to the + // work area. We ought to prevent DXE from serving allocation requests + // such that they would overlap the work area. + // + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase), + (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize), + EfiBootServicesData + ); + } +} diff --git a/OvmfPkg/Library/PlatformInitLib/IntelTdxNull.c b/OvmfPkg/Library/PlatformInitLib/IntelTdxNull.c index af90e0866e89..3ebe582af8de 100644 --- a/OvmfPkg/Library/PlatformInitLib/IntelTdxNull.c +++ b/OvmfPkg/Library/PlatformInitLib/IntelTdxNull.c @@ -28,3 +28,19 @@ ProcessTdxHobList ( { return EFI_UNSUPPORTED; } + +/** + In Tdx guest, the system memory is passed in TdHob by host VMM. So + the major task of PlatformTdxPublishRamRegions is to walk thru the + TdHob list and transfer the ResourceDescriptorHob and MemoryAllocationHob + to the hobs in DXE phase. + + MemoryAllocationHob should also be created for Mailbox and Ovmf work area. +**/ +VOID +EFIAPI +PlatformTdxPublishRamRegions ( + VOID + ) +{ +} diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/PlatformInitLib/MemDetect.c index 911c0906cb3d..4c1dedf863c3 100644 --- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c @@ -37,6 +37,8 @@ Module Name: #include #include #include +#include + #include VOID @@ -528,7 +530,19 @@ PlatformAddressWidthInitialization ( PhysMemAddressWidth = 36; } + #if defined (MDE_CPU_X64) + if (TdIsEnabled ()) { + if (TdSharedPageMask () == (1ULL << 47)) { + PhysMemAddressWidth = 48; + } else { + PhysMemAddressWidth = 52; + } + } + + ASSERT (PhysMemAddressWidth <= 52); + #else ASSERT (PhysMemAddressWidth <= 48); + #endif PlatformInfoHob->FirstNonAddress = FirstNonAddress; PlatformInfoHob->PhysMemAddressWidth = PhysMemAddressWidth; diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/PlatformInitLib/Platform.c index c4fa7d445394..101074f6100d 100644 --- a/OvmfPkg/Library/PlatformInitLib/Platform.c +++ b/OvmfPkg/Library/PlatformInitLib/Platform.c @@ -136,7 +136,9 @@ PlatformMemMapInitialization ( // // Video memory + Legacy BIOS region // - PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB); + if (!TdIsEnabled ()) { + PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB); + } if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) { PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); -- 2.29.2.windows.2