From: "Ashish Singhal" <ashishsingha@nvidia.com>
To: <devel@edk2.groups.io>, <ard.biesheuvel@linaro.org>, <leif@nuviainc.com>
Cc: Ashish Singhal <ashishsingha@nvidia.com>
Subject: [PATCH] ArmPkg/ArmLib: Fix cache-invalidate initial page tables
Date: Thu, 19 Mar 2020 10:37:05 -0600 [thread overview]
Message-ID: <388539fc2f778e417d632f24e20e54c82e0d80a4.1584635658.git.ashishsingha@nvidia.com> (raw)
Because of a bug, current EL gets passed to DC IVAC instruction instead
of the VA entry that needs to be invalidated.
Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
---
ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
index f744cd6..ba0ec56 100644
--- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
@@ -122,7 +122,7 @@ ASM_FUNC(ArmSetMAIR)
ASM_FUNC(ArmUpdateTranslationTableEntry)
dsb nshst
lsr x1, x1, #12
- EL1_OR_EL2_OR_EL3(x0)
+ EL1_OR_EL2_OR_EL3(x2)
1: tlbi vaae1, x1 // TLB Invalidate VA , EL1
mrs x2, sctlr_el1
b 4f
--
2.7.4
next reply other threads:[~2020-03-19 16:37 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-19 16:37 Ashish Singhal [this message]
2020-03-19 17:39 ` [PATCH] ArmPkg/ArmLib: Fix cache-invalidate initial page tables Leif Lindholm
-- strict thread matches above, loose matches on Subject: below --
2020-03-18 18:45 Name
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