[PATCH] ArmPkg/ArmLib: Fix cache-invalidate initial page tables

[PATCH] ArmPkg/ArmLib: Fix cache-invalidate initial page tables

[Name]

From: Ashish Singhal <ashishsingha@nvidia.com>

Because of a bug, current EL gets passed to DC IVAC instruction instead
of the VA entry that needs to be invalidated.

Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
---
 ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
index f744cd6..ba0ec56 100644
--- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
@@ -122,7 +122,7 @@ ASM_FUNC(ArmSetMAIR)
 ASM_FUNC(ArmUpdateTranslationTableEntry)
    dsb     nshst
    lsr     x1, x1, #12
-   EL1_OR_EL2_OR_EL3(x0)
+   EL1_OR_EL2_OR_EL3(x2)
 1: tlbi    vaae1, x1             // TLB Invalidate VA , EL1
    mrs     x2, sctlr_el1
    b       4f
-- 
2.7.4


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[PATCH] ArmPkg/ArmLib: Fix cache-invalidate initial page tables

[Ashish Singhal]

Because of a bug, current EL gets passed to DC IVAC instruction instead
of the VA entry that needs to be invalidated.

Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
---
 ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
index f744cd6..ba0ec56 100644
--- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
@@ -122,7 +122,7 @@ ASM_FUNC(ArmSetMAIR)
 ASM_FUNC(ArmUpdateTranslationTableEntry)
    dsb     nshst
    lsr     x1, x1, #12
-   EL1_OR_EL2_OR_EL3(x0)
+   EL1_OR_EL2_OR_EL3(x2)
 1: tlbi    vaae1, x1             // TLB Invalidate VA , EL1
    mrs     x2, sctlr_el1
    b       4f
-- 
2.7.4

Re: [PATCH] ArmPkg/ArmLib: Fix cache-invalidate initial page tables

[Leif Lindholm]

On Thu, Mar 19, 2020 at 10:37:05 -0600, Ashish Singhal wrote:
> Because of a bug, current EL gets passed to DC IVAC instruction instead
> of the VA entry that needs to be invalidated.

Oh, yeah, that's obviously a bug. What idiot reviewed that patch? Oh,
me...

OK, so I should have added a reference to the bad commit before
pushing, but by the time I remembered, the CI job had already merged
the patch.

So for the record, the offending commit was 3391e20ffa3f
("ArmPkg/ArmMmuLib AARCH64: cache-invalidate initial page table entries")

Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Pushed as 0c8ea9fe1adb.

Thanks!

> Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
> ---
>  ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
> index f744cd6..ba0ec56 100644
> --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
> +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
> @@ -122,7 +122,7 @@ ASM_FUNC(ArmSetMAIR)
>  ASM_FUNC(ArmUpdateTranslationTableEntry)
>     dsb     nshst
>     lsr     x1, x1, #12
> -   EL1_OR_EL2_OR_EL3(x0)
> +   EL1_OR_EL2_OR_EL3(x2)
>  1: tlbi    vaae1, x1             // TLB Invalidate VA , EL1
>     mrs     x2, sctlr_el1
>     b       4f
> -- 
> 2.7.4
>