From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from hqnvemgate25.nvidia.com (hqnvemgate25.nvidia.com [216.228.121.64]) by mx.groups.io with SMTP id smtpd.web10.2431.1584635840093468092 for ; Thu, 19 Mar 2020 09:37:20 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nvidia.com header.s=n1 header.b=JXv+ruGA; spf=pass (domain: nvidia.com, ip: 216.228.121.64, mailfrom: ashishsingha@nvidia.com) Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 19 Mar 2020 09:36:29 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 19 Mar 2020 09:37:19 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 19 Mar 2020 09:37:19 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 19 Mar 2020 16:37:19 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 19 Mar 2020 16:37:19 +0000 Received: from ashishsingha-lnx.nvidia.com (Not Verified[10.28.48.147]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 19 Mar 2020 09:37:19 -0700 From: "Ashish Singhal" To: , , CC: Ashish Singhal Subject: [PATCH] ArmPkg/ArmLib: Fix cache-invalidate initial page tables Date: Thu, 19 Mar 2020 10:37:05 -0600 Message-ID: <388539fc2f778e417d632f24e20e54c82e0d80a4.1584635658.git.ashishsingha@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public Return-Path: ashishsingha@nvidia.com MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584635789; bh=nmfAlZaoCBPwhDKfWyRkM+Doy3zDTVl+J1tAlMCbGvU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=JXv+ruGAygbI9gxAqcThAGjnq7NXgP6thfWMAsjO7pqWj7g4FOJqZcORIWUDq53yD Zknx1x6WQ+zVeROpQT7nspRZWnpXPhv34Znd3Zk2xGjw8Z60wOuRxKf3pNWGaRHLRi fFykyxp6ssnQKDx4XXqwLWOQcdL0n0j798LFrryhAFd1ijxmmlZQNYK9rhME6TnrZy Ry9o9vGauU2sh37aHU0v9bT1vkR0nUCsjdMZYGiPhHemfIiiPjWPLILgEZeXw3J3gO POLDwxbLqdeqkb7R6I7ybZipexVDLaROWyaFCsUW37Bdkv0yYX5ran7smGgRB3vcPP 4v/p8d/T969Zw== Content-Type: text/plain Because of a bug, current EL gets passed to DC IVAC instruction instead of the VA entry that needs to be invalidated. Signed-off-by: Ashish Singhal --- ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S index f744cd6..ba0ec56 100644 --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S @@ -122,7 +122,7 @@ ASM_FUNC(ArmSetMAIR) ASM_FUNC(ArmUpdateTranslationTableEntry) dsb nshst lsr x1, x1, #12 - EL1_OR_EL2_OR_EL3(x0) + EL1_OR_EL2_OR_EL3(x2) 1: tlbi vaae1, x1 // TLB Invalidate VA , EL1 mrs x2, sctlr_el1 b 4f -- 2.7.4