From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.88; helo=mga01.intel.com; envelope-from=dandan.bi@intel.com; receiver=edk2-devel@lists.01.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2E2EE21CB87AD for ; Sun, 24 Dec 2017 17:57:06 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Dec 2017 18:01:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,452,1508828400"; d="scan'208";a="5472492" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga006.jf.intel.com with ESMTP; 24 Dec 2017 18:01:58 -0800 Received: from fmsmsx124.amr.corp.intel.com (10.18.125.39) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 24 Dec 2017 18:01:57 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx124.amr.corp.intel.com (10.18.125.39) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 24 Dec 2017 18:01:57 -0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.213]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.93]) with mapi id 14.03.0319.002; Mon, 25 Dec 2017 10:01:55 +0800 From: "Bi, Dandan" To: "Wang, Jian J" , "edk2-devel@lists.01.org" CC: "Dong, Eric" , Laszlo Ersek Thread-Topic: [PATCH 4/4] UefiCpuPkg: Update code to use new structure field names Thread-Index: AQHTfRywda8gmNDTcUG7EiEUY6mxraNTTmug Date: Mon, 25 Dec 2017 02:01:55 +0000 Message-ID: <3C0D5C461C9E904E8F62152F6274C0BB3B9F0554@SHSMSX103.ccr.corp.intel.com> References: <20171225010659.13428-1-jian.j.wang@intel.com> <20171225010659.13428-5-jian.j.wang@intel.com> In-Reply-To: <20171225010659.13428-5-jian.j.wang@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 4/4] UefiCpuPkg: Update code to use new structure field names X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Dec 2017 01:57:06 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Dandan Bi Thanks, Dandan -----Original Message----- From: Wang, Jian J=20 Sent: Monday, December 25, 2017 9:07 AM To: edk2-devel@lists.01.org Cc: Bi, Dandan ; Dong, Eric ; Las= zlo Ersek Subject: [PATCH 4/4] UefiCpuPkg: Update code to use new structure field nam= es Due to coding style fix of the structure definition in BaseLib.h, all code = referencing those structure must be updated accordingly. Cc: Dandan Bi Cc: Eric Dong Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang --- .../Ia32/ArchExceptionHandler.c | 24 +++++++++++-------= ---- .../X64/ArchExceptionHandler.c | 6 +++--- UefiCpuPkg/Library/MpInitLib/MpLib.c | 2 +- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHa= ndler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandl= er.c index 6ac8549839..4e89b0470f 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandle +++ r.c @@ -216,7 +216,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow =3D (UINT16)TssBase; TssDesc->Bits.BaseMid =3D (UINT8)(TssBase >> 16); TssDesc->Bits.Type =3D IA32_GDT_TYPE_TSS; - TssDesc->Bits.P =3D 1; + TssDesc->Bits.Present =3D 1; TssDesc->Bits.LimitHigh =3D 0; TssDesc->Bits.BaseHigh =3D (UINT8)(TssBase >> 24); =20 @@ -240,7 +240,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow =3D (UINT16)TssBase; TssDesc->Bits.BaseMid =3D (UINT8)(TssBase >> 16); TssDesc->Bits.Type =3D IA32_GDT_TYPE_TSS; - TssDesc->Bits.P =3D 1; + TssDesc->Bits.Present =3D 1; TssDesc->Bits.LimitHigh =3D 0; TssDesc->Bits.BaseHigh =3D (UINT8)(TssBase >> 24); =20 @@ -253,17 +253,17 @@ ArchSetupExcpetionStack ( continue; } =20 - Tss->EIP =3D (UINT32)(TemplateMap.ExceptionStart + Tss->Eip =3D (UINT32)(TemplateMap.ExceptionStart + Vector * TemplateMap.ExceptionStubHeaderSize)= ; - Tss->EFLAGS =3D 0x2; - Tss->ESP =3D StackTop; - Tss->CR3 =3D AsmReadCr3 (); - Tss->ES =3D AsmReadEs (); - Tss->CS =3D AsmReadCs (); - Tss->SS =3D AsmReadSs (); - Tss->DS =3D AsmReadDs (); - Tss->FS =3D AsmReadFs (); - Tss->GS =3D AsmReadGs (); + Tss->Eflags =3D 0x2; + Tss->Esp =3D StackTop; + Tss->Cr3 =3D AsmReadCr3 (); + Tss->Es =3D AsmReadEs (); + Tss->Cs =3D AsmReadCs (); + Tss->Ss =3D AsmReadSs (); + Tss->Ds =3D AsmReadDs (); + Tss->Fs =3D AsmReadFs (); + Tss->Gs =3D AsmReadGs (); =20 StackTop -=3D StackSwitchData->Ia32.KnownGoodStackSize; =20 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHan= dler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler= .c index 1dcf4277de..4d52b4eb0e 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler +++ .c @@ -186,7 +186,7 @@ ArchSetupExcpetionStack ( // TssDesc =3D StackSwitchData->X64.ExceptionTssDesc; Tss =3D StackSwitchData->X64.ExceptionTss; - if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->I= ST)) { + if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE=20 + (Tss->Ist)) { return EFI_INVALID_PARAMETER; } =20 @@ -221,7 +221,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow =3D (UINT16)TssBase; TssDesc->Bits.BaseMidl =3D (UINT8)(TssBase >> 16); TssDesc->Bits.Type =3D IA32_GDT_TYPE_TSS; - TssDesc->Bits.P =3D 1; + TssDesc->Bits.Present =3D 1; TssDesc->Bits.LimitHigh =3D 0; TssDesc->Bits.BaseMidh =3D (UINT8)(TssBase >> 24); TssDesc->Bits.BaseHigh =3D (UINT32)(TssBase >> 32); @@ -236,7 +236,7 @@ ArchSetupExcpetionStack ( // // Fixup IST // - Tss->IST[Index] =3D StackTop; + Tss->Ist[Index] =3D StackTop; StackTop -=3D StackSwitchData->X64.KnownGoodStackSize; =20 // diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 0c2058a7b0..da1a43c430 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -243,7 +243,7 @@ RestoreVolatileRegisters ( VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) { Tss =3D (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base + VolatileRegisters->Tr); - if (Tss->Bits.P =3D=3D 1) { + if (Tss->Bits.Present =3D=3D 1) { Tss->Bits.Type &=3D 0xD; // 1101 - Clear busy bit just in case AsmWriteTr (VolatileRegisters->Tr); } -- 2.15.1.windows.2