From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.12233.1587912249267738009 for ; Sun, 26 Apr 2020 07:44:09 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: dandan.bi@intel.com) IronPort-SDR: nHKDhmRgzH9GP5/0Vd+Eel/bGJ3ZS0E2Mn6f4iHS9cSGPXHxjteAjAIaamyV5Hv7iFuDfbpXLA 3/A2Mgr73rOA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2020 07:44:08 -0700 IronPort-SDR: szXLo56l5jzFiXD83+yaJkGSCpSsFCdukhxorrcf/gClLd1pB0BM5LYZLpViPnb3/LM2r40sxV tOgP50OOc+vg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,320,1583222400"; d="scan'208";a="256966039" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga003.jf.intel.com with ESMTP; 26 Apr 2020 07:44:07 -0700 Received: from fmsmsx116.amr.corp.intel.com (10.18.116.20) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 26 Apr 2020 07:44:07 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx116.amr.corp.intel.com (10.18.116.20) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 26 Apr 2020 07:44:07 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.225]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.146]) with mapi id 14.03.0439.000; Sun, 26 Apr 2020 22:44:04 +0800 From: "Dandan Bi" To: "devel@edk2.groups.io" , "abner.chang@hpe.com" CC: Gilbert Chen , Leif Lindholm , "Gao, Liming" Subject: Re: [edk2-devel] [PATCH v1 3/3] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Thread-Topic: [edk2-devel] [PATCH v1 3/3] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Thread-Index: AQHWDw6ZymspCyaIOUihsr44qrUTzqiLi9Lw Date: Sun, 26 Apr 2020 14:44:03 +0000 Message-ID: <3C0D5C461C9E904E8F62152F6274C0BB40DD59D0@SHSMSX104.ccr.corp.intel.com> References: <20200410072555.7444-1-abner.chang@hpe.com> <20200410072555.7444-4-abner.chang@hpe.com> In-Reply-To: <20200410072555.7444-4-abner.chang@hpe.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: dandan.bi@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Abner, 1. What's following definition for? It seems not be used. typedef VOID* (EFIAPI *DXEENTRYPOINT) ( IN VOID *HobStart ); 2. When reviewing this patch, found the RSIC-V switchstack related code are= not in BaseLib in MdePkg. But then noticed that you have covered them in another patch set. So here I may suggest that maybe you can make the patches which have depend= ency in one patch set and then CC all reviewers, then it can avoid such con= fusion and also can make the patches submit in right dependency order. Since now these patches are in different patch series, please pay attention= to the submit order to avoid any build break in this way. Thanks, Dandan > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Abner Chang > Sent: Friday, April 10, 2020 3:26 PM > To: devel@edk2.groups.io > Cc: abner.chang@hpe.com; Gilbert Chen ; Leif > Lindholm ; Bi, Dandan ; > Gao, Liming > Subject: [edk2-devel] [PATCH v1 3/3] MdeModulePkg/DxeIplPeim : RISC-V > platform level DxeIPL >=20 > Implementation of RISC-V DxeIPL. >=20 > Signed-off-by: Abner Chang > Co-authored-by: Gilbert Chen > Reviewed-by: Leif Lindholm >=20 > Cc: Dandan Bi > Cc: Liming Gao > Cc: Leif Lindholm > Cc: Gilbert Chen > --- > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 6 +- > .../Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 80 +++++++++++++++++++ > 2 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 > MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c >=20 > diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > index 98bc17fc9d..3f17028546 100644 > --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > @@ -7,6 +7,7 @@ > # # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<= BR> # > Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Copyrig= ht > (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.=
> # # SPDX-License-Identifier: BSD-2-Clause-Patent #@@ -25,7 +26,7 @@ > # # The following information is for reference only and not required by = the > build tools. #-# VALID_ARCHITECTURES =3D IA32 X64 EBC (EBC is = for build > only) AARCH64+# VALID_ARCHITECTURES =3D IA32 X64 EBC (EBC is f= or > build only) AARCH64 RISCV64 # [Sources]@@ -49,6 +50,9 @@ > [Sources.ARM, Sources.AARCH64] Arm/DxeLoadFunc.c > +[Sources.RISCV64]+ RiscV64/DxeLoadFunc.c+ [Packages] > MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.decdiff --git > a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c > b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c > new file mode 100644 > index 0000000000..051d11de25 > --- /dev/null > +++ b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c > @@ -0,0 +1,80 @@ > +/** @file+ RISC-V specific functionality for DxeLoad.++ Copyright (c) = 2020, > Hewlett Packard Enterprise Development LP. All rights reserved.
++ > SPDX-License-Identifier: BSD-2-Clause-Patent++**/++#include > "DxeIpl.h"++typedef+VOID*+(EFIAPI *DXEENTRYPOINT) (+ IN VOID > *HobStart+ );++/**+ Transfers control to DxeCore.++ This function > performs a CPU architecture specific operations to execute+ the entry p= oint > of DxeCore with the parameters of HobList.+ It also installs > EFI_END_OF_PEI_PPI to signal the end of PEI phase.++ @param > DxeCoreEntryPoint The entry point of DxeCore.+ @param HobList > The start of HobList passed to DxeCore.++**/+VOID+HandOffToDxeCore (+ > IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,+ IN > EFI_PEI_HOB_POINTERS HobList+ )+{+ VOID *B= aseOfStack;+ > VOID *TopOfStack;+ EFI_STATUS = Status;+ //+ //+ > // Allocate 128KB for the Stack+ //+ BaseOfStack =3D AllocatePages > (EFI_SIZE_TO_PAGES (STACK_SIZE));+ if (BaseOfStack =3D=3D NULL) {+ > DEBUG((DEBUG_ERROR, "%a: Can't allocate memory for stack.", > __FUNCTION__));+ ASSERT(FALSE);+ }++ //+ // Compute the top of the > stack we were allocated. Pre-allocate a UINTN+ // for safety.+ //+ > TopOfStack =3D (VOID *)((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES > (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);+ TopOfStack =3D > ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);++ //+ // End of > PEI phase signal+ //+ Status =3D PeiServicesInstallPpi (&gEndOfPeiSigna= lPpi);+ > if (EFI_ERROR (Status)) {+ DEBUG((DEBUG_ERROR, "%a: Fail to signal End= of > PEI event.", __FUNCTION__));+ ASSERT(FALSE);+ }+ //+ // Update the > contents of BSP stack HOB to reflect the real stack info passed to DxeCor= e.+ > //+ UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack, > STACK_SIZE);++ DEBUG ((DEBUG_INFO, "DXE Core new stack at %x, stack > pointer at %x\n", BaseOfStack, TopOfStack));++ //+ // Transfer the cont= rol > to the entry point of DxeCore.+ //+ SwitchStack (+ > (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,+ > HobList.Raw,+ NULL,+ TopOfStack+ );+}+-- > 2.25.0 >=20 >=20 > -=3D-=3D-=3D-=3D-=3D-=3D > Groups.io Links: You receive all messages sent to this group. >=20 > View/Reply Online (#57204): https://edk2.groups.io/g/devel/message/57204 > Mute This Topic: https://groups.io/mt/72916401/1768738 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [dandan.bi@intel.com] > -=3D-=3D-=3D-=3D-=3D-=3D