From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web12.1951.1588160743239207800 for ; Wed, 29 Apr 2020 04:45:43 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: dandan.bi@intel.com) IronPort-SDR: wiqcKqFXQTH0eNNiFlNLIgu2YnMm2e5KQct++TKrvAztDjOFLhfIzUJ80k8kcYqDJCDY2Xaa6c io6zJ+XivxCA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2020 04:45:41 -0700 IronPort-SDR: FnK9aemB3lN+32fcxUwzy7ieeBPCEzXZNMNDQuhthPtawuAJK0sMcdzer9D6vbJcI0Hb4Eih5O ro3JFQOMBfEw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,331,1583222400"; d="scan'208";a="432531827" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga005.jf.intel.com with ESMTP; 29 Apr 2020 04:45:41 -0700 Received: from fmsmsx117.amr.corp.intel.com (10.18.116.17) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 29 Apr 2020 04:45:41 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx117.amr.corp.intel.com (10.18.116.17) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 29 Apr 2020 04:45:40 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.225]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.22]) with mapi id 14.03.0439.000; Wed, 29 Apr 2020 19:45:37 +0800 From: "Dandan Bi" To: "devel@edk2.groups.io" , "abner.chang@hpe.com" CC: Gilbert Chen , Leif Lindholm , "Gao, Liming" Subject: Re: [edk2-devel] [PATCH v2 3/3] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Thread-Topic: [edk2-devel] [PATCH v2 3/3] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Thread-Index: AQHWG94GOyX4Xof+yUarIMDqPTRxtqiP/2EQ Date: Wed, 29 Apr 2020 11:45:37 +0000 Message-ID: <3C0D5C461C9E904E8F62152F6274C0BB40DDA2C1@SHSMSX104.ccr.corp.intel.com> References: <20200426144024.7265-1-abner.chang@hpe.com> <20200426144024.7265-4-abner.chang@hpe.com> In-Reply-To: <20200426144024.7265-4-abner.chang@hpe.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: dandan.bi@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Dandan Bi Thanks, Dandan > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Abner Chang > Sent: Sunday, April 26, 2020 10:40 PM > To: devel@edk2.groups.io > Cc: abner.chang@hpe.com; Gilbert Chen ; Leif > Lindholm ; Bi, Dandan ; > Gao, Liming > Subject: [edk2-devel] [PATCH v2 3/3] MdeModulePkg/DxeIplPeim : RISC-V > platform level DxeIPL >=20 > Implementation of RISC-V DxeIPL. >=20 > Signed-off-by: Abner Chang > Co-authored-by: Gilbert Chen > Reviewed-by: Leif Lindholm >=20 > Cc: Dandan Bi > Cc: Liming Gao > Cc: Leif Lindholm > Cc: Gilbert Chen > --- > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 6 +- > .../Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 74 +++++++++++++++++++ > 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 > MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c >=20 > diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > index 98bc17fc9d..3f17028546 100644 > --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > @@ -7,6 +7,7 @@ > # # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<= BR> # > Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Copyrig= ht > (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.=
> # # SPDX-License-Identifier: BSD-2-Clause-Patent #@@ -25,7 +26,7 @@ > # # The following information is for reference only and not required by = the > build tools. #-# VALID_ARCHITECTURES =3D IA32 X64 EBC (EBC is = for build > only) AARCH64+# VALID_ARCHITECTURES =3D IA32 X64 EBC (EBC is f= or > build only) AARCH64 RISCV64 # [Sources]@@ -49,6 +50,9 @@ > [Sources.ARM, Sources.AARCH64] Arm/DxeLoadFunc.c > +[Sources.RISCV64]+ RiscV64/DxeLoadFunc.c+ [Packages] > MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.decdiff --git > a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c > b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c > new file mode 100644 > index 0000000000..2ce52eb0ec > --- /dev/null > +++ b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c > @@ -0,0 +1,74 @@ > +/** @file+ RISC-V specific functionality for DxeLoad.++ Copyright (c) = 2020, > Hewlett Packard Enterprise Development LP. All rights reserved.
++ > SPDX-License-Identifier: BSD-2-Clause-Patent++**/++#include > "DxeIpl.h"++/**+ Transfers control to DxeCore.++ This function perfor= ms a > CPU architecture specific operations to execute+ the entry point of Dxe= Core > with the parameters of HobList.+ It also installs EFI_END_OF_PEI_PPI to > signal the end of PEI phase.++ @param DxeCoreEntryPoint The ent= ry > point of DxeCore.+ @param HobList The start of HobLis= t passed to > DxeCore.++**/+VOID+HandOffToDxeCore (+ IN EFI_PHYSICAL_ADDRESS > DxeCoreEntryPoint,+ IN EFI_PEI_HOB_POINTERS HobList+ )+{+ VOID > *BaseOfStack;+ VOID *TopOfStack;+ EFI_STATUS > Status;+ //+ //+ // Allocate 128KB for the Stack+ //+ BaseOfStack = =3D > AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE));+ if (BaseOfStack =3D=3D > NULL) {+ DEBUG((DEBUG_ERROR, "%a: Can't allocate memory for stack.", > __FUNCTION__));+ ASSERT(FALSE);+ }++ //+ // Compute the top of the > stack we were allocated. Pre-allocate a UINTN+ // for safety.+ //+ > TopOfStack =3D (VOID *)((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES > (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);+ TopOfStack =3D > ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);++ //+ // End of > PEI phase signal+ //+ Status =3D PeiServicesInstallPpi (&gEndOfPeiSigna= lPpi);+ > if (EFI_ERROR (Status)) {+ DEBUG((DEBUG_ERROR, "%a: Fail to signal End= of > PEI event.", __FUNCTION__));+ ASSERT(FALSE);+ }+ //+ // Update the > contents of BSP stack HOB to reflect the real stack info passed to DxeCor= e.+ > //+ UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack, > STACK_SIZE);++ DEBUG ((DEBUG_INFO, "DXE Core new stack at %x, stack > pointer at %x\n", BaseOfStack, TopOfStack));++ //+ // Transfer the cont= rol > to the entry point of DxeCore.+ //+ SwitchStack (+ > (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,+ > HobList.Raw,+ NULL,+ TopOfStack+ );+}+-- > 2.25.0 >=20 >=20 > -=3D-=3D-=3D-=3D-=3D-=3D > Groups.io Links: You receive all messages sent to this group. >=20 > View/Reply Online (#58150): https://edk2.groups.io/g/devel/message/58150 > Mute This Topic: https://groups.io/mt/73284221/1768738 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [dandan.bi@intel.com] > -=3D-=3D-=3D-=3D-=3D-=3D