From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=chasel.chiu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 91E9A21B02845 for ; Sun, 27 May 2018 19:33:51 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 May 2018 19:33:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,450,1520924400"; d="scan'208";a="62209099" Received: from pgsmsx112.gar.corp.intel.com ([10.108.55.201]) by orsmga002.jf.intel.com with ESMTP; 27 May 2018 19:33:49 -0700 Received: from pgsmsx111.gar.corp.intel.com ([169.254.2.7]) by PGSMSX112.gar.corp.intel.com ([169.254.3.76]) with mapi id 14.03.0319.002; Mon, 28 May 2018 10:33:49 +0800 From: "Chiu, Chasel" To: "Ni, Ruiyu" , "edk2-devel@lists.01.org" CC: "Zeng, Star" Thread-Topic: [PATCH 2/2] MdeModulePkg/PciBus: Do not enable MemWriteAndInvalidate bit for PCIE Thread-Index: AQHT9A+j52gAZu0NpkyqhfsIMKNduqREcE7g Date: Mon, 28 May 2018 02:33:48 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC500D3BD0@PGSMSX111.gar.corp.intel.com> References: <20180525100246.428944-1-ruiyu.ni@intel.com> <20180525100246.428944-3-ruiyu.ni@intel.com> In-Reply-To: <20180525100246.428944-3-ruiyu.ni@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.200.100 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYTZhZTZhNjEtNTc5NS00YjYxLWEzZDEtYjAyMDliY2E5MTNmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiUlUzUkE2c21POWUrRUtcL1V6a0p3VFFqWE80WVZQeFl3RG5XaTBqK3MzNHNISVBoMlNaY1QzdDUwS2RGYkpZQ2kifQ== x-ctpclassification: CTP_NT x-originating-ip: [172.30.20.206] MIME-Version: 1.0 Subject: Re: [PATCH 2/2] MdeModulePkg/PciBus: Do not enable MemWriteAndInvalidate bit for PCIE X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 May 2018 02:33:51 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu -----Original Message----- From: Ni, Ruiyu=20 Sent: Friday, May 25, 2018 6:03 PM To: edk2-devel@lists.01.org Cc: Zeng, Star ; Chiu, Chasel Subject: [PATCH 2/2] MdeModulePkg/PciBus: Do not enable MemWriteAndInvalida= te bit for PCIE Per PCIE spec, Memory Write and Invalidate is hardwired to 0b so PciBus dri= ver shouldn't write 1b to it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Star Zeng Cc: Chasel Chiu --- MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeMod= ulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index 81171c82d9..6f3d1bebc6 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -1,7 +1,7 @@ /** @file PCI emumeration support functions implementation for PCI Bus module. =20 -Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
(C) Copyright 2015 Hewlett Packard Enterprise Development LP
This pro= gram and the accompanying materials are licensed and made available under = the terms and conditions of the BSD License @@ -1254,9 +1254,11 @@ Determin= eDeviceAttribute ( PciSetDeviceAttribute (PciIoDevice, OldCommand, OldBridgeControl, EFI_= SET_ATTRIBUTES); =20 // - // Enable other supported attributes but not defined in PCI_IO_PROTOCO= L - // - PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_MEMORY_WRITE= _AND_INVALIDATE); + // Enable other PCI supported attributes but not defined in PCI_IO_PRO= TOCOL + // For PCI Express devices, Memory Write and Invalidate is hardwired t= o 0b so only enable it for PCI devices. + if (!PciIoDevice->IsPciExp) { + PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_MEMORY_WRI= TE_AND_INVALIDATE); + } } =20 FastB2BSupport =3D TRUE; -- 2.16.1.windows.1