From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=chasel.chiu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 982932194D3AE for ; Thu, 11 Oct 2018 06:56:48 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2018 06:56:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,368,1534834800"; d="scan'208";a="99394294" Received: from kmsmsx153.gar.corp.intel.com ([172.21.73.88]) by orsmga002.jf.intel.com with ESMTP; 11 Oct 2018 06:56:46 -0700 Received: from pgsmsx111.gar.corp.intel.com ([169.254.2.202]) by KMSMSX153.gar.corp.intel.com ([169.254.5.48]) with mapi id 14.03.0319.002; Thu, 11 Oct 2018 21:56:45 +0800 From: "Chiu, Chasel" To: "Yao, Jiewen" CC: "Desimone, Nathaniel L" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH] IntelFsp2Pkg: Support FSP API mode indicator Thread-Index: AQHUYWdaF0vT4n6lCEaKRjF+fJJja6UZhzmAgACJdHA= Date: Thu, 11 Oct 2018 13:56:45 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC5019D9F4@PGSMSX111.gar.corp.intel.com> References: <20181011133518.13284-1-chasel.chiu@intel.com> <74D8A39837DF1E4DA445A8C0B3885C503ADDFD0B@shsmsx102.ccr.corp.intel.com> In-Reply-To: <74D8A39837DF1E4DA445A8C0B3885C503ADDFD0B@shsmsx102.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZWJlNzA0ZGItMDVhMi00NzVkLWFmMDYtZWI0OWExOWZlOGQ1IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiQzMwTTFpT0lsdW1DMXhwbjBoTTFUdmhBcTJUelBsSlM4ZHZpZkZIeDN3SHVKSmpTdWt5YTdIMlJMTHZnR2t6aSJ9 x-ctpclassification: CTP_NT x-originating-ip: [172.30.20.206] MIME-Version: 1.0 Subject: Re: [PATCH] IntelFsp2Pkg: Support FSP API mode indicator X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 11 Oct 2018 13:56:48 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Jiewen, This one just adding a new field in FspGlobalData structure which never bee= n consumed in current code base. I'm checking if we should combine DISPATCH mode support code together inste= ad of just header change. Thanks! Chasel -----Original Message----- From: Yao, Jiewen=20 Sent: Thursday, October 11, 2018 9:41 PM To: Chiu, Chasel ; edk2-devel@lists.01.org Cc: Desimone, Nathaniel L Subject: RE: [PATCH] IntelFsp2Pkg: Support FSP API mode indicator Thanks Chasel. I suggest we test the real function besides just pass build. Please make sure your test below combination: 1) FSP wrapper with this change + FSP binary with this change. 2) FSP wrapper with this change + FSP binary without this change. Thank you Yao Jiewen > -----Original Message----- > From: Chiu, Chasel > Sent: Thursday, October 11, 2018 9:35 PM > To: edk2-devel@lists.01.org > Cc: Yao, Jiewen ; Desimone, Nathaniel L=20 > ; Chiu, Chasel > Subject: [PATCH] IntelFsp2Pkg: Support FSP API mode indicator >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1241 >=20 > FSP will support both API and DISPATCH mode and require one field from=20 > Global Data Structure to tell which mode is selected by boot loader. > Use one reserved byte for FSP API mode indicator - FspApiModeEnabled=20 > and maintain backward compatibility: > 1. If platform FSP supports DISPATCH mode, it must > initialize this new field. > 2. If platform FSP does not support DISPATCH mode, > this new field has no effect/not used. >=20 > Test: Verified compiling without issue. >=20 > Cc: Jiewen Yao > Cc: Desimone Nathaniel L > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Chasel Chiu > --- > IntelFsp2Pkg/Include/FspGlobalData.h | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) >=20 > diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h > b/IntelFsp2Pkg/Include/FspGlobalData.h > index 7de26606a7..ccc9ecd78a 100644 > --- a/IntelFsp2Pkg/Include/FspGlobalData.h > +++ b/IntelFsp2Pkg/Include/FspGlobalData.h > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2014 - 2016, Intel Corporation. All rights=20 > reserved.
> + Copyright (c) 2014 - 2018, Intel Corporation. All rights=20 > + reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of=20 > the BSD License > which accompanies this distribution. The full text of the license=20 > may be found at @@ -54,7 +54,8 @@ typedef struct { > VOID *MemoryInitUpdPtr; > VOID *SiliconInitUpdPtr; > UINT8 ApiIdx; > - UINT8 Reserved3[31]; > + UINT8 FspApiModeEnabled; // 1: API mode; 0: > DISPATCH mode > + UINT8 Reserved3[30]; > UINT32 PerfSig; > UINT16 PerfLen; > UINT16 Reserved4; > -- > 2.13.3.windows.1