From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.136; helo=mga12.intel.com; envelope-from=chasel.chiu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 308682117AE61 for ; Tue, 23 Oct 2018 17:12:37 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Oct 2018 17:12:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,418,1534834800"; d="scan'208";a="102075590" Received: from kmsmsx151.gar.corp.intel.com ([172.21.73.86]) by orsmga001.jf.intel.com with ESMTP; 23 Oct 2018 17:12:35 -0700 Received: from pgsmsx111.gar.corp.intel.com ([169.254.2.202]) by KMSMSX151.gar.corp.intel.com ([169.254.10.74]) with mapi id 14.03.0319.002; Wed, 24 Oct 2018 08:12:34 +0800 From: "Chiu, Chasel" To: "afish@apple.com" CC: "edk2-devel@lists.01.org" , "Yao, Jiewen" Thread-Topic: [edk2] [PATCH v2] IntelFsp2Pkg: FSP should not override IDT Thread-Index: AQHUarORbAK6dKdHX0G9hWKzOrgDIqUsGvqAgAFq83A= Date: Wed, 24 Oct 2018 00:12:33 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC501A75D8@PGSMSX111.gar.corp.intel.com> References: <20181023093330.11468-1-chasel.chiu@intel.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiM2JiY2NkZmYtMDNlZS00YmFmLWFkOWMtYjljZDJkZTdjN2E2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiNEZtVVlacDZPZWJhZFF1eVhrb2hVR3lnbmNaN0J0aTVMM0RZU3R4cmpTXC82ZVQ1RUM1Q2NWVVZTTlJ5MkY0SlgifQ== x-ctpclassification: CTP_NT x-originating-ip: [172.30.20.205] MIME-Version: 1.0 Subject: Re: [PATCH v2] IntelFsp2Pkg: FSP should not override IDT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Oct 2018 00:12:37 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hello, Please see my reply below inline. Thanks! Chasel -----Original Message----- From: afish@apple.com [mailto:afish@apple.com]=20 Sent: Tuesday, October 23, 2018 6:29 PM To: Chiu, Chasel Cc: edk2-devel@lists.01.org; Yao, Jiewen Subject: Re: [edk2] [PATCH v2] IntelFsp2Pkg: FSP should not override IDT > On Oct 23, 2018, at 2:33 AM, Chasel, Chiu wrote: >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1265 >=20 > FSP should not override IDT table when it is initialized by boot=20 > loader. IDT should be re-initialized in FSP only when it is invalid. > To mitigate temporary memory usage a PCD PcdFspMaxInterruptSupported=20 > created for platform to decide how many interrupts the FSP IDT table=20 > can support. >=20 > Test: Verified on internal platform and boots successfully. >=20 > Cc: Jiewen Yao > Cc: Desimone Nathaniel L > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Chasel Chiu > --- > IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 1 + > IntelFsp2Pkg/FspSecCore/SecMain.c | 24 +++++++++++++++++++----- > IntelFsp2Pkg/FspSecCore/SecMain.h | 6 ++---- > IntelFsp2Pkg/IntelFsp2Pkg.dec | 4 ++++ > 4 files changed, 26 insertions(+), 9 deletions(-) >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf=20 > b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > index c61af10b8a..dafe6f5993 100644 > --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > @@ -62,6 +62,7 @@ > gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUME= S > gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUME= S > gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUME= S > + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## CONSUM= ES >=20 > [Ppis] > gEfiTemporaryRamSupportPpiGuid ## PRODUCES > diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c=20 > b/IntelFsp2Pkg/FspSecCore/SecMain.c > index 37fd4dfdeb..ddbfc4fcdf 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecMain.c > +++ b/IntelFsp2Pkg/FspSecCore/SecMain.c > @@ -70,6 +70,7 @@ SecStartup ( > UINT32 Index; > FSP_GLOBAL_DATA PeiFspData; > UINT64 ExceptionHandler; > + UINTN IdtSize; >=20 > // > // Process all libraries constructor function linked to SecCore. > @@ -98,13 +99,26 @@ SecStartup ( > // | | > // |-------------------|----> TempRamBase > IdtTableInStack.PeiService =3D NULL; > - ExceptionHandler =3D FspGetExceptionHandler(mIdtEntryTemplate); > - for (Index =3D 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) { > - CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&ExceptionH= andler, sizeof (UINT64)); > + AsmReadIdtr (&IdtDescriptor); > + if ((IdtDescriptor.Base =3D=3D 0) && (IdtDescriptor.Limit =3D=3D 0xFFF= F)) { Are these architectural value at reset? Thanks, Andrew Fish Chasel: Yes, these are default values from reset. > + ExceptionHandler =3D FspGetExceptionHandler(mIdtEntryTemplate); > + for (Index =3D 0; Index < FixedPcdGet8(PcdFspMaxInterruptSupported);= Index ++) { > + CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&Exceptio= nHandler, sizeof (UINT64)); > + } > + IdtSize =3D sizeof (IdtTableInStack.IdtTable); } else { > + if (IdtDescriptor.Limit + 1 > sizeof (IdtTableInStack.IdtTable)) { > + // > + // ERROR: IDT table size from boot loader is larger than FSP can s= upport, DeadLoop here! > + // > + CpuDeadLoop(); > + } else { > + IdtSize =3D IdtDescriptor.Limit + 1; > + } > + CopyMem ((VOID *) (UINTN) &IdtTableInStack.IdtTable, (VOID *)=20 > + IdtDescriptor.Base, IdtSize); > } > - > IdtDescriptor.Base =3D (UINTN) &IdtTableInStack.IdtTable; > - IdtDescriptor.Limit =3D (UINT16)(sizeof (IdtTableInStack.IdtTable) -=20 > 1); > + IdtDescriptor.Limit =3D (UINT16)(IdtSize - 1); >=20 > AsmWriteIdtr (&IdtDescriptor); >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.h=20 > b/IntelFsp2Pkg/FspSecCore/SecMain.h > index 291bc5ca5c..19ac2fbfc1 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecMain.h > +++ b/IntelFsp2Pkg/FspSecCore/SecMain.h > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2014 - 2016, Intel Corporation. All rights=20 > reserved.
> + Copyright (c) 2014 - 2018, Intel Corporation. All rights=20 > + reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the B= SD License > which accompanies this distribution. The full text of the license=20 > may be found at @@ -29,8 +29,6 @@ #include =20 > #include >=20 > -#define SEC_IDT_ENTRY_COUNT 34 > - > typedef VOID (*PEI_CORE_ENTRY) ( \ > IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData, \ > IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList \ @@ -38,7 +36,7 @@=20 > typedef VOID (*PEI_CORE_ENTRY) ( \ >=20 > typedef struct _SEC_IDT_TABLE { > EFI_PEI_SERVICES *PeiService; > - UINT64 IdtTable[SEC_IDT_ENTRY_COUNT]; > + UINT64 IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported)]= ; > } SEC_IDT_TABLE; >=20 > /** > diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec=20 > b/IntelFsp2Pkg/IntelFsp2Pkg.dec index 5b037d65e2..50496241da 100644 > --- a/IntelFsp2Pkg/IntelFsp2Pkg.dec > +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec > @@ -86,6 +86,10 @@ > # x % of FSP temporary memory will be used for heap > # (100 - x) % of FSP temporary memory will be used for stack > gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage | 50| UI= NT8|0x10000004 > + # > + # Maximal Interrupt supported in IDT table. > + # > + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported | 34| U= INT8|0x10000005 >=20 > [PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx] > gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength=20 > |0x00100000|UINT32|0x46530000 > -- > 2.13.3.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel