From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.24; helo=mga09.intel.com; envelope-from=chasel.chiu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 16422211E9FC5 for ; Mon, 1 Apr 2019 18:11:38 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Apr 2019 18:11:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,298,1549958400"; d="scan'208";a="160474191" Received: from pgsmsx105.gar.corp.intel.com ([10.221.44.96]) by fmsmga001.fm.intel.com with ESMTP; 01 Apr 2019 18:11:37 -0700 Received: from pgsmsx111.gar.corp.intel.com ([169.254.2.237]) by PGSMSX105.gar.corp.intel.com ([169.254.4.121]) with mapi id 14.03.0415.000; Tue, 2 Apr 2019 09:10:21 +0800 From: "Chiu, Chasel" To: "Kubacki, Michael A" , "edk2-devel@lists.01.org" CC: "Sinha, Ankit" , "Desimone, Nathaniel L" , "Gao, Liming" , "Kinney, Michael D" Thread-Topic: [edk2-platforms][PATCH v1 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map update Thread-Index: AQHU6Bl1jwfUTvAI40qTviaksXp2waYoEWSA Date: Tue, 2 Apr 2019 01:10:21 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC502A42CB@PGSMSX111.gar.corp.intel.com> References: <20190331232740.16872-1-michael.a.kubacki@intel.com> <20190331232740.16872-3-michael.a.kubacki@intel.com> In-Reply-To: <20190331232740.16872-3-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYjBmMzgzNDEtYTk5MS00ZDIzLTlhZjEtMjRiZTA4ZjEzNGRmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiSGF2dEcyWXA3VVFKZHEzM0UzdDFaczBuZkx2S0FYRURqK0F5OHNkQ2p2VDNkMTJ6cE1kb2h0NzZYNzR0RjNlUSJ9 x-ctpclassification: CTP_NT x-originating-ip: [172.30.20.206] MIME-Version: 1.0 Subject: Re: [edk2-platforms][PATCH v1 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map update X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 02 Apr 2019 01:11:39 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu > -----Original Message----- > From: Kubacki, Michael A > Sent: Monday, April 1, 2019 7:28 AM > To: edk2-devel@lists.01.org > Cc: Sinha, Ankit ; Desimone, Nathaniel L > ; Chiu, Chasel ; G= ao, > Liming ; Kinney, Michael D > > Subject: [edk2-platforms][PATCH v1 2/3] ClevoOpenBoardPkg/N1xxWU: Flash > map update >=20 > Updates the total BIOS flash image size to 0x5E0000. This size matches th= e BIOS > region size already configured in the SPI flash descriptor. >=20 > To write an image produced from the N1xxWU board build, write the N1XXWU.= fd > file (~6 MB) to the beginning of the BIOS region in the SPI flash (curren= tly > 0x220000). >=20 > Always back up the original SPI flash image. These offsets and sizes are = subject to > change over time. >=20 > Cc: Ankit Sinha > Cc: Nate DeSimone > Cc: Chasel Chiu > Cc: Liming Gao > Cc: Michael D Kinney > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Michael Kubacki > --- > .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc | 2 +- > .../N1xxWU/Include/Fdf/FlashMapInclude.fdf | 44 > +++++++++++----------- > .../Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat | 4 +- > 3 files changed, 26 insertions(+), 24 deletions(-) >=20 > diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc > b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc > index 81487ed58d..2116c48fc0 100644 > --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc > +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc > @@ -55,7 +55,7 @@ > # > # Default value for OpenBoardPkg.fdf use > # > - DEFINE BIOS_SIZE_OPTION =3D SIZE_70 > + DEFINE BIOS_SIZE_OPTION =3D SIZE_60 >=20 >=20 > ################################################################ > ################ > # > diff --git > a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude. > fdf > b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude. > fdf > index a727eb3b83..423c6b18f5 100644 > --- > a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude. > fdf > +++ > b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclud > +++ e.fdf > @@ -14,39 +14,41 @@ > ## >=20 >=20 > #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D# > -# 8 M BIOS - for FSP wrapper > +# 6 M BIOS - for FSP wrapper >=20 > #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D# > -DEFINE FLASH_BASE =3D = 0xFF800000 # > -DEFINE FLASH_SIZE =3D = 0x00800000 # > +DEFINE FLASH_BASE =3D = 0xFFA20000 # > +DEFINE FLASH_SIZE =3D = 0x005E0000 # > DEFINE FLASH_BLOCK_SIZE =3D = 0x00010000 > # > -DEFINE FLASH_NUM_BLOCKS =3D > 0x00000080 # > +DEFINE FLASH_NUM_BLOCKS =3D > 0x0000005E # >=20 > #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D# >=20 > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset =3D > 0x00000000 # Flash addr (0xFF800000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset =3D > 0x00000000 # Flash addr (0xFFA20000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize =3D > 0x00040000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D > 0x00000000 # Flash addr (0xFF800000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D > 0x00000000 # Flash addr (0xFFA20000) > SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D > 0x0001E000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D > 0x0001E000 # Flash addr (0xFF81E000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D > +0x0001E000 # Flash addr (0xFFA3E000) > SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > =3D 0x00002000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D > 0x00020000 # Flash addr (0xFF820000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D > 0x00020000 # Flash addr (0xFFA40000) > SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D > 0x00020000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D > 0x00040000 # Flash addr (0xFF840000) > +SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset =3D > 0x00040000 # Flash addr (0xFFA60000) > +SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize =3D > 0x00010000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D > 0x00050000 # Flash addr (0xFFA70000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D > 0x00060000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D > 0x000A0000 # Flash addr (0xFF8A0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D > 0x000B0000 # Flash addr (0xFFAD0000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D > 0x00070000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D > 0x00110000 # Flash addr (0xFF910000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D > 0x00120000 # Flash addr (0xFFB40000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D > 0x00090000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D > 0x001A0000 # Flash addr (0xFF9A0000) > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D > 0x001E0000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D > 0x00380000 # Flash addr (0xFFB80000) > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D > 0x00180000 # > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D > 0x00500000 # Flash addr (0xFFD00000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D > 0x001B0000 # Flash addr (0xFFBD0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D > 0x00140000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D > 0x002F0000 # Flash addr (0xFFD10000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D > 0x000B0000 # > +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D > 0x003A0000 # Flash addr (0xFFDC0000) > SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > 0x000A0000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D > 0x005A0000 # Flash addr (0xFFDA0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D > 0x00440000 # Flash addr (0xFFE60000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D > 0x00060000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D > 0x00600000 # Flash addr (0xFFE00000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D > 0x004A0000 # Flash addr (0xFFEC0000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D > 0x000BC000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D > 0x006BC000 # Flash addr (0xFFEBC000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D > 0x0055C000 # Flash addr (0xFFF7C000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D > 0x00004000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D > 0x006C0000 # Flash addr (0xFFEC0000) > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D > 0x00140000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D > 0x00560000 # Flash addr (0xFFF80000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D > 0x00080000 # > diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat > b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat > index c09d2d5b16..c3360403f1 100644 > --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat > +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat > @@ -202,8 +202,8 @@ cl >=20 > @set BIOS_SIZE_OPTION=3D >=20 > -@REM default size option is 7M > -@set BIOS_SIZE_OPTION=3D-DBIOS_SIZE_OPTION=3DSIZE_70 > +@REM default size option is 6M > +@set BIOS_SIZE_OPTION=3D-DBIOS_SIZE_OPTION=3DSIZE_60 >=20 > :BiosSizeDone > @echo BIOS_SIZE_OPTION=3D%BIOS_SIZE_OPTION% > -- > 2.16.2.windows.1